CN2935475Y - Semiconductor wafer with standby element - Google Patents
Semiconductor wafer with standby element Download PDFInfo
- Publication number
- CN2935475Y CN2935475Y CN 200620123997 CN200620123997U CN2935475Y CN 2935475 Y CN2935475 Y CN 2935475Y CN 200620123997 CN200620123997 CN 200620123997 CN 200620123997 U CN200620123997 U CN 200620123997U CN 2935475 Y CN2935475 Y CN 2935475Y
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- metal
- spare part
- semiconductor wafer
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Abstract
The utility model provides a semiconductor wafer with a spare element, which comprises a base, a spare element installed upon the base and a plurality of metal layers and metal holes are piled up on an input and output port. The metal layer on the outermost layer of the substrate is the top level metal layer, through which the input and output port is connected to a system voltage or a grounded voltage. The utility model only needs to modify a few top level metal layers, owing to the application of the top level metal as the contact at the input and output port, thus greatly saving the cost.
Description
Technical field
The utility model is about a kind of semiconductor device, especially in regard to a kind of semiconductor device with spare part.
Background technology
In the design phase of integrated circuit, can avoid the mistake that designs in order to make product, be necessary to test for the sample of designing, and further debug and modification, for example utilize newly-increased (deletion) element or cut-out (connecting) ways of connecting.
Because after integrated circuit (IC) design finishes, the inevitable logical problem logic function of original design (or want afterwards to change) is arranged unavoidably, when needing the temporary changes design, because integrated circuit can't additionally increase element again.Therefore, integrated circuit is when layout, and except the logic element (standard cell) that standard is arranged, general designer can be with in the pre-configured layout of advancing integrated circuit of a plurality of spare parts (sp are cell), to be used for revising the mistake in the design.Spare part (spare cell) can be the logic element of part in the standard component, and it is also therefore the same on the structure, difference between the two only is that its signal input part does not link to each other with other any unit with output, and be connected to system voltage (power) or earthed voltage (ground), therefore lose logic function, but this does not influence the general logic operation result of standard component in the integrated circuit (IC) design.
Please refer to Fig. 1, is the debug program that shows general integrated circuit, debug the method for normal use then comprise design alteration (engineering change order, ECO) and electron beam (fiber ion beams, FIB) debug.As shown in Figure 1, when integrated circuit (IC) design finishes 110, carry out debug 120 after after tested, this moment can be earlier via electron beam debug 130 checkings, or directly with design alteration 140.When verify back 150 design alterations 140 of carrying out follow-up integrated circuit of debug success, back 160 designs 170 of finishing integrated circuit of debug success with electron beam debug 130.
Electron beam (FIB) and design alteration (ECO) change logical course and can only utilize metal level to do to reconnect on demand get final product, or use the logic behaviour of spare part to add the pattern that changes the metal level connection and finish.In general, the method of electron beam (FlB) need be destroyed wafer, finds the position in suitable space to dig the metal of revising to desire downwards, above except other layers metal can not be arranged, also enough distances must be arranged apart from the next door metal, carry out chemical etching again and cut to do and be connected with metal deposition.Electron beam (FIB) can't change the structure of basalis (baselayer) and can only change metal level, therefore if will utilize spare part to do electron beam (FIB) debug, also just the metal connection of input/output port is done and is cut and reconnect.Design alteration (ECO) then is to remodify part light shield manufacture wafer, its method can be to increase or reduce element and metal connection, even also can replace already present element, and keep the position of most of element and only change minority logical operation function, main purpose is to keep most design characteristics in the wafer.
Yet; in order to reduce the influence of spare part to other standard component coilings in the wafer; in existing integrated circuit; the input/output port of spare part is used low order metal coiling (for example metal level 1 (metal 1) and metal level 2 (metal 2)) usually and is waited connected system voltage (power) or earthed voltage (ground); therefore; if desire utilizes spare part to carry out electron beam (FIB) or design alteration (ECO) comes debug, can be difficult to because of this restriction usually carry out.For electron beam (FIB) debug, if the metal wire low order metal of these spare part input/output ports (for example metal level 1 and metal level 2) wiring, meant too many other layers metal and may can do electron beam (FIB) debug so use spare part to come debug will not have too many space because of above coiling covers.In addition, the principle of design alteration (ECO) and electron beam (FIB) are similar, and difference is that the ECO debug can't destroy wafer, but utilize the method for revising light shield, in order to produce the wafer with different coilings.Yet tradition is used spare part when carrying out ECO essential the revise multi-layer photo-mask of low order metal as input/output port, and therefore, the light shield number of plies of modification is many more, causes the increasing degree of cost big more.
The utility model content
In existing integrated circuit, the signal contact of the input/output port of all standard components and spare part, all be defined on the coiling grid (routing grid) of low order metal level (the 1st layer of metal level), though can keep the coiling resource effectively, but influenced the ability to work of carrying out ion beam (FIB) and design alteration (ECO) execution debug so also, because when we need utilize spare part, all get the metal connecting line that cuts off lowest-order earlier and remove top high-order metal level.Therefore the purpose of this utility model is promptly providing a semiconductor device with spare part, and it is to use the signal contact of high-order metal level as the spare part input/output port, avoids existing problem.In addition, because this spare part is to use high-order metal level to be connected with system voltage or earthed voltage, can sacrifice some coiling resource of other metals, so the new stacks of metal layers stack structure (for example being the X-shape stacked structure) of the further collocation of the utility model is saved the coiling resource.
The utility model provides a kind of semiconductor device with spare part, includes a substrate, a spare part; Be disposed on this substrate, this spare part has an input/output port; And a plurality of metal levels and metal hole are stacked vertically on this input/output port, wherein to be positioned at the outermost metal level of substrate be to be high-order metal level to these a plurality of metal levels, and this input/output port is to be to make to be connected to a system voltage or earthed voltage by this high-order metal level.
Semiconductor device with spare part described in the utility model, wherein in these a plurality of metal levels, the adjacent metal layer is piled up with a stacked structure to form in twos, this stacked structure is the Design Rule that meets integrated circuit layout, as the rule of metal minimum area, minimum widith, for example be square stacked structure, strip stacked structure or X-shape stacked structure.
Semiconductor wafer with spare part described in the utility model, this substrate are the p type substrates for use silicon materials.
Semiconductor wafer with spare part described in the utility model, the stacks as high of these a plurality of metal levels are not influence power plane planning.
Semiconductor wafer with spare part described in the utility model, this spare part comprises a logic element, has logic function.
Semiconductor wafer with spare part described in the utility model, except this high-order metal level, the outer metal that surrounds of other metal level blocks layer (a metal blockagelayer).
Semiconductor wafer with spare part described in the utility model comprises n NMOS N-channel MOS N (NMOS) transistor.
Semiconductor wafer with spare part described in the utility model comprises p NMOS N-channel MOS N (PMOS) transistor.
Semiconductor wafer with spare part described in the utility model because the metal that input/output port has used high-order gets final product so only need revise the metal level on several floor heights rank as contact, provides cost savings greatly.
Description of drawings
Fig. 1 is the debug program that shows general integrated circuit.
Fig. 2 shows the described semiconductor device with spare part of the utility model one preferred embodiment, and it is the integrated circuit (6 layers of metal level of p type silicon base collocation) for 1P6M.
The schematic diagram of Fig. 3 for using the described integrated circuit of Fig. 2 to carry out ion beam and design alteration debug.
Fig. 4 is the square stacked structure that shows the described stacks of metal layers stack structure of the utility model one preferred embodiment.
Fig. 5 is the strip stacked structure that shows the described stacks of metal layers stack structure of the utility model one preferred embodiment.
Fig. 6 a is the X-shape stacked structure that shows the described stacks of metal layers stack structure of the utility model one preferred embodiment.
Fig. 6 b is the sectional structure chart of Fig. 6 a along the tangent line of A-A '.
Fig. 7 shows the integrated circuit of the gate spare part of the utility model one preferred embodiment through the Design of Digital Circuit of automatic configuration and coiling (APR).
Embodiment
According to the utility model one preferred embodiment, the semiconductor device with spare part described in the utility model can be the integrated circuit 200 (p type silicon base collocation 6 layers of metal level) of a 1P6M, as shown in Figure 2.This integrated circuit 200 includes a substrate 210, is formed with a standard component, a spare part 220 in this substrate 210.In this embodiment, spare part 220 districts comprise a n channel metal oxide semiconductor transistor (nMOStransistor); Wherein, this substrate 210 can be a p type substrate that uses silicon materials, p+ doped region 222, is positioned on the two adjacent N+ doped regions 223 with a polysilicon layer 240 (Polysilicon layer).This polysilicon layer 240 is used for forming the grid of this n NMOS N-channel MOS N, after suitably coiling connects, can be used as the input/output port of this spare part 220.On the other hand, spare part 220 districts also can comprise a p channel metal oxide semiconductor transistor (pMOS transistor), a CMOS transistor (CMOS transistor), or other semiconductor element.This spare part 220 has predetermined logic function, can be applicable to ion beam or design alteration debug processing procedure.This spare part utilizes a plurality of metal levels (ground floor metal level 251, second layer metal layer 252, three-layer metal layer 253, the 4th layer of metal level 254, layer 5 metal level 255, layer 6 metal level 256) and interlayer hole connector (via) 241,242,243,244,245 and 246 will be imported and output connects to high-order metal level (this high-order metal level is to be positioned at the outermost metal level of substrate in a plurality of metal levels), be layer 6 metal level 256 at present embodiment.The stacks as high of these a plurality of metal levels is not influence power plane planning.
A plurality of metal interlevels are with the metal interconnecting structure conducting, that is two metal interlevels make the two electrical connection with interlayer hole connector (via).In spare part 220, between input/output port, ground floor metal level 251, second layer metal layer 252, three-layer metal layer 253, the 4th layer of metal level 254, layer 5 metal level 255 and the layer 6 metal level 256, utilize interlayer hole connector (via) 241,242,243,244,245 and 246 to make its mutual electric connection respectively in regular turn.It should be noted that, in the utility model, a plurality of metal levels and metal hole are stacked vertically on an input port and the output port, and this input port and output port are to be connected to a system voltage or earthed voltage by this high-order metal level (layer 6 metal level 256).
Please refer to Fig. 3, the example that is to use the described integrated circuit 200 of Fig. 2 to carry out ion beam and design alteration debug.In the time of need enabling spare part 220 when desiring to carry out the ion beam debug, promptly utilize ion beam to cut off the junction (the 4th layer of metal level 254) of standard component and prime (or back level) circuit earlier, and being connected with the high-order metal level (layer 6 metal level 256) of ion beam cut-out spare part and system voltage or earthed voltage.Then, only need utilize design alteration that the high-order metal level (layer 6 metal level 256) of spare part is connected with prime (or back level) circuit and enable spare part 220.
Because this spare part is to use high-order metal level to be connected with system voltage or earthed voltage, can sacrifice some coiling resource of other metals, so the new stacks of metal layers stack structure (for example being the X-shape stacked structure) of the further collocation of the utility model is saved the coiling resource.
In another preferred embodiment of the utility model, be that spare part is placed in the wafer at random, and the metal wire of the power plane planning winding space that accounted for, for fear of the general coiling of influence, so then do not put down below, just standard component be placed on other locus at last as far as possible.We are example with the wafer of 6 layers of metal procedure, and its area size is 4.4e+7 μ m
2, and most of module component is the wafer of memory.All standard components and spare part have 203563, other module component sizes are not listed calculating in, it is about 76.76% that then the standard component gross area accounts for the area that can place, and totally 1890 and comprised 8 kinds of logic kenels of spare parts account for 0.9 3% of standard component sum.Then, be to utilize new stacks of metal layers stack structure to save the coiling resource in this embodiment, this new stacks of metal layers stack structure comprises square stacked structure, strip stacked structure, reaches the X-shape stacked structure, is described as follows:
The square stacked structure: as shown in Figure 4, upper strata metal and lower metal are the square-shaped metal layer, and other metal minimum ranges are more not enough on each layer metal and the grid that winds the line all around in this structure, can't arrange coiling all around.In other words, this square-shaped metal layer winding space on the grid that winds the line around having accounted for.
The strip stacked structure: as shown in Figure 5, upper strata metal and lower metal are the strip metal level, and stacked in parallel, and each metal level and top coiling metal minimum range is not enough in the structure, but left and right, below and other metals then meet.In other words, the winding space of coiling grid above this strip metal level has accounted for.
The X-shape stacked structure: shown in Fig. 6 a, putting according to each layer metal coiling characteristic, is the vertical direction coiling as M2, M4, M6, and then M3 and M5 are horizontal direction, each layer metal all have a direction can with other metal minimum range deficiencies that winds the line.In other words, accounted for the top and the winding space of right-hand coiling grid of this X-shape metal level.Please refer to Fig. 6 b, is to be the sectional structure chart of Fig. 6 a along the tangent line of A-A '.This spare part is to be a p channel metal oxide semiconductor transistor (pMOS transistor), be positioned on the n type trap, by among the figure as can be known, M1/M3 and M2/M4 direction of winding are inequality.
For making the feature of the present utility model can be clearer and more definite, below be that three kinds of stacks of metal layers stack structures described in the utility model and general standard element are compared as spare part:
When standard component is used as the spare part use, the coiling total length is 24375091.3 μ m in the wafer, and when using square stacked structure, the coiling total length is 24407661.43 μ m, increased by 0.13% altogether, if use vertical strip then to increase by 0.06%, and the decussate texture increase is minimum, has only 0.04%.To there be metal to pass through with a not enough just representative of coiling lattice spacing, say nothing of and to place metal hole and thread-changing, and no matter be strip or X-shape stacked structure, that one deck that has only a direction that each layer metal impacts, but each of square stacked structure layer metal do not wind the line and can pass through around then being, so the extra winding length that increases is the longest.Please refer to Fig. 7, be the integrated circuit of display logic door spare part through the Design of Digital Circuit of automatic configuration and coiling (APR), with this integrated circuit is example, and its input port all uses top metal level (metal 4) to connect as can be known, then is foursquare stacked structure in the circle.In addition, wind the line, except this high-order metal level, the outer metal that surrounds of other metal level can be blocked layer (a metal blockage layer) for avoiding in the APR step using the metal beyond the high-order of stacked structure.
The most significant advantage of the utility model is not need to increase extra light shield, as long as laminated metal and metal hole on the spare part input/output port, therefore the metal chance that covers above the stacked structure also tails off, it is just big more to use spare part to do FIB debug opportunity of success, solved the use standard component when spare part, too many other layers metal arranged above the cause, and the problem that can't cut off the lower-order metal easily and reconnect.In the time of will utilizing spare part to make metal ECO change logical operation function in addition, need not revise all metal levels yet, just can make the spare part input/output signal be connected to the tram, the utility model is because input/output port has used the metal of high-order as contact, get final product so only need revise the metal level on several floor heights rank, save cost greatly.In addition,, use suitable stacked structure,, then can save the coiling resource as the X-shape stacked structure though the semiconductor device with spare part described in the utility model needs to sacrifice some coiling resource of other metals.
The above only is the utility model preferred embodiment; so it is not in order to limit scope of the present utility model; any personnel that are familiar with this technology; in not breaking away from spirit and scope of the present utility model; can do further improvement and variation on this basis, so the scope that claims were defined that protection range of the present utility model is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
110: IC design
120: carry out afterwards after tested debug
130: the electron beam debug
140: design alteration
150,160: the debug success
170: finish the design of integrated circuit
200: integrated circuit
210: substrate
220: spare part
221:n type trap (n-well)
The 222:P+ doped region
The 223:N+ doped region
240: polysilicon layer
241,242,243,244,245 and 246: interlayer hole connector (via)
251: the ground floor metal level
252: the second layer metal layer
253: the three-layer metal layers
254: the four layers of metal levels
255: the layer 5 metal level
256: the layer 6 metal level
Claims (9)
1. the semiconductor wafer with spare part is characterized in that, described semiconductor wafer with spare part comprises:
One substrate;
One spare part is disposed on this substrate, and this spare part has an input/output port; And
A plurality of metal levels and metal hole are stacked vertically on this input/output port, wherein being positioned at the outermost metal level of substrate in these a plurality of metal levels is to be high-order metal level, and this input/output port is to be connected to a system voltage or earthed voltage by this high-order metal level.
2. the semiconductor wafer with spare part according to claim 1 is characterized in that, the adjacent metal layer is to constitute a square stacked structure.
3. the semiconductor wafer with spare part according to claim 1 is characterized in that, the adjacent metal layer is to constitute a strip stacked structure.
4. the semiconductor wafer with spare part according to claim 1 is characterized in that, the adjacent metal layer is to constitute an X-shape stacked structure.
5. the semiconductor wafer with spare part according to claim 1 is characterized in that, this substrate is the p type substrate for use silicon materials.
6. the semiconductor wafer with spare part according to claim 1 is characterized in that this spare part comprises a logic element.
7. the semiconductor wafer with spare part according to claim 1 is characterized in that, except this high-order metal level, the outer metal that surrounds of other metal level blocks layer.
8. the semiconductor wafer with spare part according to claim 1 is characterized in that, comprises a n channel metal oxide semiconductor transistor.
9. the semiconductor wafer with spare part according to claim 1 is characterized in that, comprises a p channel metal oxide semiconductor transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620123997 CN2935475Y (en) | 2006-07-27 | 2006-07-27 | Semiconductor wafer with standby element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620123997 CN2935475Y (en) | 2006-07-27 | 2006-07-27 | Semiconductor wafer with standby element |
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| Publication Number | Publication Date |
|---|---|
| CN2935475Y true CN2935475Y (en) | 2007-08-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620123997 Expired - Lifetime CN2935475Y (en) | 2006-07-27 | 2006-07-27 | Semiconductor wafer with standby element |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111063671A (en) * | 2019-12-05 | 2020-04-24 | 珠海格力电器股份有限公司 | Chip |
| CN113764410A (en) * | 2020-06-04 | 2021-12-07 | 上海复旦微电子集团股份有限公司 | Semiconductor unit device |
| CN116505904A (en) * | 2023-06-29 | 2023-07-28 | 睿思芯科(深圳)技术有限公司 | Wire-wound based delay unit |
-
2006
- 2006-07-27 CN CN 200620123997 patent/CN2935475Y/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111063671A (en) * | 2019-12-05 | 2020-04-24 | 珠海格力电器股份有限公司 | Chip |
| CN113764410A (en) * | 2020-06-04 | 2021-12-07 | 上海复旦微电子集团股份有限公司 | Semiconductor unit device |
| CN113764410B (en) * | 2020-06-04 | 2024-03-26 | 上海复旦微电子集团股份有限公司 | Semiconductor unit device |
| CN116505904A (en) * | 2023-06-29 | 2023-07-28 | 睿思芯科(深圳)技术有限公司 | Wire-wound based delay unit |
| CN116505904B (en) * | 2023-06-29 | 2023-09-29 | 睿思芯科(深圳)技术有限公司 | Wire-wound based delay unit |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070815 |
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| EXPY | Termination of patent right or utility model |