CN113764410A - Semiconductor unit device - Google Patents

Semiconductor unit device Download PDF

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Publication number
CN113764410A
CN113764410A CN202010501168.6A CN202010501168A CN113764410A CN 113764410 A CN113764410 A CN 113764410A CN 202010501168 A CN202010501168 A CN 202010501168A CN 113764410 A CN113764410 A CN 113764410A
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China
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interconnection line
metal interconnection
metal
configurable
tube
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CN202010501168.6A
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CN113764410B (en
Inventor
李卿
刘红霞
曹鹏辉
黄高中
徐烈伟
俞军
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Shanghai Fudan Microelectronics Group Co Ltd
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Shanghai Fudan Microelectronics Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A semiconductor cell device, comprising: the power supply circuit comprises a power supply area, a PMOS (P-channel metal oxide semiconductor) tube, an NMOS (N-channel metal oxide semiconductor) tube, a grounding area, an output end and a metal connecting layer, wherein the metal connecting layer comprises a first metal interconnecting wire and a second metal interconnecting wire, the source electrode of the PMOS tube is coupled with the power supply area, and the grid electrode of the PMOS tube is coupled with the first metal interconnecting wire; the source electrode of the NMOS tube is coupled with the grounding area, and the grid electrode of the NMOS tube is coupled with the first metal interconnection line; the output end is coupled with the second metal interconnection line; a configurable first through hole structure is arranged on the first metal interconnection line so as to connect the first metal interconnection line to a selected first object; the second metal interconnection line is provided with a configurable second through hole structure so as to connect the second metal interconnection line to a selected second object, so that the second object is conducted with the output end. According to the scheme, when the output logic of the semiconductor unit device needs to be changed after tape-out, ECO winding is not needed, the output logic of the semiconductor unit device can be changed, and therefore ECO cost can be reduced.

Description

Semiconductor unit device
Technical Field
The embodiment of the invention relates to the field of semiconductors, in particular to a semiconductor unit device.
Background
The chip often has some fixed logic codes inside, such as a Read Only Memory (ROM) Self Test (BIST) check code, a device ID number, version information, and the like. These fixed logic encodings map RTL 1 'b 1/1' b0 to standard Cell libraries for output 1 'b 1 High level logic cells (Tie High cells, TIEHI) or for output 1' b0 Low level logic cells (Tie Low cells, TIELO) cells.
Typically, these codes have many intermediate versions that cannot be finally fixed until the stream slice. In the conventional TIEHI/TIELO unit, since the positions of the pins of the back-end layout are different, after a front-end engineer changes the logic, the back-end engineer is required to perform an Engineering Change Order (ECO) winding to complete the whole replacement work. Meanwhile, because the TIEHI/TIELO units in the standard cell library are not compatible in layout, if the logic needs to be changed again after tape-out, the ECO cost is high.
Disclosure of Invention
The embodiment of the invention solves the technical problem that the logic needs to be changed again after the tape-out, and the ECO cost is higher.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor unit device, including: the power supply comprises a power supply area, a PMOS (P-channel metal oxide semiconductor) tube, an NMOS (N-channel metal oxide semiconductor) tube, a grounding area, an output end and a metal connecting layer, wherein the metal connecting layer comprises a first metal interconnecting wire and a second metal interconnecting wire, a source electrode of the PMOS tube is coupled with the power supply area, and a grid electrode of the PMOS tube is coupled with the first metal interconnecting wire; the source electrode of the NMOS tube is coupled with the grounding area, and the grid electrode of the NMOS tube is coupled with the first metal interconnection line; the output end is coupled with the second metal interconnection line; a configurable first via structure is arranged on the first metal interconnection line, and the position of the configurable first via structure is configurable so as to connect the first metal interconnection line to a selected first object; a configurable second via structure is arranged on the second metal interconnection line, and the position of the configurable second via structure is configurable to connect the second metal interconnection line to a selected second object so as to enable the second object to be conducted with the output end, wherein the first object is one of a drain electrode of the PMOS transistor and a drain electrode of the NMOS transistor, and the second object is the other one of the drain electrode of the PMOS transistor and the drain electrode of the NMOS transistor.
Optionally, the PMOS transistor active region corresponding to the PMOS transistor is located between the power supply region and the NMOS transistor active region corresponding to the NMOS transistor; the NMOS tube active region is positioned between the PMOS tube active region and the grounding region; the grid electrode of the PMOS tube divides the PMOS tube active region into a PMOS tube first active region 321 and a PMOS tube second active region; the grid electrode of the NMOS tube divides the active region of the NMOS tube into a first active region of the NMOS tube and a second active region of the NMOS tube; the first end of the first metal interconnection line is positioned above the first active area of the PMOS tube, and the second end of the first metal interconnection line is positioned above the first active area of the NMOS tube; and the first end of the second metal interconnection line is positioned above the second active area of the PMOS tube, and the second end of the second metal interconnection line is positioned above the second active area of the NMOS tube.
Optionally, the semiconductor unit device further includes: grid portion and fifth through-hole structure, wherein: the first end of the grid part is used as the grid of the PMOS tube, and the second end of the grid part is used as the grid of the NMOS tube; the metal connecting layer further comprises a seventh metal interconnecting wire, a first end of the seventh metal interconnecting wire is coupled with the first metal interconnecting wire, and a second end of the seventh metal interconnecting wire is connected with the grid part; the fifth through hole structure is arranged at the second end of the seventh metal interconnection line so as to conduct the grid electrode of the PMOS tube and the grid electrode of the NMOS tube with the first metal interconnection line.
Optionally, the configurable first via structure is disposed at the second end of the first metal interconnection line, the first active region of the NMOS transistor is conducted with the gate of the PMOS transistor, and the first active region of the NMOS transistor serves as the drain of the NMOS transistor; the configurable second through hole structure is arranged at the first end of the second metal interconnection line, a second active area of the PMOS tube is communicated with the second metal interconnection line, and the second active area of the PMOS tube is used as a drain electrode of the PMOS tube.
Optionally, the semiconductor unit device further includes: a third configurable via structure, a fourth configurable via structure, the metal connection layer further comprising: third metal interconnect, fourth metal interconnect, fifth metal interconnect, sixth metal interconnect, wherein: a first end of the third metal interconnection line is positioned above the power supply area, and a second end of the third metal interconnection line is positioned above the first active area of the PMOS tube; a first end of the fourth metal interconnection line is positioned above the power supply area, and a second end of the fourth metal interconnection line is positioned above the second active area of the PMOS tube; a first end of the fifth metal interconnection line is positioned above the first active region of the NMOS tube, and a second end of the fifth metal interconnection line is positioned above the grounding region; a first end of the sixth metal interconnection line is positioned above the second active region of the NMOS tube, and a second end of the sixth metal interconnection line is positioned above the grounding region; the position of the configurable third through hole structure is configurable, and the configurable third through hole structure is arranged at the second end of the third metal interconnection line; the position of the configurable fourth via structure is configurable, and the configurable fourth via structure is arranged at the first end of the sixth metal interconnection line.
Optionally, the configurable first via structure is disposed at a first end of the first metal interconnection line, the first active region of the PMOS transistor is in conduction with the gate of the NMOS transistor, and the first active region of the PMOS transistor serves as the drain of the PMOS transistor; the configurable second through hole structure is arranged at a second end of the second metal interconnection line, a second active area of the NMOS tube is conducted with the second metal interconnection line, and the second active area of the NMOS tube is used as a drain electrode of the NMOS tube.
Optionally, the metal connection layer further includes: third metal interconnect line, fourth metal interconnect line, fifth metal interconnect line, sixth metal interconnect line, configurable third through-hole structure, configurable fourth through-hole structure, wherein: a first end of the third metal interconnection line is positioned above the power supply area, and a second end of the third metal interconnection line is positioned above the first active area of the PMOS tube; a first end of the fourth metal interconnection line is positioned above the power supply area, and a second end of the fourth metal interconnection line is positioned above the second active area of the PMOS tube; a first end of the fifth metal interconnection line is positioned above the first active region of the NMOS tube, and a second end of the fifth metal interconnection line is positioned above the grounding region; a first end of the sixth metal interconnection line is positioned above the second active region of the NMOS tube, and a second end of the sixth metal interconnection line is positioned above the grounding region; the position of the configurable third through hole structure is configurable, and the configurable third through hole structure is arranged at the second end of the fourth metal interconnection line; the position of the configurable fourth through hole structure can be configured, and the configurable fourth through hole structure is arranged at the first end of the fifth metal interconnection line.
An embodiment of the present invention further provides another semiconductor unit device, including: high level output unit, low level output unit and metal interconnect, wherein: configurable via structures are arranged on the metal interconnection lines, and the positions of the configurable via structures can be configured so as to connect the metal interconnection lines to selected objects.
Optionally, the configurable via structure is configured to connect the metal interconnection line to the high-level output unit, or connect the metal interconnection line to the low-level output unit.
Optionally, the high-level output unit and the low-level output unit are formed on a first metal layer, and the metal interconnection line is formed on a second metal layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the semiconductor unit device includes: the power supply device comprises a power supply area, a PMOS (P-channel metal oxide semiconductor) tube, an NMOS (N-channel metal oxide semiconductor) tube, a grounding area, an output end and a metal connecting layer, wherein a source electrode of the PMOS tube is coupled with the power supply area, a grid electrode of the PMOS tube is coupled with a first metal interconnection line, a source electrode of the NMOS tube is coupled with the grounding area, a grid electrode of the NMOS tube is coupled with the first metal interconnection line, an output end of the NMOS tube is coupled with a second metal interconnection line, a configurable first through hole structure is arranged on the first metal interconnection line, and a configurable second through hole structure is arranged on the second metal interconnection line. The positions of the first through hole structure and the second through hole structure can be configured, the first metal interconnection line can be connected to a selected first object and the second metal interconnection line can be connected to a second object by configuring the positions of the first through hole structure and the second through hole structure, the first object is one of a drain electrode of the PMOS tube and a drain electrode of the NMOS tube, and the second object is the other of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube. The connection objects of the first metal interconnection lines and the connection objects of the second metal interconnection lines are adjusted by configuring the positions of the first through hole structures and the second through hole structures, and the output logics of the semiconductor unit devices are different due to the fact that the connection objects of the first metal interconnection lines and the second metal interconnection lines are different. Therefore, when the output logic of the semiconductor unit device needs to be changed after tape-out, the change of the output logic function of the semiconductor unit device can be realized only by modifying the layout of the metal connecting layer and adjusting the configuration positions of the first through hole structure and the second through hole structure, namely only by modifying one photomask layer and adjusting the positions of the configurable first through hole structure and the configurable second through hole structure, the change of the output logic of the semiconductor unit device can be realized, and because the output ends are compatible, ECO winding is not needed, so that the ECO cost is lower.
Drawings
FIG. 1 is a schematic diagram of a TIEHI unit in the prior art;
FIG. 2 is a schematic diagram of a TIELO cell in the prior art;
fig. 3 is a schematic structural view of a semiconductor unit device in an embodiment of the present invention;
fig. 4 is a corresponding circuit diagram of the semiconductor unit device shown in fig. 3;
fig. 5 is a schematic structural view of another semiconductor unit device in the embodiment of the present invention;
fig. 6 is a circuit diagram corresponding to the semiconductor unit device shown in fig. 5;
fig. 7 is a schematic structural view of still another semiconductor unit device in the embodiment of the present invention;
fig. 8 is a schematic structural view of still another semiconductor unit device in the embodiment of the present invention.
Detailed Description
As described above, referring to fig. 1, a schematic diagram of a tiell cell in the prior art is shown, and referring to fig. 2, a schematic diagram of a tiell cell in the prior art is shown, where an output pin of the tiell cell is a, as shown in fig. 1, and an output pin of the tiell cell is B, as shown in fig. 2. After the front-end engineer changes the logic, the back-end engineer is required to complete the whole replacement work by ECO winding because the pin positions of the TIEHI unit and the TIELO unit in the back-end layout are different. Meanwhile, because the layout of the TIEHI unit and the TIELO unit in the standard cell library are incompatible, for example, the connection layer, the Metal1 or other layers are incompatible, if the logic needs to be changed again after tape-out, the ECO cost is higher.
In an embodiment of the present invention, a semiconductor unit device includes: the power supply device comprises a power supply area, a PMOS (P-channel metal oxide semiconductor) tube, an NMOS (N-channel metal oxide semiconductor) tube, a grounding area, an output end and a metal connecting layer, wherein a source electrode of the PMOS tube is coupled with the power supply area, a grid electrode of the PMOS tube is coupled with a first metal interconnection line, a source electrode of the NMOS tube is coupled with the grounding area, a grid electrode of the NMOS tube is coupled with the first metal interconnection line, an output end of the NMOS tube is coupled with a second metal interconnection line, a configurable first through hole structure is arranged on the first metal interconnection line, and a configurable second through hole structure is arranged on the second metal interconnection line. The positions of the first through hole structure and the second through hole structure can be configured, the first metal interconnection line can be connected to a selected first object and the second metal interconnection line can be connected to a second object by configuring the positions of the first through hole structure and the second through hole structure, the first object is one of a drain electrode of the PMOS tube and a drain electrode of the NMOS tube, and the second object is the other of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube. The connection objects of the first metal interconnection lines and the connection objects of the second metal interconnection lines are adjusted by configuring the positions of the first through hole structures and the second through hole structures, and the output logics of the semiconductor unit devices are different due to the fact that the connection objects of the first metal interconnection lines and the second metal interconnection lines are different. Therefore, when the output logic of the semiconductor unit device needs to be changed after tape-out, the change of the output logic function of the semiconductor unit device can be realized only by modifying the layout of the metal connecting layer and adjusting the configuration positions of the first through hole structure and the second through hole structure, namely only by modifying one photomask layer and adjusting the positions of the configurable first through hole structure and the configurable second through hole structure, the change of the output logic of the semiconductor unit device can be realized, and because the output ends are compatible, ECO winding is not needed, so that the ECO cost is lower.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments accompanied with figures are described in detail below.
Referring to fig. 3, a schematic structural diagram of a semiconductor unit device according to an embodiment of the present invention is shown, and fig. 4 is a circuit diagram of the semiconductor unit device shown in fig. 3. Referring to fig. 5, a schematic structural diagram of another semiconductor unit device in an embodiment of the present invention is given. Fig. 6 is a circuit diagram corresponding to the semiconductor unit device shown in fig. 5. The structure of the semiconductor unit device will be described with reference to fig. 3 to 6.
In a specific implementation, the semiconductor cell device 30 may include: a power supply region 31(VDD), a PMOS tube, an NMOS tube, a ground region 35(GND), an output terminal 368, and a metal connection layer.
The metal connection layer may include a first metal interconnection line 361 and a second metal interconnection line 362.
The source of the PMOS transistor is coupled to the power region 31, and the gate of the PMOS transistor is coupled to the first metal interconnection line 361.
The source of the NMOS transistor is coupled to the ground region 35, and the gate of the NMOS transistor is coupled to the first metal interconnection line 361.
The output terminal 368 is coupled to the second metal interconnection line 362.
The first metal interconnection line 361 is provided with a configurable first via structure 371, and the configurable first via structure 371 is configurable in position to connect the first metal interconnection line 361 to a selected first object.
The second metal interconnection line 362 is provided with a configurable second via structure 372, the configurable second via structure 372 is configurable in position, and the second metal interconnection line 362 can be connected to a selected second object so as to make the second object conductive to the output terminal 368.
The first object is one of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube, and the second object is the other one of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube.
In an embodiment of the present invention, the first metal interconnection line 361 is connected to the drain of the NMOS transistor by configuring the position of the first via structure 371, and the second metal interconnection line 362 is connected to the drain of the PMOS transistor by configuring the position of the second via structure 372, and the output terminal 368(VOUT) outputs high level.
In another embodiment of the present invention, the first metal interconnection line 361 is connected to the drain of the PMOS transistor by configuring the position of the first via structure 371, and the second metal interconnection line 362 is connected to the drain of the NMOS transistor by configuring the position of the second via structure 372, and the output terminal 368(VOUT) outputs a low level.
As can be seen from the above, the semiconductor unit device includes: the power supply device comprises a power supply area, a PMOS (P-channel metal oxide semiconductor) tube, an NMOS (N-channel metal oxide semiconductor) tube, a grounding area, an output end and a metal connecting layer, wherein a source electrode of the PMOS tube is coupled with the power supply area, a grid electrode of the PMOS tube is coupled with a first metal interconnection line, a source electrode of the NMOS tube is coupled with the grounding area, a grid electrode of the NMOS tube is coupled with the first metal interconnection line, an output end of the NMOS tube is coupled with a second metal interconnection line, a configurable first through hole structure is arranged on the first metal interconnection line, and a configurable second through hole structure is arranged on the second metal interconnection line. The positions of the first through hole structure and the second through hole structure can be configured, the first metal interconnection line can be connected to a selected first object and the second metal interconnection line can be connected to a second object by configuring the positions of the first through hole structure and the second through hole structure, the first object is one of a drain electrode of the PMOS tube and a drain electrode of the NMOS tube, and the second object is the other of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube. And adjusting the connection objects of the first metal interconnection lines and the second metal interconnection lines by configuring the positions of the first through hole structures and the second through hole structures, wherein when the connection objects of the first metal interconnection lines and the second metal interconnection lines are different, the output logics of the semiconductor unit devices are different. Therefore, when the output logic of the semiconductor unit device needs to be changed after tape-out, the change of the output logic function of the semiconductor unit device can be realized only by modifying the layout of the metal connecting layer and adjusting the configuration positions of the first through hole structure and the second through hole structure, namely only by modifying one photomask layer and adjusting the positions of the configurable first through hole structure and the configurable second through hole structure, the change of the output logic of the semiconductor unit device can be realized, and because the output ends are compatible, ECO winding is not needed, so that the ECO cost can be reduced.
In an implementation, referring to fig. 3 and 5, the PMOS transistor active region corresponding to the PMOS transistor is located between the power region 31 and the NMOS transistor active region corresponding to the NMOS transistor. The NMOS tube active region is located between the PMOS tube active region and the grounding region 35.
The gate of the PMOS transistor divides the PMOS transistor active region into a PMOS transistor first active region 321 and a PMOS transistor second active region 322. The gate of the NMOS transistor divides the NMOS transistor active region into an NMOS transistor first active region 331 and an NMOS transistor second active region 332.
A first end of the first metal interconnection line 361 is located above the PMOS transistor first active region 321, and a second end of the first metal interconnection line 361 is located above the NMOS transistor first active region 331.
A first end of the second metal interconnection line 362 is located above the PMOS transistor second active region 322, and a second end of the second metal interconnection line 362 is located above the NMOS transistor second active region 332.
In an embodiment of the invention, referring to fig. 3, a configurable first via structure 371 is disposed at a second end of the first metal interconnection line 361, the NMOS tube first active region 331 is conducted with a gate of the PMOS tube, and the NMOS tube first active region 331 serves as a drain of the NMOS tube. A configurable second via structure 372 is disposed at a first end of the second metal interconnection line 362, the PMOS transistor second active region 322 is electrically connected to the second metal interconnection line 362, the PMOS transistor second active region 322 serves as a drain of the PMOS transistor, and at this time, the output terminal 368 outputs a high level.
In another embodiment of the present invention, referring to fig. 4, a configurable first via structure 371 is disposed at a first end of the first metal interconnection line 361, the PMOS transistor first active region 321 is in conduction with the gate of the NMOS transistor, and the PMOS transistor first active region 321 serves as the drain of the PMOS transistor. The configurable second via structure 372 is disposed at a second end of the second metal interconnection line 362, the NMOS tube second active region 332 is conducted with the second metal interconnection line 362, the NMOS tube second active region 332 serves as a drain of the NMOS tube, and at this time, the output terminal 368 outputs a low level.
In a specific implementation, the semiconductor unit device 30 may further include a gate portion and a fifth via structure 375. The first end 341 of the gate portion serves as the gate of the PMOS transistor, and the second end 342 of the gate portion serves as the gate of the NMOS transistor.
In a specific implementation, the metal connection layer may further include a seventh metal interconnection line 367, a first end of the seventh metal interconnection line 367 is coupled to the first metal interconnection line 361, and a second end of the seventh metal interconnection line 367 is connected to the gate portion; the fifth via structure 375 is disposed at the second end of the seventh metal interconnection line 367, so as to connect the gates of the PMOS transistor and the NMOS transistor to the first metal interconnection line 361.
In a specific implementation, the semiconductor cell device 30 may further include a configurable third via structure 373 and a configurable fourth via structure 374. The metal connection layer may further include: third metal interconnection lines 363, fourth metal interconnection lines 364, fifth metal interconnection lines 365, and sixth metal interconnection lines 366.
A first end of the third metal interconnection line 363 is located above the power region 31, and a second end of the third metal interconnection line 363 is located above the PMOS transistor first active region 321.
A first end of the fourth metal interconnection line 364 is located above the power region 31, and a second end of the fourth metal interconnection line 364 is located above the PMOS transistor second active region 322.
The first end of the fifth metal interconnection line 365 is located above the first active region 331 of the NMOS transistor, and the second end of the fifth metal interconnection line 365 is located above the ground region 35.
A first end of the sixth metal interconnection line 366 is located above the NMOS transistor second active region 332, and a second end of the sixth metal interconnection line 366 is located above the ground region 35.
The position of the configurable third through-hole structure 373 is configurable and the position of the configurable fourth through-hole structure 374 is configurable. When the arrangement position of the third through-hole structure 373 and the arrangement position of the fourth through-hole structure 374 are changed, the output logics of the semiconductor unit device 30 are different.
Referring to fig. 3, in an embodiment of the invention, the configurable third through hole structure 373 is disposed at the second end of the third metal interconnection line 363, so that the PMOS transistor first active region 321 and the third metal interconnection line 363 are conducted, and the first end of the third metal interconnection line 363 is conducted with the power region 31, at this time, the PMOS transistor first active region 321 serves as a source of the PMOS transistor, and correspondingly, the PMOS transistor second active region 322 serves as a drain of the PMOS transistor. A configurable fourth via structure 374 is disposed at a first end of the sixth metal interconnection line 366, so that the NMOS tube second active region 332 is conducted with the sixth metal interconnection line 366, and a second end of the sixth metal interconnection line 366 is conducted with the ground region 35, at this time, the NMOS tube second active region 332 serves as a source of the NMOS tube, and correspondingly, the NMOS tube first active region 331 serves as a drain of the NMOS tube.
Referring to fig. 4, in another embodiment of the present invention, the configurable third via structure 373 is disposed at the second end of the fourth metal interconnection line 364, so that the PMOS transistor second active region 322 is conducted with the fourth metal interconnection line 364, and the first end of the fourth metal interconnection line 364 is conducted with the power region 31, at this time, the PMOS transistor second active region 322 serves as the source of the MPOS transistor, and correspondingly, the PMOS transistor first active region 321 serves as the drain of the MPOS transistor. The configurable fourth through-hole structure 374 is disposed at the first end of the fifth metal interconnection line 365, so that the first active region 331 of the NMOS transistor is conducted with the fifth metal interconnection line 365, the second end of the fifth metal interconnection line 365 is conducted with the ground region 35, at this time, the first active region 331 of the NMOS transistor serves as the source of the NMOS transistor, and the second active region 332 of the NMOS transistor serves as the drain of the NMOS transistor.
In an embodiment of the present invention, each of the configurable first via structure 371, the configurable second via structure 372, the configurable third via structure 373, the configurable fourth via structure 374, and the fifth via structure 375 may include a via and a conductive plug disposed within a via pair.
In a specific implementation, referring to fig. 3 and fig. 4, when the output logic of the semiconductor unit device 30 is changed, the positions of the configurable first via structure 371, the configurable second via structure 372, the configurable third via structure 373, and the configurable fourth via structure 374 may be reconfigured by modifying a mask layer or modifying a metal connection layer layout.
Specifically, when the output logic of the semiconductor unit device 30 changes from the high level to the low level, the position of the configurable first via structure 371 is configured from the second end of the first metal interconnection line 361 to the first end of the first metal interconnection line 361, the position of the configurable second via structure 372 is configured from the first end of the second metal interconnection line 362 to the second end of the second metal interconnection line 362, the position of the configurable third via structure 373 is configured from the second end of the third metal interconnection line 363 to the second end of the fourth metal interconnection line 364, and the position of the configurable fourth via structure 374 is configured from the first end of the sixth metal interconnection line 366 to the first end of the fifth metal interconnection line 365, so that the output logic of the semiconductor unit device 30 can be adjusted from the high level to the low level.
Accordingly, when the output logic of the semiconductor unit device 30 changes from the low level to the high level, the position of the configurable first via structure 371 is configured from the first end of the first metal interconnection line 361 to the second end of the first metal interconnection line 361, the position of the configurable second via structure 372 is configured from the second end of the second metal interconnection line 362 to the first end of the second metal interconnection line 362, the position of the configurable third via structure 373 is configured from the second end of the fourth metal interconnection line 364 to the second end of the third metal interconnection line 363, and the position of the configurable fourth via structure 374 is configured from the first end of the fifth metal interconnection line 365 to the first end of the sixth metal interconnection line 366.
Referring to fig. 7, a schematic structural diagram of a semiconductor unit device according to still another embodiment of the present invention is shown. Referring to fig. 8, a schematic structural diagram of a semiconductor unit device according to still another embodiment of the present invention is shown. The structure of the semiconductor unit device will be described with reference to fig. 7 and 8.
In a specific implementation, the semiconductor unit device 10 may include a high-level output unit 11, a low-level output unit 12, and a metal interconnection line 13. The metal interconnection line 13 is provided with a configurable via structure 14, and the position of the configurable via structure 14 is configurable, so as to connect the metal interconnection line to a selected object by configuring the position of the configurable via structure 14.
In an implementation, the selected object may be any one of the high level output unit 11 and the low level output unit 12.
In some embodiments of the present invention, as shown in fig. 7, the configurable via structure 14 may connect the metal interconnection line 13 to the high-level output unit 11, so that the configurable via structure 14 may conduct the metal interconnection line 13 with the high-level output unit 11 to output a high level.
In other embodiments of the present invention, as shown in fig. 8, the configurable via structure 14 may connect the metal interconnection line 13 to the low-level output unit 12, so that the configurable via structure 14 conducts the metal interconnection line 13 with the low-level output unit 12 to output a low level.
In an embodiment of the present invention, the configurable VIA structure 14 may include a VIA (VIA1) and a conductive plug filled in the VIA.
When the output logic of the semiconductor unit device 10 needs to be changed after tape-out, for example, when the output logic is changed from a high level to a low level, only one mask layer needs to be modified, the configurable via structure 14 conducts the metal interconnection 13 with the high level output unit 11, and the configurable via structure 14 conducts the metal interconnection 13 with the low level output unit 12, that is, the mask layer is modified, through the position of the via structure 14, the selected object conducted with the metal interconnection 13 is the low level output unit 12 or the high level output unit 11, so as to change the output logic.
As can be seen from the above, the semiconductor unit device includes a high-level output unit, a low-level output unit, and a metal interconnection line, and the metal interconnection line is provided with a configurable via structure, and since the location of the via structure is configurable, the metal interconnection line can be connected to a selected object, for example, the via structure can be used to connect the metal interconnection line to the high-level output unit, or connect the metal interconnection line to the low-level output unit, and use the metal interconnection line as an output pin, so that compatibility of the output pin can be achieved. If the output logic needs to be changed after tape out, because the output pins are compatible, ECO winding is not needed before and after ECO, and the change of the output logic can be realized by changing a photomask layer to reconfigure the position of the through hole structure, so that the ECO cost can be reduced.
In a specific implementation, the high level output unit 11 may adopt a logic unit TIEHI for outputting 1' b1 high level in a standard cell bank. The low level output unit 12 may employ a logic cell TIELO for outputting 1' b0 low level in a standard cell library.
In one embodiment, the high output unit 11 and the low output unit 12 can be formed on the first metal layer. The metal interconnection line 13 may be formed at the second metal layer.
It should be noted that the first Metal layer in the embodiment of the present invention may be Metal 1. The second Metal layer may be Metal 2. The first Metal layer may be Metal2 and the second Metal layer may be Metal 3. In the embodiment of the present invention, the "first" in the first metal layer and the "second" in the second metal layer are only used to distinguish that the first metal layer and the second metal layer are not the same metal layer, that is, the metal layers where the high-level output unit 11 and the low-level output unit 12 are located and the metal layers formed by the metal interconnection lines 13 are different metal layers.
In an embodiment of the invention, the first metal layer and the second metal layer may be adjacent.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A semiconductor cell device, comprising: a power supply region, a PMOS tube, an NMOS tube, a ground region, an output end, and a metal connection layer including a first metal interconnection line and a second metal interconnection line,
the source electrode of the PMOS tube is coupled with the power supply area, and the grid electrode of the PMOS tube is coupled with the first metal interconnection line;
the source electrode of the NMOS tube is coupled with the grounding area, and the grid electrode of the NMOS tube is coupled with the first metal interconnection line;
the output end is coupled with the second metal interconnection line;
a configurable first via structure is arranged on the first metal interconnection line, and the position of the configurable first via structure is configurable so as to connect the first metal interconnection line to a selected first object; a configurable second via structure is arranged on the second metal interconnection line, and the position of the configurable second via structure is configurable to connect the second metal interconnection line to a selected second object so as to enable the second object to be conducted with the output end, wherein the first object is one of a drain electrode of the PMOS transistor and a drain electrode of the NMOS transistor, and the second object is the other one of the drain electrode of the PMOS transistor and the drain electrode of the NMOS transistor.
2. The semiconductor cell device of claim 1,
the PMOS tube active area corresponding to the PMOS tube is positioned between the power supply area and the NMOS tube active area corresponding to the NMOS tube;
the NMOS tube active region is positioned between the PMOS tube active region and the grounding region;
the grid electrode of the PMOS tube divides the PMOS tube active region into a PMOS tube first active region 321 and a PMOS tube second active region;
the grid electrode of the NMOS tube divides the active region of the NMOS tube into a first active region of the NMOS tube and a second active region of the NMOS tube;
the first end of the first metal interconnection line is positioned above the first active area of the PMOS tube, and the second end of the first metal interconnection line is positioned above the first active area of the NMOS tube;
and the first end of the second metal interconnection line is positioned above the second active area of the PMOS tube, and the second end of the second metal interconnection line is positioned above the second active area of the NMOS tube.
3. The semiconductor cell device of claim 2, further comprising: grid portion and fifth through-hole structure, wherein:
the first end of the grid part is used as the grid of the PMOS tube, and the second end of the grid part is used as the grid of the NMOS tube;
the metal connecting layer further comprises a seventh metal interconnecting wire, a first end of the seventh metal interconnecting wire is coupled with the first metal interconnecting wire, and a second end of the seventh metal interconnecting wire is connected with the grid part;
the fifth through hole structure is arranged at the second end of the seventh metal interconnection line so as to conduct the grid electrode of the PMOS tube and the grid electrode of the NMOS tube with the first metal interconnection line.
4. The semiconductor cell device of claim 2,
the configurable first through hole structure is arranged at the second end of the first metal interconnection line, a first active area of the NMOS tube is conducted with the grid electrode of the PMOS tube, and the first active area of the NMOS tube is used as the drain electrode of the NMOS tube;
the configurable second through hole structure is arranged at the first end of the second metal interconnection line, a second active area of the PMOS tube is communicated with the second metal interconnection line, and the second active area of the PMOS tube is used as a drain electrode of the PMOS tube.
5. The semiconductor cell device according to any one of claims 2 to 4, further comprising: a third configurable via structure, a fourth configurable via structure, the metal connection layer further comprising: third metal interconnect, fourth metal interconnect, fifth metal interconnect, sixth metal interconnect, wherein:
a first end of the third metal interconnection line is positioned above the power supply area, and a second end of the third metal interconnection line is positioned above the first active area of the PMOS tube;
a first end of the fourth metal interconnection line is positioned above the power supply area, and a second end of the fourth metal interconnection line is positioned above the second active area of the PMOS tube;
a first end of the fifth metal interconnection line is positioned above the first active region of the NMOS tube, and a second end of the fifth metal interconnection line is positioned above the grounding region;
a first end of the sixth metal interconnection line is positioned above the second active region of the NMOS tube, and a second end of the sixth metal interconnection line is positioned above the grounding region;
the position of the configurable third through hole structure is configurable, and the configurable third through hole structure is arranged at the second end of the third metal interconnection line;
the position of the configurable fourth via structure is configurable, and the configurable fourth via structure is arranged at the first end of the sixth metal interconnection line.
6. The semiconductor cell device of claim 2,
the configurable first through hole structure is arranged at a first end of the first metal interconnection line, a first active region of the PMOS tube is conducted with a grid electrode of the NMOS tube, and the first active region of the PMOS tube is used as a drain electrode of the PMOS tube;
the configurable second through hole structure is arranged at a second end of the second metal interconnection line, a second active area of the NMOS tube is conducted with the second metal interconnection line, and the second active area of the NMOS tube is used as a drain electrode of the NMOS tube.
7. The semiconductor cell device of claim 2, 3 or 6, wherein the metal connection layer further comprises: third metal interconnect line, fourth metal interconnect line, fifth metal interconnect line, sixth metal interconnect line, configurable third through-hole structure, configurable fourth through-hole structure, wherein:
a first end of the third metal interconnection line is positioned above the power supply area, and a second end of the third metal interconnection line is positioned above the first active area of the PMOS tube;
a first end of the fourth metal interconnection line is positioned above the power supply area, and a second end of the fourth metal interconnection line is positioned above the second active area of the PMOS tube;
a first end of the fifth metal interconnection line is positioned above the first active region of the NMOS tube, and a second end of the fifth metal interconnection line is positioned above the grounding region;
a first end of the sixth metal interconnection line is positioned above the second active region of the NMOS tube, and a second end of the sixth metal interconnection line is positioned above the grounding region;
the position of the configurable third through hole structure is configurable, and the configurable third through hole structure is arranged at the second end of the fourth metal interconnection line;
the position of the configurable fourth through hole structure can be configured, and the configurable fourth through hole structure is arranged at the first end of the fifth metal interconnection line.
8. A semiconductor cell device, comprising: high level output unit, low level output unit and metal interconnect, wherein:
configurable via structures are arranged on the metal interconnection lines, and the positions of the configurable via structures can be configured so as to connect the metal interconnection lines to selected objects.
9. The semiconductor unit device of claim 8, wherein the configurable via structure is to conduct the metal interconnect line with the high-level output cell or to conduct the metal interconnect line with the low-level output cell.
10. The semiconductor cell device according to claim 8, wherein the high-level output unit and the low-level output unit are formed in a first metal layer, and the metal interconnection line is formed in a second metal layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114914237A (en) * 2022-07-19 2022-08-16 北京智芯微电子科技有限公司 Layout structure of ROMKEY unit, chip layout method and chip

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030227315A1 (en) * 2002-06-11 2003-12-11 Jian-Shen Yu Level shifting circuit
US20050224982A1 (en) * 2004-04-02 2005-10-13 Kemerling James C Via configurable architecture for customization of analog circuitry in a semiconductor device
US20070109832A1 (en) * 2005-11-17 2007-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. ECO cell for reducing leakage power
CN2935475Y (en) * 2006-07-27 2007-08-15 威盛电子股份有限公司 Semiconductor wafer with standby element
US8446176B1 (en) * 2011-12-15 2013-05-21 Freescale Semiconductor, Inc. Reconfigurable engineering change order base cell
JP2013102094A (en) * 2011-11-09 2013-05-23 Renesas Electronics Corp Wiring design device, wiring design method, and program
CN103681722A (en) * 2013-12-30 2014-03-26 上海集成电路研发中心有限公司 Manufacturing method of structure of image sensor
US20170116366A1 (en) * 2015-10-26 2017-04-27 Samsung Electronics Co., Ltd. Engineering change order (eco) cell, layout thereof and integrated circuit including the eco cell
US9640522B1 (en) * 2016-04-19 2017-05-02 Qualcomm Incorporated V1 and higher layers programmable ECO standard cells
CN107017228A (en) * 2015-11-30 2017-08-04 台湾积体电路制造股份有限公司 Standard cell placement structure of integrated circuit and forming method thereof
US20170323902A1 (en) * 2016-05-06 2017-11-09 Globalfoundries Inc. Method, apparatus, and system for improved cell design having unidirectional metal layout architecture
CN206877987U (en) * 2017-06-02 2018-01-12 北京集创北方科技股份有限公司 Integrated circuit
DE102017117801A1 (en) * 2016-09-30 2018-04-05 Taiwan Semiconductor Manufacturing Co. Ltd. STANDARD CELL LAYOUT, SEMICONDUCTOR COMPONENT WITH TECHNICAL MODIFICATION INSTRUCTIONS (ECO) CELLS AND METHOD
CN109037192A (en) * 2018-08-31 2018-12-18 长鑫存储技术有限公司 Through silicon via fault tolerable circuit and method, integrated circuit
CN109756222A (en) * 2017-11-03 2019-05-14 展讯通信（上海）有限公司 A kind of level shifting circuit and chip system
TW201923448A (en) * 2017-11-07 2019-06-16 美商高通公司 Engineering change order (ECO) cell architecture and implementation

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030227315A1 (en) * 2002-06-11 2003-12-11 Jian-Shen Yu Level shifting circuit
US20050224982A1 (en) * 2004-04-02 2005-10-13 Kemerling James C Via configurable architecture for customization of analog circuitry in a semiconductor device
US20070109832A1 (en) * 2005-11-17 2007-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. ECO cell for reducing leakage power
CN2935475Y (en) * 2006-07-27 2007-08-15 威盛电子股份有限公司 Semiconductor wafer with standby element
JP2013102094A (en) * 2011-11-09 2013-05-23 Renesas Electronics Corp Wiring design device, wiring design method, and program
US8446176B1 (en) * 2011-12-15 2013-05-21 Freescale Semiconductor, Inc. Reconfigurable engineering change order base cell
CN103681722A (en) * 2013-12-30 2014-03-26 上海集成电路研发中心有限公司 Manufacturing method of structure of image sensor
US20170116366A1 (en) * 2015-10-26 2017-04-27 Samsung Electronics Co., Ltd. Engineering change order (eco) cell, layout thereof and integrated circuit including the eco cell
CN107017228A (en) * 2015-11-30 2017-08-04 台湾积体电路制造股份有限公司 Standard cell placement structure of integrated circuit and forming method thereof
US9640522B1 (en) * 2016-04-19 2017-05-02 Qualcomm Incorporated V1 and higher layers programmable ECO standard cells
US20170323902A1 (en) * 2016-05-06 2017-11-09 Globalfoundries Inc. Method, apparatus, and system for improved cell design having unidirectional metal layout architecture
DE102017117801A1 (en) * 2016-09-30 2018-04-05 Taiwan Semiconductor Manufacturing Co. Ltd. STANDARD CELL LAYOUT, SEMICONDUCTOR COMPONENT WITH TECHNICAL MODIFICATION INSTRUCTIONS (ECO) CELLS AND METHOD
CN206877987U (en) * 2017-06-02 2018-01-12 北京集创北方科技股份有限公司 Integrated circuit
CN109756222A (en) * 2017-11-03 2019-05-14 展讯通信（上海）有限公司 A kind of level shifting circuit and chip system
TW201923448A (en) * 2017-11-07 2019-06-16 美商高通公司 Engineering change order (ECO) cell architecture and implementation
CN109037192A (en) * 2018-08-31 2018-12-18 长鑫存储技术有限公司 Through silicon via fault tolerable circuit and method, integrated circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
韩江洪，吴迈，刘征宇: "一种基于ECN 的无线TCP 拥塞控制机制", 电信科学, no. 2, pages 50 - 54 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114914237A (en) * 2022-07-19 2022-08-16 北京智芯微电子科技有限公司 Layout structure of ROMKEY unit, chip layout method and chip

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