KR100443349B1 - Apparatus for semiconductor and designing mehtod thereof - Google Patents

Abstract

The present invention relates to a semiconductor technology, and in particular, to provide a semiconductor device and a method of designing a semiconductor device that can reduce the cost and process steps required for debugging in the design of the semiconductor device, the present invention for this purpose, A main logic provided on the board to perform a substantial operation; A preliminary logic integrated on the same substrate as the main logic and replacing the main logic; And a plurality of metal wires stacked in multiple layers via an insulating layer between the main logic and the preliminary logic phases, wherein the preliminary logic is connected to a voltage terminal using all of the plurality of metal wires. A semiconductor device is provided.

The present invention also provides a method of designing a semiconductor device having a plurality of metal wires, the method comprising: designing a main logic having a first connection terminal to which a predetermined metal wire is connected among the plurality of metal wires; Designing a preliminary logic having a second connection terminal connected to a voltage terminal in a form in which all metal wires used in the first connection terminal are connected; And selectively disconnecting the second metal wire of the second connection terminal forming the same layer as the first metal wire connected to the first connection terminal of the main logic to disconnect the voltage terminal and to connect the first connection of the main logic. And a debugging step of connecting the first metal wiring connected to the terminal and the second metal wiring.

Description

Semiconductor device and semiconductor device design method {Apparatus for semiconductor and designing mehtod

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a semiconductor device and a method of designing a semiconductor device that are easy to debug.

In general, semiconductors in the memory and non-memory fields are designed by computer aided design (hereinafter referred to as CAD) or by hand, and then implement a real semiconductor device through a manufacturing process. Prototypes are manufactured through an appropriate manufacturing process to verify the design and then tested to verify that the designed semiconductor device works as designed.

As a result of this test process, some of the logic and the like that make up the semiconductor device are misplaced during the design process, and often need to be replaced with other logic or additional logic.

Therefore, the above-mentioned problem is solved by additionally designing an extra preliminary logic in the semiconductor design and embedding it in the semiconductor device.

1A to 1B are schematic diagrams illustrating a schematic wiring form of a semiconductor device having three metal lines. FIG. 1A illustrates a wiring form before debugging, and FIG. 1B illustrates a wiring form after debugging. It is shown.

As shown in FIG. 1A, the semiconductor device replaces the main logic 100 when a problem occurs due to a design or process error in a part of the main logic 100 and the main logic 100 for substantially driving the device. And a plurality of preliminary logics (200-1 to 200-n) for the purpose, and the above-described main logic 100 and the preliminary logics (200a to 200n) are integrated on the same substrate so that each unit constituting them substantially. The process of forming the elements, for example, the transistors and the metal wirings 101, 102, and 103 are performed in a series of orders. Due to the nature of the process, the process of the main logic 100 or the preliminary logic 200-1 to 200-n is performed. The metal wirings 101, 102, and 103 interconnecting the input and output terminals have a series of vertical stacked structures to improve the degree of integration.

Accordingly, the pre-logics 200-1 to 200-n and the main logic 100 can both have a plurality of metal wires 101, 102, 103 arranged vertically in multiple layers, for example, '101'. 'Indicates a first metal wiring, and' 102 'indicates a second metal wiring. '103' represents third metal wirings, respectively, and in the preliminary logics 200-1 to 200-n, the second metal wiring 102 is connected to an input terminal and an output terminal thereof.

Meanwhile, each connection terminal of the preliminary logic 200-1 to 200-n, that is, the input / output terminal is connected to the ground voltage terminal GND or the power supply voltage terminal VDD, which is a preliminary logic 200-1 to 200-n. -n) is to prevent noise deterioration of the main logic 100 due to unnecessary transient current which may occur when the input terminal or the output terminal of the terminal is floating. The preliminary logics 200a to 200n are inverters. The case will be described with reference to Figs. 2A to 2B.

2A and 2B show that the PMOS transistor P1 and the NMOS transistor N1 form an inverter, and in practice, a plurality of such inverters are arranged, but only one is shown for simplicity of the drawings.

When the input terminal (IN) and output terminal (OUT) of the inverter are floating, that is, when the input terminal and output terminal are not connected to the power supply voltage terminal (VDD) or ground voltage terminal (GND), the potential level of the input terminal is logic. A state other than "0" and logic "1" is also referred to as "high impedance" state, and the PMOS transistor P1 and NMOS transistor N1 shown in FIG. 2A are completely inactive (OFF) as described above. Neither the state nor the full ON state is a "high impedance" state.

Accordingly, the PMOS transistor P1 and the NMOS transistor N1 are in an incompletely activated state to form a current path between the power supply voltage terminal VDD and the ground voltage terminal GND. Each inverter forms a current path that consumes different current depending on the potential level of the input stage. For example, since the aforementioned inverter forms a current path either instantaneously or continuously, the noise characteristic of the semiconductor device incorporating the preliminary logic is deteriorated.

Accordingly, as shown in FIG. 2B, the input terminal IN of each inverter constituting the preliminary logic is connected to the power supply voltage terminal VDD or to the ground voltage terminal GND.

Herein, the configuration of the preliminary logic inverter is exemplified, but the same applies to any logic combination generated by the coupling between the AND gate, the NAND gate, the NOR gate, the exclusive OR gate, flip-flop, and other logic circuits.

For the above reason, the plurality of preliminary logics 200-1 to 200-n shown in FIG. 1A have their input / output terminals connected to a power supply voltage terminal VDD or a ground voltage terminal GND. 101).

On the other hand, in the process of testing the prototype semiconductor chip consisting of the main logic 100 and a plurality of preliminary logic (200-1 ~ 200-n), as a result of the error is determined that the design layout should be changed, that is, debugging If necessary often occurs, for example, as shown in Figure 1b, if you want to connect the input terminal of the main logic 100 and any one of the preliminary logic 200-1, among the preliminary logic 200-1 input stage After making the connection with the power supply voltage terminal (VDD) or the ground voltage terminal (GND) of the input terminal to be disconnected, connect to the output terminal of the main logic (100).

At this time, the input terminals of the main logic 100 are connected through the third metal wiring 103, and the input terminals of the preliminary logic 200-1 are connected through the first metal wiring 101 so as to connect each other. In order to do this, the following minimum process is required.

end. Mask and series of processes for disconnecting the first metal wiring 101 connected to the input terminal of the preliminary logic 200-1 from the power supply voltage terminal VDD or the ground voltage terminal GND

I. Mask and series of processes for contacting the second metal wiring 102 of the preliminary logic 200-1

All. Mask and series of processes for forming the second metal wiring 102 of the preliminary logic 200-1

la. Mask and series of processes for contacting the third metal wiring 103 of the preliminary logic 200-1

hemp. Mask and a series of processes for forming the third metal wiring 103 connecting the input terminal of the preliminary logic 200-1 and the main logic 100 input terminal

That is, as described above, since the metal wires 101, 102, and 103 are arranged in a multi-layered structure, the third metal wire 103 at the top and the first metal wire 101 at the bottom thereof are connected to each other. In order to do this, at least five mask processes are required. An example in which the above-described main logic and preliminary logic are connected through metal wirings will be described in detail with reference to FIG. 3, which illustrates a cross-sectional view of a semiconductor device including a transistor.

Referring to FIG. 3, a field insulating film Fox is locally disposed on a substrate Sub, and is contacted through a second metal wiring 102 and a third metal wiring 103. A transistor including a contact drain (D) and a gate (G) contacted through the first metal wiring 101, that is, a preliminary logic 200-1 and a source S contacted through the second metal wiring 102. ) And a transistor including a gate (G) contacted through the drain (D) and the third metal wiring (103), that is, the main logic (100) is a main logic region (B) and a preliminary logic region (B) on the substrate (Sub). An angle is disposed in A), and a plurality of insulating layers PMD, IMD1, and IMD2 are interposed between each transistor and the metal wiring.

As described above, in order to connect the gate G, the input terminal of the preliminary logic 200a, and the gate G, the input terminal of the main logic 100, to each other, first, the first metal wiring of the preliminary logic 200-1. A mask process for separating the 101 from the power supply voltage terminal VDD or the ground voltage terminal GND is required, and the second metal wiring 102 is disposed on the first metal wiring 101 of the preliminary logic 200a. A contact mask for forming a via hole, that is, a via contact mask, is needed to connect the vias, and again, a mask for forming the second metal wiring 102, the third metal wiring 103 and the second metal. The contact mask for connecting the interconnection 102, the contact mask for connecting the second metal interconnection 102 and the third metal interconnection 103, and the gate G which is an input terminal of the preliminary logic 200-1 described above. The third metal wire contact formed through the process, that is, the third via contact 103 'is connected to the input terminal of the main logic 100 A mask for connecting with the third metal wiring 103 connected to the bit G is required.

On the other hand, the metal wiring described above shows only the minimum mask process when applied only in the case of a simple laminated structure, at least five masks are required.

On the other hand, the metal wirings 101, 102, 103 of the input or output of the preliminary logic 200-1 to be connected and the metal wirings 101, 102, 103 of the input or output of the main logic 100 to be connected If it is disposed on the same layer, the main circuit 100 and the main circuit 100 are disconnected by breaking the metal wirings 101, 1021, and 103 of the preliminary logic 200-1 connected to the power supply voltage terminal VDD or the ground voltage terminal GND. Although only one mask may be required for the connection, in practice, there is almost no debugging between metal wires having the same layer. Rather, due to high integration, the metal wires arranged in more layers than the metal wires of the three-layer structure described above are highly integrated. As it is used, the mask process due to debugging is more than necessary, which increases development time and increases the cost burden of making a mask.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problems, and provides a semiconductor device and a method of designing the semiconductor device, which can reduce the cost and process steps required for debugging in the design of the semiconductor device. The purpose.

1A to 1B are schematic diagrams showing a schematic wiring form of a semiconductor device having three metal wirings;

2A to 2B are circuit diagrams illustrating a case in which the preliminary logic is an inverter;

3 is a cross-sectional view of a semiconductor device having a transistor;

4A and 4B are schematic diagrams showing a schematic wiring form of a semiconductor device having three metal wirings according to an embodiment of the present invention;

5 is a cross-sectional view of a semiconductor device including the transistor according to FIG. 4B.

6A and 6B are schematic views showing a schematic wiring form of a semiconductor device having three metal wires according to another embodiment of the present invention;

7 is a cross-sectional view of a semiconductor device including the transistor according to FIG. 6B.

* Explanation of symbols for the main parts of the drawings

400: main logic 500-1 to 500-n: preliminary logic

401, 402, 403: metal wiring

The present invention to achieve the above object, the main logic is provided on the substrate to perform a substantial operation; A preliminary logic integrated on the same substrate as the main logic and replacing the main logic; And a plurality of metal wires stacked in multiple layers via an insulating layer between the main logic and the preliminary logic phases, wherein the preliminary logic is connected to a voltage terminal using all of the plurality of metal wires. A semiconductor device is provided.

In addition, in order to achieve the above object, the present invention provides a method of designing a semiconductor device having a plurality of metal wirings, the main logic having a first connection terminal connected to a predetermined metal wiring of the plurality of metal wirings; step; Designing a preliminary logic having a second connection terminal connected to a voltage terminal in a form in which all metal wires used in the first connection terminal are connected; And selectively disconnecting the second metal wire of the second connection terminal forming the same layer as the first metal wire connected to the first connection terminal of the main logic to disconnect the voltage terminal and to connect the first connection of the main logic. And a debugging step of connecting the first metal wiring connected to the terminal and the second metal wiring.

In order to solve the problem of debugging using a plurality of masks and a series of processes according to the debugging as described above, the present invention arranges metal wires inside a multi-layered insulating structure disposed on top of the preliminary logic. Alternatively, by simultaneously connecting to the voltage level of the ground voltage terminal, it is a technical feature to reduce the mask operation due to debugging.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. 4A and 4B are schematic diagrams showing a schematic wiring form of a semiconductor device having three metal wirings according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view of a semiconductor device including a transistor according to FIG. 4B. do.

6A and 6B are schematic views showing a schematic wiring form of a semiconductor device having three metal wirings according to another embodiment of the present invention, and FIG. 7 is a cross-sectional view of a semiconductor device including a transistor according to FIG. 6B. Shows.

As shown in FIG. 4A, the semiconductor device replaces the main logic 400 when a problem occurs due to a design or process error in a part of the main logic 400 and a part of the main logic 400 for substantially driving the device. And a plurality of preliminary logics 500-1 to 500-n, and the above-described main logic 400 and the preliminary logics 500-1 to 500-n are integrated on the same substrate. The process of forming each unit element, for example, the transistor and the metal wirings, is performed in the same manner, and the metals interconnecting the input / output terminals of the main logic 400 or the preliminary logic 500-1 to 500-n described above due to the characteristics of the process. The wirings 401, 402, and 403 are a series of vertical stacked structures, which improves the degree of integration.

Accordingly, the preliminary logics 500-1 to 500-n and the main logic 400 may both have three metal wires 401, 402, and 403 vertically arranged in a multi-layer, where '401' is a first. 1 metal wiring, '402' is the second metal wiring. '403' represents the third metal wiring, respectively.

Here, the preliminary logic 500-1 to 500-n uses all metal wirings 401, 402, and 403, with a power supply voltage terminal VDD or a ground voltage interposed therebetween with an insulating layer (not shown) therebetween. It is connected to the stage GND, which prevents deterioration of noise characteristics of the main logic 400 due to unnecessary transient current which may occur when the input terminal or the output terminal of the preliminary logic 400-1 to 400-n is floated. It is for.

On the other hand, in the process of testing a prototype semiconductor chip consisting of the main logic 400 and a plurality of preliminary logics 400-1 to 400-n, as a result of an error determination, the layout of the design must be changed, that is, debugging is performed. If necessary often occurs, for example, as shown in Figure 1b to connect the input terminal of the main logic 400 and any one of the preliminary logic 500-1, among the preliminary logic 500-1 input stage After making the connection state with the power supply voltage terminal (VDD) or the ground voltage terminal (GND) of the input terminal to be disconnected and connected to the output terminal of the main logic 400.

At this time, the input terminal of the main logic 400 is connected through the third metal wiring 403, the input terminal of the preliminary logic 400-1 is the first metal wiring 401 and the second metal wiring 402 and Since the third metal wiring 403 is connected through both, the third metal wiring 403 connected to the input terminal of the preliminary logic 400-1 and the power supply voltage terminal VDD or the ground voltage terminal GND are connected to each other. Disconnecting the, and only one of a mask and a series of processes for forming the third metal wiring 403 for connecting the input terminal of the preliminary logic 400-1 and the main logic 400 input terminal are required.

Accordingly, the mask and process steps are performed in a recurring process, compared to the prior art, in which at least five mask processes are required to connect the uppermost third metal wiring 403 and the lowermost first metal wiring 401 to each other. It will be possible to reduce the bar, it will be described in detail with reference to Figure 5 showing an example in which the above-described main logic and preliminary logic is connected through the metal wiring, respectively.

Referring to FIG. 5, a field insulating layer Fox is locally disposed on a substrate Sub and is contacted through a first metal wire 401, a second metal wire 402, and a third metal wire 403. A transistor composed of a source S, a drain D, and a gate G, that is, a preliminary logic 500-1, a source S and a drain D contacted through the second metal wiring 402. And a transistor including a gate G contacted through the third metal wiring 403, that is, the main logic 100 is disposed at each of the main logic region B and the preliminary logic region A on the substrate Sub. Insulation layers PMD, IMD1, and IMD2 are interposed between the transistors and the metal wirings.

As described above, in order to connect the gate G which is the input terminal of the preliminary logic 500-1 and the gate G which is the input terminal of the main logic 400 to each other, first, the third of the preliminary logic 500-1 may be connected. A mask for separating the metal wiring 401 from the power supply voltage terminal VDD or the ground voltage terminal GND, and connecting the metal wiring 401 to the third metal wiring 403 connected to the gate G which is an input terminal of the main logic 400. Only one is needed.

In short, the design debugging process of the semiconductor device according to the present invention described above is briefly described as follows.

In the first step, a preliminary logic in which the first connection terminal is connected to the voltage terminal is designed using all metal wirings used in the semiconductor device in series.

In the second step, a main logic having a second connection terminal connected to a metal wiring is designed.

In the third step, a prototype semiconductor device is manufactured and tested based on the layout of the semiconductor device designed for the pre- and main logic.

In the fourth step, when debugging the test result, the above-mentioned metal wiring of the preliminary logic is disconnected from the voltage wiring and the metal wiring, which is the same layer as the metal wiring of the main logic, and connected to the metal wiring of the main logic.

Through a series of processes for design debugging of the semiconductor device described above, debugging of the first designed semiconductor device is facilitated.

6A, 6B, and 7, which illustrate another embodiment of the present invention, in this embodiment, the input terminal of the main logic 400 and the input terminal of the preliminary logic 500-1 are connected to the main logic. The output terminal of the 400 and the output terminal of the preliminary logic 500-1 are added to each other, but this also requires only a series of processes including one mask as in the above-described embodiment. The same components as those in 4A, 4B, and 5 will be omitted.

Meanwhile, even if the metal wiring of the main logic to be connected other than the above-described embodiments is the second metal wiring, the mask for via contact of the third metal wiring on the second metal wiring and the via contact of the main logic described above may be formed. As a result of forming a three metal wiring and disconnecting the third metal wiring of the preliminary logic from the voltage terminal, only a series of processes including two masks including a mask for connecting with the third metal wiring of the main logic are necessary. The mask process can be reduced as compared with the prior art.

In the above-described invention, all the metal wires used in the semiconductor device are used in the preliminary logic in the design of the semiconductor device, and in this case, all the metal wires are connected to one voltage terminal, and thus, a series of processes including a mask during subsequent debugging are performed. The embodiment has been shown that the steps can be reduced and the debugging can be facilitated.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above, by having all the metal wiring used in the semiconductor device in the design of the preliminary logic for the modification of the semiconductor device, not only can easily debug the design, but also significantly reduce the process, ultimately Excellent effects can be expected to improve the price competitiveness of semiconductor devices.

Claims (5)

A main logic provided on the substrate to perform substantial operation; A preliminary logic integrated on the same substrate as the main logic and replacing the main logic; And It is provided with a plurality of metal wiring laminated in multiple layers via an insulating layer between the main logic and the pre-logic phase, And the preliminary logic is connected to a voltage terminal using all of the plurality of metal wires. The method of claim 1, And the plurality of metal wires are connected in series to the connection terminal of the preliminary logic. The method of claim 1, The voltage terminal comprises a power supply voltage terminal or a ground voltage terminal. delete In the design method of a semiconductor device having a plurality of metal wirings, Designing a main logic having a first connection terminal to which a predetermined metal wiring is connected among the plurality of metal wirings; Designing a preliminary logic having a second connection terminal connected to a voltage terminal in a form in which all metal wires used in the first connection terminal are connected; And Selectively disconnecting the second metal wiring of the second connecting terminal forming the same layer as the first metal wiring connected to the first connecting terminal of the main logic to disconnect the voltage terminal, and connecting the first connecting terminal of the main logic. A debugging step of connecting the first metal wire and the second metal wire connected to each other; Design method of a semiconductor device comprising a.