JP2002076126A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device that can make a fuse configuration correspond easily regardless of the number of layer whereupon the topmost layer wiring of a system LSI product is provided. SOLUTION: This device, in which a plurality of fuses, each consisting of a different wiring layer, are arranged hierarchically, comprises fuse selective circuits 7L, 7R for connecting these fuses to internal circuit nodes selectively, a logic signal generating circuit 3 for controlling the fuse selective circuits 7L, 7R, and a control signal generating circuit 1 for controlling the logic signal generating circuit 3. In addition, the logic of control signals 2 generated from the control signal generating circuit 1 is determined by means of a mask application step of a manufacturing process and is automatically generated at supplying of power to the product by means of a power-on reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device formed by a multilayer wiring process and having a fuse relief function in the process.

[0002]

2. Description of the Related Art Until now, the progress of high integration and high performance of a semiconductor integrated circuit device has been unavoidable, and today, a large capacity memory core (hereinafter referred to as a memory macro) and a logic circuit are mixedly mounted. Mass production of system LSIs (hereinafter, simply referred to as system LSIs) is in full swing.

In order to realize this system LSI, generally, a multi-layer wiring process of three or more layers is applied.
In order to maximize the features of the above, the number of wiring layers used by the products will be different even if the applied miniaturization process rules are the same.

A problem here is the fuse formation layer of the memory macro mounted on the system LSI as described above. The memory macro is provided for switching the connection by cutting the internal wiring for the purpose of replacing a defective memory cell with a redundant memory cell or for adjusting a voltage value generated in an internal power supply circuit. Fuse technology has been widely adopted.

[0005] When these fuses are cut by a laser trimmer or the like, the fuse to be cut is more likely to be cut near the surface of the chip, and must be formed of the uppermost wiring layer. As described above, even if the miniaturization process rule is the same, the number of wiring layers used differs depending on the product. Therefore, it is necessary to match the fuse forming layer of the memory macro with the uppermost wiring layer of each product.

FIG. 16 shows a third wiring layer (hereinafter referred to as M3).
1 shows a cross-sectional structure of a fuse portion in a conventional memory macro in which a fuse is formed. This memory macro is M3
Is applied to a product having a top layer wiring.

[0007] Both ends of the fuse 3F formed in M3 are connected to a second wiring layer (hereinafter, referred to as M2) via a third wiring layer-second wiring interlayer contact (hereinafter, referred to as V2).
2) and again, via V2, one end
The other end is connected to the first internal circuit node formed by M3, and the other end is connected to the second internal circuit node formed by M3.

FIG. 17 shows a fourth wiring layer (hereinafter, referred to as M4).
1 shows a cross-sectional structure of a fuse portion in a conventional memory macro in which a fuse is formed. This memory macro is M4
Is applied to a product having a top layer wiring. In this case, although the memory macro itself is completed by the wiring layers up to M3, the layer in which the fuse (hatched portion) is formed is M4 and is adapted to the uppermost layer wiring of the product.

Both ends of the fuse 4F formed in M4 are connected to M3 via a fourth wiring layer-third wiring interlayer contact (hereinafter, referred to as V3), and further connected to M2 via V2. Connected again, one end is connected via V2 to a first internal circuit node formed by M3, and the other end is connected to a second internal circuit node formed by M3.

As shown in FIGS. 16 and 17 described above, the fuse is formed by aligning the fuse forming layer with the uppermost wiring of each system LSI product, that is, by forming the fuse in the wiring layer closest to the chip surface. Fuse cutting with a laser trimmer or the like is facilitated.

[0011]

However, in the above-described conventional semiconductor integrated circuit device, even if the memory macros mounted on the respective system LSI products have exactly the same electrical specifications, they can be used. It is necessary to individually prepare a memory macro having a fuse forming layer corresponding to the uppermost wiring layer of each product for each LSI product.

Therefore, there is a problem that the number of types of memory macros corresponding to each of the system LSI products increases, which leads to an increase in man-hours such as design and verification and a complicated management of the types of memory macros. I was

The present invention solves the above-mentioned conventional problems. In the case of a system LSI product on which a memory macro having exactly the same electrical specifications is mounted, no matter how many wiring layers are used, a fuse is required. A memory macro whose formation layer appropriately corresponds to the number of all wiring layers can be configured, suppressing an increase in the number of types of memory macros, increasing man-hours for designing and verifying LSI products, and managing types of memory macros. To provide a semiconductor integrated circuit device capable of preventing complication of the semiconductor integrated circuit.

[0014]

In order to solve the above-mentioned problems, a semiconductor integrated circuit device according to the present invention comprises a plurality of wiring layers formed by a multi-layer wiring process, and has a fuse relief function in the process. An integrated circuit device, wherein a plurality of hierarchical fuses including a plurality of fuses formed in different wiring layers of the plurality of wiring layers are provided.

As described above, regardless of the total number of wiring layers of an LSI product, the fuse forming layer can always exist at the uppermost layer of all the wiring layers.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to a first aspect of the present invention is a semiconductor integrated circuit device having a plurality of wiring layers formed by a multi-layer wiring process and having a fuse relief function in the process. In addition, a plurality of hierarchical fuses including a plurality of fuses formed in different wiring layers from the plurality of wiring layers are provided.

According to this configuration, the fuse forming layer always exists at the uppermost layer of all the wiring layers, regardless of the total number of wiring layers of the LSI product. According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device in which a plurality of hierarchical fuses according to the first aspect are arranged so as to be overlapped with each other without any displacement between different wiring layers.

According to this configuration, a plurality of fuses can be arranged without increasing the area of the fuse forming portion formed by a single wiring layer as in the related art. According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device in which the plurality of hierarchical fuses according to the first aspect are arranged so as to be displaced from each other between different wiring layers at different levels.

According to this configuration, damage to the lower fuse that occurs when the fuse formed in the uppermost wiring layer is cut by a laser trimmer or the like is eliminated. Claim 4
The semiconductor integrated circuit device according to the present invention has a configuration in which the plurality of hierarchical fuses according to the first aspect of the present invention are arranged so as to be displaced from each other in a stepwise manner between different wiring layers.

According to this structure, damage to the lower fuse caused when the fuse formed in the uppermost wiring layer is cut by a laser trimmer or the like is eliminated, and
All of the plurality of fuses forming one hierarchical fuse are horizontally shifted from each other, facilitating the layout of connection between each fuse terminal and an internal circuit node.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit device, the plurality of hierarchical fuses according to any one of the second to fourth aspects are respectively connected to a first internal circuit node and a second internal circuit node. A plurality of fuses formed between different wiring layers are selectively connected to the first internal circuit node and the second internal circuit node.

According to this configuration, a fuse that is effective in terms of circuit can be selected from a plurality of fuses, each of which includes a different wiring layer, based on the fuse disconnection information. Even if it is received, it has no effect on the circuit.

According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit device for selectively connecting one end of a plurality of fuses formed in different wiring layers according to the fifth aspect to a first internal circuit node. The configuration includes the first fuse selection circuit.

According to this configuration, a specific terminal is selected from a terminal group of a plurality of fuses each having a different wiring layer, and the terminal is electrically connected to the first internal circuit node.

According to a seventh aspect of the present invention, there is provided a semiconductor integrated circuit device for selectively connecting the other ends of a plurality of fuses formed in different wiring layers according to the sixth aspect to a second internal circuit node. And a second fuse selection circuit.

According to this configuration, a specific terminal is selected from another terminal group of the plurality of fuses each including a different wiring layer, and the terminal is electrically connected to the second internal circuit node.

According to an eighth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a logic signal generation circuit for generating a logic signal for controlling a selective connection of the first or second fuse selection circuit according to the sixth or seventh aspect. A configuration is provided.

According to this configuration, the fuse selection circuit is controlled by the logic signal from the logic signal generation circuit. According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit device including a control signal generation circuit for generating a control signal for controlling generation of a logic signal from the logic signal generation circuit according to the eighth aspect.

According to this configuration, the logic signal generation circuit is controlled by the control signal from the control signal generation circuit. A semiconductor integrated circuit device according to a tenth aspect is configured such that the control signal from the control signal generation circuit according to the ninth aspect is switched by a mask application step of a manufacturing process.

According to this configuration, the logic of the control signal generated from the control signal generation circuit is determined by the mask application step of the manufacturing process. A semiconductor integrated circuit device according to an eleventh aspect of the present invention controls the control signal generation circuit according to the tenth aspect based on a power-on reset signal generated when the power of the device is turned on and based on the power-on reset signal. It is configured to generate a signal.

According to this configuration, the control signal from the control signal generation circuit whose logic is determined by the mask application step of the manufacturing process is automatically generated when the power to the LSI product is turned on.

Hereinafter, a semiconductor integrated circuit device according to an embodiment of the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing an outline of a circuit configuration for selectively connecting hierarchical fuses in the semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 1, 1 is a control signal generation circuit to which a power-on reset signal POR is input, 2 is a control signal generated from the control signal generation circuit 1, 3 is a logic signal generation circuit controlled by the control signal 2, and 4 is A logic signal generated from the logic signal generation circuit 3,
Reference numeral 5 denotes a first layer fuse composed of a plurality of fuses each having a different wiring layer, 6L denotes one terminal group of the first layer fuse 5, 6R denotes another terminal group of the first layer fuse 5, and 7L denotes a first group fuse. First fuse selection circuits (L), 7R provided between the internal circuit node (11) and one terminal group 6L of the first-level fuse 5 and controlled by the logic signal 4
Is a first fuse selection circuit (R) provided between the internal circuit node (21) and the other terminal group 6R of the first hierarchical fuse 5 and controlled by the logic signal 4.

The first layer fuse 5 and the first fuse selection circuit (L) 7L and the first fuse selection circuit (R) disposed on the left and right of the first layer fuse 5 respectively.
7R is arranged in a straight line between the internal circuit node (11) and the internal circuit node (21), and similarly, in parallel with this, the second hierarchical fuse and the second fuse selection circuit (L) ) And the second fuse selection circuit (R) are arranged in a straight line between the internal circuit node (12) and the internal circuit node (22).

Similarly, in parallel with this, an n-th hierarchical fuse, an n-th fuse selection circuit (L), and an n-th fuse selection circuit (R) are connected to an internal circuit node (1n) and an internal circuit node (1n). It is arranged linearly with the node (2n).

The plurality of fuse selection circuits (L) and (R) all share a common logic signal 4.
It is configured to be controlled by FIG. 2 is a block diagram schematically showing a circuit configuration for selectively connecting hierarchical fuses in the semiconductor integrated circuit device according to the second embodiment of the present invention. The difference from FIG. 1 is that the fuse selection circuit (L)
Has been removed and the circuit has been simplified, and the terminal group 6L of the hierarchical fuse and the internal circuit node 11 are physically and electrically connected. Otherwise, the configuration is the same as that of FIG.

FIGS. 3 to 5 are diagrams schematically showing the overlapping configuration of the hierarchical fuses in the semiconductor integrated circuit devices according to the first and second embodiments of the present invention. The schematic diagram of FIG.
For example, a case is shown where a plurality of wiring layer fuses constituting one hierarchical fuse of the first to third hierarchical fuses are hierarchically arranged without any positional displacement in the horizontal direction.

FIG. 4 is a schematic view showing a state in which a plurality of wiring fuses constituting one hierarchical fuse of, for example, the first to third hierarchical fuses are hierarchically superimposed and shifted in the horizontal direction. This shows a case in which they are arranged.

The schematic diagram of FIG. 5 shows a state where a plurality of wiring layer fuses constituting one hierarchical fuse of, for example, the first to third hierarchical fuses are hierarchically overlapped in a stepwise manner and shifted in the horizontal direction. It shows the case where it is arranged with.

As shown in FIGS. 3 to 5, the hierarchical fuse may have any configuration. 6 to 8 are schematic diagrams illustrating the concept of hierarchical fuse selection switching in the semiconductor integrated circuit device according to the first embodiment of the present invention. In this case, the memory macro is a system LSI in which the uppermost layer wiring is the fourth layer, and the memory macro is
It can be mounted on both the system LSI which is the layer and the system LSI whose uppermost layer wiring is the sixth layer.

FIG. 6 is a schematic diagram showing a concept of hierarchical fuse selection switching when a memory macro is mounted on a system LSI having a sixth layer as the uppermost layer wiring. In this case, there are three fuses of the fourth layer wiring fuse, the fifth layer wiring fuse, and the sixth layer wiring fuse in the hierarchical fuse section, and the fuses disposed on the left and right sides of the hierarchical fuse section including these fuses. The selection circuit (L) and the fuse selection circuit (R) select both terminals of the sixth layer wiring fuse, which is the uppermost layer wiring fuse, respectively, so that the internal circuit node (1) is connected to the fuse selection circuit (L), Sixth
It is electrically connected to the internal circuit node (2) via the layer wiring fuse and the fuse selection circuit (R) in this order.

As a result, only the sixth layer wiring fuse, which is the uppermost layer wiring fuse, becomes electrically effective as a fuse, and the fourth layer wiring fuse and the fifth layer wiring fuse have no meaning as a fuse. Will not be.

FIG. 7 is a schematic diagram showing the concept of hierarchical fuse selection switching when a memory macro is mounted on a system LSI having a fifth layer as the uppermost layer wiring. In this case, there are two fuses, a fourth-layer wiring fuse and a fifth-layer wiring fuse, in the hierarchical fuse section. Fuse selection circuit (R)
By selecting both terminals of the fifth layer wiring fuse, which is the uppermost layer wiring fuse, respectively, the internal circuit node (1) is connected to the fuse selection circuit (L), the fifth layer wiring fuse, and the fuse selection circuit (R). Are sequentially connected to the internal circuit node (2).

As a result, only the fifth layer wiring fuse, which is the uppermost layer wiring fuse, becomes electrically effective as a fuse, and the fourth layer wiring fuse has no meaning as a fuse.

FIG. 8 is a schematic diagram showing the concept of hierarchical fuse selection switching when a memory macro is mounted on a system LSI having the fourth layer as the uppermost layer wiring. In this case, the fourth layer wiring fuse 1
There are only two fuses, and the fuse selection circuit (L) and the fuse selection circuit (R) disposed on the left and right sides of the hierarchical fuse portion respectively connect both terminals of the fourth layer wiring fuse, which is the uppermost layer wiring fuse. By selection, the internal circuit node (1) becomes the fuse selection circuit (L), the fourth layer wiring fuse, and the fuse selection circuit (R).
Are sequentially connected to the internal circuit node (2).

As a result, the fourth layer wiring fuse becomes electrically effective. FIG. 9 is a block diagram showing a configuration for selectively switching a hierarchical fuse in the semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 9, Tr4L, Tr4L
4R, Tr5L, Tr5R, Tr6L, Tr6R are Nch MOS transistors, respectively, and Tr4L, Tr5
The sources of L and Tr6L are commonly connected to the internal circuit node (1), and the drains are respectively connected to one end of a fourth-layer wiring fuse, one end of a fifth-layer wiring fuse, and one end of a sixth-layer wiring fuse. I have.

The sources of Tr4R, Tr5R and Tr6R are commonly connected to an internal circuit node (2), and the drains are respectively connected to the other end of the fourth-layer wiring fuse, the other end of the fifth-layer wiring fuse, and the sixth. It is connected to the other end of the layer wiring fuse.

Further, the gates of Tr4L and Tr4R are
The gates of Tr5L and Tr5R are commonly connected to the logic signal O2 from the logic signal generation circuit 3, and the gates of Tr6L and Tr6L are commonly connected to the logic signal O2 from the logic signal generation circuit 3.
The gate of 6R is provided with the logic signal O from the logic signal generation circuit 3.
3 are connected in common.

The logic signal generation circuit 3 is composed of a NAND element and an inverter element and includes four control signals A, / A,
B and / B are input, and three logic signals O1, O2 and O3 are output based on the control signals.

FIG. 10 shows the logic signal generating circuit 3 shown in FIG.
7 is an operation function table of (the logic signal generation circuit 3 has a common configuration in the first and second embodiments). FIG. 10 shows that only one of the three logic signals O1, O2, and O3 output from the logic signal generation circuit 3 becomes "H". Note that the fuse selection circuit and the logic signal generation circuit shown in FIG. 9 are merely examples of the configuration. For example, a PchMOS transistor may be used in the configuration of the fuse selection circuit. In that case, the logic signal generation circuit 3 and the operation function table of FIG. 10 are of course different from the above.

FIG. 11 is a circuit block diagram showing a configuration of a control signal generation circuit 1 (the control signal generation circuit 1 has a common configuration in the first and second embodiments) in the semiconductor integrated circuit device of the present invention. In FIG. 11, SW_
A and SW_B are switches that are determined to be ON or OFF in a mask application step of the manufacturing process. The switch SW_A includes a sixth wiring layer-fifth wiring interlayer contact (hereinafter, referred to as V5) and a A switch which is turned ON by applying a mask of six wiring layers (hereinafter, referred to as M6). SW_B is a fifth wiring layer-fourth wiring interlayer contact (hereinafter, referred to as V4) and a fourth wiring layer. This switch is turned ON when a mask of five wiring layers (hereinafter, referred to as M5) is applied.

That is, when the mask application is M4 or later, V4,
In a manufacturing process that proceeds in the order of M5, V5, and M6, in a product in which the M4 process is the final process of the wiring layer, SW
_A and SW_B are both in the OFF state, and SW_A is OFF in a product in which the M5 process is the final process of the wiring layer.
State, SW_B is ON state, and SW_A and SW_B are both ON in the product in which the M6 process is the final process of the wiring layer.
It is configured to be in a state.

The power-on reset signal POR is input to the control signal generation circuit 1, and the control signals A, / A, B, / The logic of B is determined.

FIG. 12 is an operation function table of the control signal generation circuit 1 shown in FIG. SW_A, SW_B ON / O
It shows that the logic of the control signals A, / A, B, / B changes depending on the FF state.

FIGS. 13 to 15 show SW_A and SW_A.
A state in which the state of _B switches in the mask application step of the manufacturing process is shown by the cross-sectional structure of each switch. FIG. 13 shows a state in which up to M4 is formed, and both SW_A and SW_B are OFF. FIG. 14 shows a state where M5 is formed, and SW
_A is OFF and SW_B is ON. FIG.
Indicates a state in which up to M6 is formed, and SW_A and SW_B are both ON.

In each of the embodiments described above, the fuse forming layer in the memory macro has been described. However, the present invention is not limited to the fuse forming layer in the memory macro, but may be applied to a semiconductor integrated circuit to which a multilayer wiring process is applied. It is applicable to all of the circuit devices.

[0056]

As described above, according to the first aspect of the present invention, the fuse forming layer always exists at the uppermost layer of all the wiring layers, regardless of the number of all wiring layers of the LSI product. it can.

According to the second aspect of the present invention, a plurality of fuses can be arranged without increasing the area of a fuse forming portion formed by a single wiring layer as in the related art. According to the third aspect of the present invention, it is possible to eliminate damage to the lower fuse that occurs when the fuse formed in the uppermost wiring layer is cut by a laser trimmer or the like.

According to the fourth aspect of the present invention, damage to the lower fuse caused when the fuse formed in the uppermost wiring layer is cut by a laser trimmer or the like is eliminated, and one hierarchical fuse is formed. All of the plurality of fuses are shifted in the horizontal direction, thereby facilitating a layout for connecting each fuse terminal to an internal circuit node.

According to the fifth aspect of the present invention, it is possible to select a fuse which is effective in terms of a circuit from a plurality of fuses each including a different wiring layer, based on the fuse cutting information, and to select a non-selected state. Even if the fuse is damaged, it can be made to have no effect on the circuit.

According to the present invention, a specific terminal is selected from a terminal group of a plurality of fuses each having a different wiring layer, and the selected terminal is electrically connected to the first internal circuit node. Can be connected to

According to the seventh aspect of the present invention, a specific terminal is selected from another terminal group of a plurality of fuses each including a different wiring layer, and the selected terminal is electrically connected to the second internal circuit node. Can be connected to

According to the present invention, the fuse selection circuit can be controlled by the logic signal from the logic signal generation circuit. According to the ninth aspect, the logic signal generation circuit can be controlled by the control signal from the control signal generation circuit.

According to the tenth aspect, the logic of the control signal generated from the control signal generation circuit can be determined by the mask application step of the manufacturing process. According to the eleventh aspect, the control signal from the control signal generation circuit whose logic is determined by the mask application step of the manufacturing process can be automatically generated by turning on the power to the LSI product.

As described above, in the case of a system LSI product in which a memory macro having exactly the same electrical specifications is mounted, the fuse forming layer appropriately corresponds to all the number of wiring layers, regardless of the number of all wiring layers. Thus, it is possible to suppress an increase in types of memory macros, to prevent an increase in man-hours for designing and verifying an LSI product, and to prevent complicated management of types of memory macros.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration for selectively connecting hierarchical fuses in a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 2 is a block diagram showing a schematic configuration for selectively connecting hierarchical fuses in a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 3 is a schematic diagram 1 showing an overlapping configuration of hierarchical fuses in the first and second embodiments.

FIG. 4 is a schematic diagram showing an overlapping configuration of hierarchical fuses in the first and second embodiments.

FIG. 5 is a schematic diagram showing an overlapping configuration of hierarchical fuses in the first and second embodiments.

FIG. 6 is a schematic diagram 1 showing a concept of switching the selection of a hierarchical fuse in the first embodiment.

FIG. 7 is a schematic diagram 2 showing a concept of selecting and switching a hierarchical fuse in the first embodiment.

FIG. 8 is a schematic diagram 3 showing a concept of selecting and switching a hierarchical fuse in the first embodiment.

FIG. 9 is a block diagram showing a configuration for selectively switching a hierarchical fuse according to the first embodiment;

FIG. 10 is an explanatory diagram of an operation function of the logic signal generation circuit in the first and second embodiments.

FIG. 11 is a block diagram showing a configuration of a control signal generation circuit in the first and second embodiments.

FIG. 12 is an explanatory diagram of an operation function of the control signal generation circuit in the first and second embodiments.

FIG. 13 is an explanatory diagram of state switching of a switch unit in a control signal generation circuit according to the first and second embodiments.

FIG. 14 is an explanatory diagram of state switching of a switch unit in the control signal generation circuit according to the first and second embodiments.

FIG. 15 is an explanatory diagram of state switching of a switch unit in the control signal generation circuit according to the first and second embodiments.

FIG. 16 is a sectional structural view of a fuse portion formed by a third wiring layer in a conventional semiconductor integrated circuit device.

FIG. 17 is a sectional structural view of a fuse portion formed by a fourth wiring layer in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 Reference Signs List 1 control signal generating circuit 2 control signal 3 logical signal generating circuit 4 logical signal 5 hierarchical fuse 6L one terminal group of hierarchical fuse 6R other terminal group of hierarchical fuse 7L fuse selection circuit (L) 7R fuse selection circuit (R)

Claims (11)

[Claims] 1. A semiconductor integrated circuit device having a plurality of wiring layers formed by a multi-layer wiring process and having a fuse relieving function in the process, wherein the plurality of wiring layers are formed on different wiring layers. A plurality of hierarchical fuses composed of the above-mentioned fuses. 2. The semiconductor integrated circuit device according to claim 1, wherein a plurality of hierarchical fuses are arranged so as to overlap each other without any displacement between different wiring layers. 3. The semiconductor integrated circuit device according to claim 1, wherein a plurality of hierarchical fuses are arranged so as to be shifted from each other between different wiring layers so as to be displaced. 4. The semiconductor integrated circuit device according to claim 1, wherein the plurality of hierarchical fuses are arranged so as to be displaced from each other in a stepwise manner between different wiring layers. 5. The method according to claim 1, wherein each of the plurality of hierarchical fuses includes a first fuse.
And a plurality of fuses formed in different wiring layers are selectively connected to the first internal circuit node and the second internal circuit node. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is configured. 6. A first fuse selection circuit for selectively connecting one end of a plurality of fuses formed in different wiring layers to a first internal circuit node. Item 6. A semiconductor integrated circuit device according to item 5. 7. A semiconductor device comprising a second fuse selection circuit for selectively connecting the other end of the plurality of fuses formed in different wiring layers to a second internal circuit node. A semiconductor integrated circuit device according to claim 6. 8. The semiconductor integrated circuit according to claim 6, further comprising a logic signal generation circuit for generating a logic signal for controlling selection connection of the first or second fuse selection circuit. Circuit device. 9. The semiconductor integrated circuit device according to claim 8, further comprising a control signal generation circuit for generating a control signal for controlling generation of a logic signal from the logic signal generation circuit. 10. A control signal from a control signal generation circuit,
10. The semiconductor integrated circuit device according to claim 9, wherein the switching is performed by a mask application step in a manufacturing process. 11. A control signal generation circuit, wherein a power-on reset signal generated when the power of the device is turned on is input, and a control signal is generated based on the power-on reset signal. The semiconductor integrated circuit device according to claim 10.