JP2000082093A - Semiconductor device and its layout design method and recording medium recording layout design program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To develop a semiconductor device in a short period by changing the physical configuration of a distribution plane layout that is selected from the distribution plane layout of a 1st layout corresponding to a 1st net list and generating a 2nd layout corresponding to a 2nd net list. SOLUTION: A 1st net list N1 is prepared in a process S100 and a 1st layout is generated based on the list N1 in a process S200. A 2nd net list N2 is prepared in a process S300 and (n-1) pieces or less of distribution plane layouts are selected from 1st to n-th distribution plane layouts in a process S400. Then the physical configurations (patterns) of selected (n-1) pieces or less of distribution plane layouts are changed in process S500. A 2nd layout is generated from those changed distribution plane layouts and the remaining plane layouts of the 1st layout based on the list N2 in a process S600.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design method for designing a semiconductor device, and more particularly to a layout design method capable of easily changing the layout of a connection structure in accordance with a change in specifications, and executing such a layout design method. And a semiconductor device having a structure in which a connection structure can be easily changed.

[0002]

2. Description of the Related Art In recent years, with the advancement of high functionality, high performance and miniaturization of electronic devices, semiconductor devices for specific users (Application Specific Integments) which can be developed in a relatively short time.
The need for ratedCircuit (ASIC) is increasing.
Therefore, in order to further shorten the development period of the ASIC, a gate array system and an embedded gate array system partially incorporating the gate array system have been proposed.

In the gate array system, gates arranged in an array prepared in advance as a master slice are
By wiring according to the specifications of each user, a logic circuit for each user is formed. Since the specifications of each user can be met only by designing the wiring, it is possible to reduce the development cost and the development period.

[0004] The embedded gate array system partially employs the gate array system. Based on whether or not the specification has been determined, a functional circuit (also simply referred to as an “element” or “cell”) is determined by a determined circuit unit (determined element or determined cell) and an undetermined circuit unit (undetermined element or undetermined) Cell). The standard cell method is used for the definite circuit part, and the gate array method is used for the undetermined circuit part. After the specification of the undetermined circuit section is determined, the gates in an array formed in the undetermined circuit section are wired according to the determined specification. According to this method, for example, a fixed circuit unit such as a memory unit is completed up to a layout design in advance. Therefore, a development period required for the layout design is only a design period for an undetermined circuit unit. Becomes possible. Further, since standard cells can be used for the definitive circuit portion, the degree of integration (chip area can be reduced) as compared with the gate array system. An embedded gate array type LSI is disclosed in, for example, US Pat. No. 4,786,631.

Here, definitions of terms used in the present specification will be described with reference to FIG. What defines the geometric structure of the LSI is called a layout 900. LS
The I layout 900 includes an element layout (cell layout) 920 that defines a functional circuit (or cell);
And a wiring layout 940 that defines “wiring”.
The element layout 920 includes a plurality of element plane layouts 9.
22, 923, 924, 925 and 926. Element plane layouts 922, 923, 924, 92
Reference numerals 5 and 926 respectively define an N-well, an active region, a polysilicon layer, a P + ion implantation region, and an N + ion implantation region. A plurality of wiring plane layouts 942 and 94 included in the wiring layout 940
Reference numerals 3, 944, and 945 define patterns of a contact hole, a first wiring, a through hole, and a second wiring, respectively. The "interconnection" means not only an in-plane interconnection (interconection line), but also an interlayer connection (interlay) through a through hole (via hole).
er connection). In order to manufacture a semiconductor device using a normal photolithography process, a mask corresponding to each planar layout is manufactured.

In the above-described gate array type and embedded gate array type LSIs, as the number of gates increases and the number of wiring layers increases, the time required for layout design increases, and the cost and cost for manufacturing masks increase. There is a problem that time increases. In particular, a mask for forming a fine pattern (for example, a design rule of 0.25 μm or less) is significantly more expensive than a conventional mask (for example, a design rule of 0.35 μm or more), and the number of layers is increasing. Therefore, the number of masks required to manufacture one semiconductor device has been greatly increased (for example, six-layer wiring or more). As a result, an increase in cost and time required for manufacturing a mask is becoming a major factor in causing an increase in semiconductor device development cost and a prolonged development period.

A conventional LSI layout design method will be described with reference to FIG.

FIG. 21 shows a flowchart of a conventional layout design method when a circuit change (connection structure change) is required for an LSI once designed.

In step S1700, a layout is designed based on a net list N1 indicating connection information of initial specifications. At this stage, an initial layout corresponding to the initial specification is generated. If there is no need to change the design,
An initial layout is output, and a mask (strictly, a set of masks) is created based on the initial layout.
The set of masks includes masks corresponding one-to-one with each planar layout of the initial layout.

In step S1710, in response to the circuit change, a net list N2 indicating the changed connection information is generated.

In step S1720, netlist N
Layout design is performed again on the basis of 2. here,
A modified layout corresponding to the changed specification is generated. The generation of the modified layout is performed completely independently of the initial layout. For example, in the case of the gate array system, all wirings are re-wired.

In step S1730, netlist N
The modified layout corresponding to No. 2 is output. A mask is manufactured based on the output layout after the correction.

[0013]

SUMMARY OF THE INVENTION The above-mentioned prior art includes:
There are the following problems. An example in which the conventional layout method shown in FIG. 21 is applied to a gate array type LSI will be described.
The problem will be described.

When the layout of the gate array type LSI is changed based on the netlist N2 after the design change, only the wiring layout needs to be re-wired (re-designed), but the re-wiring is executed for all the wirings. Is done. Therefore, the number of processes and the number of masks for the layout design,
That is, the repair period and repair cost cannot be reduced. If a mask is manufactured based on the initial layout, all masks are discarded and a new mask is manufactured from the beginning. Furthermore, if wafers (master slices) have been put into a line for actually manufacturing LSIs, all in-process products must be discarded.

According to the above-described layout method, for example, even for minor changes such as a change in input / output signals and a change in pull-up in a power supply system, all the masks for the wiring layers must be re-produced. Further, as the number of circuits integrated on a single chip increases, the possibility of specification change is also increasing. Therefore, an increase in mask manufacturing cost and a prolonged mask manufacturing time due to design change are becoming serious problems. is there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a layout design method and a layout which enable a semiconductor device to be developed in a shorter time than the conventional one. An object of the present invention is to provide a recording medium on which a design program is recorded and a semiconductor device capable of designing in a short period of time.

[0017]

SUMMARY OF THE INVENTION A layout design method for a semiconductor device according to the present invention comprises the steps of: (a) corresponding to a first netlist, and first to nth (n) elements sequentially stacked on the element layout and the element layout; Preparing a first layout having n wiring plane layouts up to ≧ 2), (b) receiving a second netlist different from the first netlist, and (c) receiving the first layout. Selecting at least n-1 or less wiring plane layouts from the n wiring plane layouts;
(D) changing the physical configuration of the at least one selected wiring plane layout to change the element layout, the unselected wiring plane layout of the first layout, and the changed wiring And generating a second layout corresponding to the second netlist, thereby achieving the above object.

[0018] Before the step (a), the method includes a step of receiving the first netlist and a step of generating the first layout based on the first netlist, wherein the n of the first layout is included. Each of the plurality of wiring plane layouts includes a plurality of redundant wiring patterns that are not included in the first connection structure defined by the first netlist and that are separated from each other, and the step (d) includes the step of: Preferably, the method is a step of generating the second layout including at least one of the plurality of redundant wiring patterns included in the wiring plane layout in a second connection structure defined by the second netlist.

Preferably, the element layout defines at least one standard cell.

Preferably, the element layout defines a plurality of macro blocks.

It is preferable that the step (c) is a step of selecting one wiring plane layout from the n wiring plane layouts of the first layout.

Preferably, the selected wiring plane layout is an n-th plane layout.

The step (c) is a step of selecting a k-th wiring plane layout (1 ≦ k ≦ n) from the n wiring plane layouts of the first layout. In the step (d), When a second layout in which the k wiring plane layout is changed is generated, information indicating k and a second layout are output, and when a second layout in which the k wiring plane layout is changed is not generated Alternatively, the steps (c) and (d) may be repeated until k becomes 1 by replacing k with k-1.

The step (c) is executed for all the combinations, the step (d) is executed for all the combinations obtained in the step (c), and the selection is performed for each of all the combinations. The method may include outputting a second layout set including information for specifying at least one wiring plane layout and a second layout corresponding to the information.

The computer-readable recording medium according to the present invention comprises: (a) an element layout corresponding to a first netlist and a first layer sequentially stacked on the element layout;
Preparing a first layout having n wiring plane layouts from n to n (n ≧ 2); (b) receiving a second netlist different from the first netlist; and (c). Selecting at least n-1 or less wiring plane layouts from the n wiring plane layouts of the first layout; and (d) changing a physical configuration of the selected at least one wiring plane layout. By doing so, it comprises the element layout, the unselected wiring plane layout of the first layout, and the changed wiring plane layout,
Generating a second layout corresponding to the second netlist; and recording a program for causing a computer to execute a layout design method for a semiconductor device, the method comprising:
Thereby, the above object is achieved.

A semiconductor device according to the present invention comprises: an element layer for forming a plurality of elements; and a plurality of wiring layers stacked on the element layer and forming wiring for electrically connecting the plurality of elements to each other. At least one of the plurality of wiring layers
One wiring layer has a redundant wiring provided in a region intersecting with a wiring formed in an upper layer of the at least one wiring layer, and the redundant wiring has at least two conductor portions extending in directions intersecting each other. And the above-mentioned object is achieved.

According to another aspect of the present invention, there is provided an element layer for forming a plurality of elements, and a plurality of wiring layers stacked on the element layer and forming wiring for electrically connecting the plurality of elements to each other. And a plurality of redundant wirings regularly arranged between wirings formed in at least one of the plurality of wiring layers, thereby achieving the above object.

[0028]

FIG. 1 is a flowchart of a layout method according to an embodiment of the present invention.

First, in step S100, a first netlist N1 is prepared. The first netlist may be generated according to the initial specification of the LSI for a specific user, or may be generated according to the versatile basic specification. Next, in step S200, a first layout is generated based on the first netlist N1.
The first layout includes an element layout and a wiring layout. The element layout and the wiring layout have a plurality of element plane layouts and wiring plane layouts, respectively. Here, it is assumed that the wiring layout includes first to n-th (n ≧ 2) wiring plane layouts sequentially stacked on the element layout. That is, the first wiring layout is the lowermost layer (immediately above the element layout), and the n-th wiring plane layout is the uppermost layer. Up to step S200 can be performed by a conventional method. Alternatively, the first layout may be created in advance and stored in a library.

Although the element layout may partially include a gate array type element (functional circuit), it is preferable to use a standard cell. By using the standard cell, it is possible to realize higher density and lower cost as well as higher performance and higher function of the LSI. According to the layout design method of the present invention, it is possible to cope with various specifications (specification changes) compared to the conventional one simply by changing the wiring layout of the multilayer wiring. Need not be used, and an element layout using standard cells can be created. The LSI to which the layout design method of the present invention can be applied may be not only a conventional ASIC but also a system LSI including a plurality of macro cells (also called IP). The system LSI corresponds to the above-mentioned standard cell replaced with a macro cell.

In step S300, a second net list is prepared. The second netlist may correspond to a change in the specification of an LSI for a specific user, or may be a specification determination for a basic specification for responding to a specification from a specific user.

In steps S400 and subsequent steps, a second layout corresponding to the second netlist N2 is generated by changing only the wiring layout.

First, in step S400, n-1 or less wiring plane layouts are selected from the first to n-th wiring plane layouts of the first layout. Subsequently, the physical configuration (pattern) of the selected n-1 or less wiring plane layouts is changed in step S500. Step S600
, A second layout based on the second netlist is generated from the changed wiring plane layout and the remaining plane layouts of the first layout (that is, the element plane layout and the unselected wiring plane layout). The specific method of step S400 to step S600 will be described later. Further, in order to realize various layouts by changing the wiring layout, it is preferable to include a redundant wiring pattern in the wiring layout in advance, as described later in a specific embodiment.

According to the layout method of the present invention, instead of changing the physical configuration of all wiring plane layouts as in the prior art, only the physical configuration of at most n-1 wiring plane layouts is changed. Thus, the layout of the LSI can be designed in accordance with the specification from the user. Therefore, the time and cost required for manufacturing the mask can be reduced. The smaller the number of wiring plane layouts for changing the layout, the greater the effect of reducing the time and cost spent on mask manufacturing.

The position of the wiring plane layout to be changed is preferably in the upper layer. For the upper layer mask, LS
Processing can proceed without waiting for the manufacture of the correction mask up to the step requiring the mask in the manufacturing process of I, so that the manufacturing time can be shortened. In addition, there may be a situation where work in progress flowing on the production line is not wasted. These effects can also be obtained when, for example, a process of drawing with an electron beam is used without using a mask.

The steps S400 to S600 in FIG. 1 can be performed, for example, according to the flowchart shown in FIG.

In step S410, one wiring plane layout (k-th wiring plane layout) is selected from the first to n-th wiring plane layouts of the first layout. First,
Assuming that k = n, the wiring plane layout of the uppermost layer is selected. In step S510, the physical configuration (pattern) of the selected k-th wiring plane layout is changed, and step S6 is performed.
In 10, the second k-th wiring plane layout and the remaining plane layouts are used for the second netlist based on the second netlist.
Generate a layout. Next, in step S612,
It is determined whether the generation of the second layout has succeeded. If the generation has succeeded, the layout design ends. That is, the second layout is generated by correcting only the n-th wiring plane layout in the uppermost layer of the first layout.

It is determined in step S612 that the second layout could not be generated, and k = k in step S614.
If it is not 1, the generation of the second layout is attempted by selecting / changing the lower wiring plane layout with k = k−1 (steps S410 to S6).
Repeat 10). The layout design ends when the second layout is successfully generated. Steps S510 and S610 can be performed using a known rip-up / reroute method.

Here, the lip-up / reroute method is shown in FIG.
2 (a), FIG. 22 (b) and FIG. 22 (c). FIG. 22A shows a wiring plane layout before modification (part of the first layout), FIG. 22B shows a wiring plane layout after rip-up, and FIG.
(C) shows the wiring plane layout (a part of the second layout) after rerouting (rewiring).

As shown by the broken line in FIG. 22A, the two RT1s are connected to each other before the change.
It is assumed that the connection relationship (logical relationship) is changed by the specification change so that one terminal (upper side in the drawing) of RT1 becomes an RT2 terminal and is connected to another RT2 terminal. In this case, as shown in FIG. 22B, the wiring indicated by the broken line is ripped up (peeled off). Thereafter, as shown by the broken line in FIG.
The T2 terminals are connected to each other by a wiring shown by a broken line. For connection between the two terminals, for example, a maze wiring method can be used. For a description of the rip-up / reroute method and the wiring method, see Jiri Soukup, “C
ircuit Layout ", Proc. of IE
EE, Vol. 69, no. 10, pp. 1281-1
304, 1981. Is incorporated herein by reference.

That is, according to the flow shown in FIG.
A second layout generated by changing only one wiring plane layout in the uppermost layer is obtained. If the second layout cannot be generated by changing one wiring plane layout, this flow ends. In that case, the flow of FIG. 3 described later may be executed, or the second layout may be generated by changing all the wiring plane layouts.

Steps S400 to S600 in FIG. 1 can be performed according to the flowchart shown in FIG.

When the method shown in FIG. 3 is used, all the first layouts obtained by changing any n-1 or less wiring plane layouts out of the n wiring plane layouts can be obtained.

First, in step S420, n-1 or less (n
2) Select an arbitrary wiring plane layout. The number of all combinations for selecting an arbitrary number equal to or less than n-1 from n is the number obtained by adding nCm from m = 1 to m = n-1. First, one combination is selected from all the combinations. Actually, it is preferable to select m in a small value (the number of masks is small) and the number of the selected planar layout is large (upper layer as much as possible). The flow of selecting the first wiring plane layout in order from the n-th wiring plane layout with m = 1 can be realized as the flow similar to FIG. A flow for selecting a plurality of wiring plane layouts can be easily realized.

Steps S520 and S620 can be performed using, for example, a lip-up / reroute method, similarly to steps S510 and S610 in FIG. In step S622, it is determined whether the generation of the second layout has been successful. If it is determined in step S622 that the generation of the second layout has failed, and if it is determined in step S624 that the second combination is not the last combination, steps S420 to S620 are repeatedly performed for other combinations. You.

If it is determined in step S622 that the generation of the second layout has been successful, the process proceeds to step S630 in which the number of the changed wiring plane layout and the changed plane wiring layout are set as one set. Generate When the layout design method of the present invention is executed using a computer, this information is stored at least temporarily in the storage device. Then, step S632
In step S420, if it is determined that the combination is not the last combination, steps S420 to S6 are performed for other combinations.
20 are repeatedly executed.

When the steps S420 to S630 are executed for all combinations of the n-1 or less wiring plane layouts, the second layout is obtained by changing the n-1 or less wiring plane layouts. , A set of {changed wiring plane layout number, changed wiring plane layout} is generated for all combinations. That is, a set of all solutions that can generate the second layout is obtained under the condition that the number of masks less than n is changed.

Next, for example, the most preferable solution is selected from all the solutions according to the conditions such as the number and the number of the planar layouts that are allowed to be changed, which are prepared in step S640.
The layout design flow ends. For example, an optimal mask (wiring plane layout) for conditions such as a minimum number of masks and a mask positioned as high as possible.
Select For example, when a mask (a set of masks) based on the first layout is actually manufactured, the number of masks is more important than the position of the mask (upper layer or lower layer) in order to reduce the cost of the correction mask. It is. on the other hand,
When the LSI is actually manufactured in the manufacturing line, it is preferable to provide the position of the mask so that only the mask used in the manufacturing process that has not started yet is changed.

As described above, when the present invention is used, it is necessary to change all the wiring plane layouts in the past, but it is possible to cope with the layout change only by changing at least one wiring plane layout. I can do it. Therefore, the cost and time required for manufacturing the mask can be reduced.

In steps S612 and S622 in the flowcharts shown in FIGS. 2 and 3, only the success or failure of the generation of the second layout is determined. However, the present invention is not limited to this. Then, the determination of success or failure may be made. (Embodiment 1) A mask designing method according to Embodiment 1 of the present invention will be described with reference to FIGS. In the first embodiment, an example will be described in which the layout design method of the present invention is used for correcting a mask.

In this embodiment, a higher-level wiring layer (also referred to as a metal layer) is corrected based on an initial layout designed based on the initial netlist N1 and the changed netlist N2 after the circuit is changed. The purpose is to change the initial layout to the modified layout based on the modified netlist N2.

FIG. 4 is a flowchart of the mask designing method according to the present embodiment. First, in step S1100, a layout design is performed based on the initial netlist N1 to form an initial layout.

Next, in step S1200, a changed netlist N2 describing a circuit change based on the specification change that has occurred is described.
Enter By the above steps S1100 and S1200, an initial layout based on the initial netlist N1 and
The changed netlist N2, which is the connection information that is the basis of the layout change, can be obtained.

Next, in step S1300, a correction mask to be corrected is estimated. In step S1300,
After sequentially estimating the wiring layers necessary for correcting the initial layout based on the initial netlist N1 to the layout based on the changed netlist N2 from the uppermost wiring layer of the initial layout, the wiring layers are corrected. The mask to be modified, ie, the modified mask. Then, correction mask information R for the correction mask is created.

Next, in step S1400, a process (rip-up) of peeling off the wiring layer to be corrected is performed based on the generated correction mask information R.

Next, after rewiring is performed in step S1500 according to the changed netlist N2, in step S1600,
The corrected layout result generated in steps S1100 to 1500 is output.

The feature of the mask designing method according to the present embodiment is that the correction mask corresponding to the wiring layer to be corrected among all the wiring layers is determined by estimating the correction mask in order from the upper wiring layer, and the created correction mask is determined. That is, rewiring is performed based on the information R, and a layout result after the correction is output. As a result, the design change and mask production need only be performed for a minimum number of masks.

As described above, according to the present embodiment, when there is a circuit change, it is not necessary to change the design and manufacture the mask for all the wirings, and the upper level is determined based on the corrected mask information R created by the estimation. For only a minimum number of masks from the wiring layer, design change and mask manufacture are performed. Therefore, the cost required for mask design change and manufacture, that is, the repair cost, can be reduced, and the period required for mask change can be shortened, so that the LSI development period can be shortened.

The correction is performed from the uppermost wiring layer formed in a process close to the final stage of the manufacturing process. This makes it possible to cope with circuit changes even if the manufacture of the LSI has progressed to some extent. Therefore, the turnaround time required for correcting the LSI can be reduced.

Further, the mask designing method of the present embodiment can be applied to a method other than the method of designing an LSI by combining basic circuits composed of transistors. Therefore, the circuit area can be optimized and the area of the LSI can be reduced, so that the cost of the LSI can be reduced.

The design change and layout transition according to the flow of FIG. 4 will be specifically described with reference to FIGS. 4 and 5. FIGS. 5A to 5C are pattern diagrams showing layouts before modification, during modification, and after modification, respectively, for a layout to be changed. Here, the transition of the layout will be described for the case where the number of metal layers among the wiring layers is three, that is, the case where the layout design is performed as the metal layers M3, M2, and M1 in order from the uppermost layer. In this case, the wiring layer includes five metal layers, that is, three metal layers and two interlayer connection layers for connecting the metal layers. In FIG. 5, wirings M2a and M2
are wirings belonging to the metal layer M2, and wirings M3a, M3c,... are wirings belonging to the metal layer M3. The via holes V3a, V3b,... Are via holes belonging to an interlayer connection layer V3 for connecting wirings respectively belonging to the metal layers M3 and M2.

First, in step S1100 of FIG. 4, an initial layout is designed based on the initial netlist N1. Here, for example, the initial netlist N1 is net1 connect (A, B) and net2 connect (C, D) for the terminals A to D. The initial netlist N1 indicates that the terminal A is connected to the terminal B and the terminal C is connected to the terminal D. Initial wiring is performed based on the initial netlist N1 to obtain an initial layout 10 shown in FIG. That is, as shown in FIG.
B, the wiring M2a, the via hole V3a, and the wiring M3
a, via hole V3b, and wiring M2b. Similarly, a wiring M2c, a via hole V3c, a wiring M3c, a via hole V3d, and a wiring M2 are provided between the terminals C and D.
Connect via d.

Next, in step S1200, a changed netlist N2 is obtained. Here, for example, the changed netlist N
Reference numeral 2 denotes net1 connect (A, C) and net2 connect (B, D) for terminals A to D. The netlist N2 after this change is the terminal A
And terminal C are connected, and terminal B and terminal D are connected.

Next, in step S1300, a mask to be corrected is estimated based on the changed netlist N2 to generate corrected mask information R. Here, it is assumed that the metal layer M3 has been obtained as the correction mask information R.

Next, in step S1400, the correction mask is rip-up based on the correction mask information R. That is,
The metal layer M3 is rip-up based on the modified mask information R to generate wiring layer data including data of the remaining wiring layers. In this step, since it is not included in the correction mask information R, the interlayer connection layer V3 is not peeled off.
As a result, as shown in FIG. 5B, from the initial layout 10, the wiring M3 belonging to the metal layer M3
a and M3c are removed to obtain a layout 11.

Next, in step S1500, based on the wiring layer data, rewiring is performed in accordance with the changed netlist N2 to obtain the modified layout 20 shown in FIG. 5C.
That is, between the terminals A and C, the wiring M2a, the via hole V3a, the wiring M3a ', the via hole V3c, the wiring M2
Connect via c. Similarly, a wire M is connected between the terminals B and D.
2b, via hole V3b, wiring M3b ', via hole V3d, and wiring M2d.

Here, according to the conventional design method including the gate array system and the embedded gate array system, when the above-described circuit change is made, three metal layers M1 to M3 and two metal layers M1 to M3 are used. It was necessary to design and manufacture a total of five masks respectively corresponding to the interlayer connection layers. In contrast, according to the present embodiment, the metal layer M3
Only one mask corresponding to the above may be manufactured by changing the design. As a result, it can be seen that the period required for changing the mask and the repair cost have been greatly reduced.

Hereinafter, the step of estimating the correction mask and generating the correction mask information R, that is, step S1300 in FIG. 4, will be described with reference to FIGS. FIG.
5 is a flowchart of step S1300 in FIG.

First, in step S1310, the metal layer M3, which is the uppermost layer of the wiring layers, is set as the correction mask information R, and R = {M3}.

Next, in step S1320, step S1 in FIG.
Initial layout 1 shown in FIG.
From 0, the wiring belonging to the metal layer M3 specified by the correction mask information R is virtually peeled off by rip-up processing to generate wiring layer data including data of the remaining metal layers M2, M1 and the interlayer connection layer V3. I do. As a result, the layout 11 shown in FIG. 5B is obtained.

Next, in step S1330, step S1 in FIG.
Similarly to 500, rewiring is performed virtually according to the changed netlist N2 based on the wiring layer data. as a result,
If the wiring connection is successful, the modified layout 20 shown in FIG. 5C is obtained.

Next, in step S1340, it is determined whether or not the wiring connection has succeeded by virtual rewiring. Here, if the wiring connection is successful, that is, if the wiring correction processing is completed by rewiring, the process proceeds to step S135.
The process proceeds to 0, and the correction mask information R = {M3} set in step S1310 is output as it is. Then, the step of estimating the correction mask and creating the correction mask information R, that is, the step S1300 in FIG. 4, is ended. On the other hand, if the wiring cannot be corrected by the virtual rewiring, the process proceeds to step S1360.

Next, in step S1360, it is determined whether or not the corrected mask information R indicates all wiring layers. Here, if the correction mask information R indicates all wiring layers, it means that a circuit change could not be performed even if correction was made for all wiring layers, and thus correction including transistor arrangement is necessary. Therefore, the process proceeds to step S1370, and in step S1370, the correction mask information R is set as R = {φ}, and then in step S1350, the correction mask information R (=
{Φ}), and the step S1300 in FIG. 4 ends. On the other hand, if the correction mask information R does not indicate all the wiring layers, the process proceeds to step S1380.

Next, in step S1380, the uppermost wiring layer among the wiring layers belonging to the lower wiring layer which is not included in the correction mask information R is added to the correction mask information R.
The process returns to 1320. Then, the process is repeated from step S1320, that is, from the step of virtually riping up the added wiring layer.

The processing according to the flow of FIG. 6 and the transition of the layout will be specifically described with reference to FIG.
FIGS. 7A to 7C are pattern diagrams showing layouts before modification, during modification, and after modification, respectively, for a layout to be changed. FIG. 7A shows FIG.
The same initial layout as in (a) is shown.

In step S1320 in FIG. 6, the metal layer M3 is virtually ripped up from the initial layout 10 shown in FIG. 7A, and the same layout 11 shown in FIG. obtain.

Here, consider the case where rewiring could not be performed in step S1330. In this case, step S1340
In step S136, it is determined that rewiring could not be performed.
Proceed to 0. Then, in step S1360, since the correction mask information R is R = {M3} and not all the wiring layers, the process proceeds to step S1380.

In step S1380, since the uppermost layer in the wiring layer lower than metal layer M3 indicated by correction mask information R is interlayer connection layer V3, the process returns to step S1320 after setting R = {M3, V3}. .

In step S1320, the wiring layer added to the correction mask information R, ie, the interlayer connection layer V3 is virtually flipped up to generate wiring layer data, and the layout 12 shown in FIG. obtain.

Further, in step S1330, the wiring M3
a ″ and via hole V3 belonging to interlayer connection layer V3
a ′, V3c ′ and a wiring M3b between the terminals A and C.
And via holes V3b ', V3 belonging to interlayer connection layer V3.
The terminals B and D are virtually connected using d ′. As a result, the modified layout 20 'shown in FIG. 7C is obtained.

As described above, according to the step of estimating the correction mask of the design method according to the present embodiment, the virtual rip-up (step S1320 in FIG. 6) and the rewiring (step S1330 in FIG. 6) are performed, respectively. Thus, the correction mask information R required for the layout design according to the post-change netlist N2 can be reliably created.

In this embodiment, the correction mask information R
Is determined based on whether or not rewiring based on the changed netlist N2 is possible or not, as in step S1340 in FIG. 6, but is not limited to this. The correction mask information R may be created. In this case, since each via hole can be selected from the interlayer connection layer V3 in consideration of the wiring characteristics, a corrected layout having excellent wiring characteristics can be reliably obtained. For example,
In the case shown in FIG. 7, the wiring length is evaluated as the wiring characteristic and the corrected mask information R is created, whereby
As shown in (c), an excellent modified layout having a short wiring length, that is, a small wiring resistance can be reliably realized.

(Embodiment 2) FIGS. 8 to 10 show a mask design method and a semiconductor device according to Embodiment 2 of the present invention.
This will be described with reference to FIG. In the present embodiment, regardless of the presence or absence of a circuit change, the layout of the semiconductor device is previously set to a layout that can be easily corrected, thereby facilitating the design change and preventing the deterioration of the wiring characteristics after the change. The purpose is.

FIG. 8 is a flowchart of the mask designing method according to the present embodiment. The mask design method shown in FIG. 8 is different from the mask design method shown in FIG.
Step S115 after designing an initial layout in 1100
By adding 0, layout conversion is performed to facilitate design change, that is, to facilitate correction.

Hereinafter, the process of facilitating the correction in step S1150 of FIG. 8 will be described with reference to FIG.
FIGS. 9A to 9D show layouts before and after the simplification process, after the simplification process and after the design, and after the simplification process and after the circuit change for the layouts to be changed. FIG. FIG. 9A shows the same layout 12 as FIG. 7B in the first embodiment. This layout 12 corresponds to FIG.
From the initial layout 10 shown in FIG.
The layout is made up of only the metal layer M2 except for the metal layer M3 and the interlayer connection layer V3.

In step S1150 of FIG. 8, the wiring M2a, which was a single wiring in the layout 12 shown in FIG. 9A, is divided into a wiring M2a1 and a wiring M2a2 as shown in FIG. 9B. I do. Similarly, the wiring M2c is connected to the wiring M
The wiring M2d is connected to the wiring M2d1 between the wiring 2c1 and the wiring M2c2.
And the wiring M2d2. The wiring M2b is not divided because it is shorter than a predetermined reference compared to a predetermined reference. As a result, the simplified layout 13 shown in FIG. 9B is obtained.

Here, as in the first embodiment, when the layout is designed based on the initial netlist N1, the layout 10 'shown in FIG. 9C is obtained. That is,
Wirings M2a2, M3a1, M2a1, M3a2, M2b
And the vias belonging to the interlayer connection layer V3 are used to connect the terminals A and B to each other to form wirings M2c2, M3c1, and M2c.
1, M3c2, M2d2, M3c3, M2d1 and each of the via holes belonging to the interlayer connection layer V3, the terminals C and D
Connect between. As a result, a layout 10 'that satisfies the connection of the initial netlist N1 can be obtained in the same manner as the initial layout 10 shown in FIG.

Further, when the circuit is changed in the same manner as in the first embodiment, the layout is designed based on, for example, the changed netlist N2 to obtain the corrected layout 20 '' shown in FIG. 9D. . In this case, wiring M2a2, M
3a ', M2c2 and each via hole belonging to the interlayer connection layer V3, the terminals A and C are connected to each other, and the wiring M2b, M
Terminals B and D are connected using 2b ', M2d1 and each via hole belonging to interlayer connection layer V3. The modified layout 20 ″ shown in FIG. 9D and the modified layouts 20 and 20 ′ according to the first embodiment (FIGS. 5C and 7C).
As can be seen from the comparison with the modified layout 2,
In the case of 0 ″, the connection between the terminals A and C and between the terminals B and D are realized by short wiring.

Here, a feature of the mask designing method according to the present embodiment is that a single wire can be divided in advance. Thereby, when the layout is modified by changing the circuit, the layout can be easily modified, and the wiring length can be reduced, that is, the wiring length can be optimized, that is, the wiring can be corrected with a shorter wiring. Therefore, the signal delay due to the wiring can be improved by improving the wiring characteristics.

FIGS. 10A to 10D and FIGS.
(B) is a pattern diagram showing, in a modification of the design method according to the present embodiment, an initial layout in the metal layer M2, results of various facilitation processes for the initial layout, and results after the design change, respectively. is there. FIG.
(A) shows an initial layout 30 using only the metal layer M2.
Is shown. Then, in the simplification process of this modification, as shown in FIG. 10B, a wiring not used in the initial layout 30, that is, a redundant wiring M2h, is added to an empty area between the wirings M2s. The layout 31 is obtained.

According to the present modification, by using the simplified layout 31 to which the redundant wiring M2h is added, it is possible to use the metal layer M2 in the wiring correction after the metal layer M3 and the interlayer connection layer V3 are peeled off. The number of wiring patterns can be increased. Therefore, by increasing the wiring pattern in the metal layer M2 using the redundant wiring M2h, the wiring length can be optimized and the rewiring can be facilitated.

For this modification, another design method can be further combined. For example, FIG.
10 shows a design method in which wiring is divided in advance into the layout shown in FIG. 10B, that is, a simplified layout 32 obtained by applying the method described earlier in the present embodiment. According to this method, by dividing the wiring M2s and the redundant wiring M2h in advance, the metal layer M3 and the interlayer connection layer V
3 in the wiring correction after peeling off the metal layer M2
Can further increase the usable wiring patterns. Therefore, as shown in FIG. 10D, the wiring M2s, the via hole V3e belonging to the interlayer connection layer V3, and the metal layer M3
And a short wiring M3e belonging to As a result, the wiring length can be optimized, the rewiring can be further facilitated, and a layout 30 ′ electrically equivalent to the initial layout 30 can be obtained.

Further, as shown in FIG.
A plurality of redundant via holes V3f are added to the layout 30 'shown in (d) to form an easy layout 33, and rewiring can be performed using the easy layout 33. As a result, a layout 30 ″ as shown in FIG. 11B is obtained. In this case, by using the wiring M2s, the via hole V3e, and the wiring M3e, FIG.
A layout electrically equivalent to the initial layout 30 shown in (a) can be obtained, and a wiring can be added using the redundant wiring M2h, the redundant via hole V3f, and the wiring M3f. That is, the redundant via hole V
Since the wiring belonging to the higher-order metal layer M3 is more effectively used by using 3f, the metal layers M2 and M3 can be more effectively used to easily re-wire, and the wiring length can be optimized. In this case, in order to use other metal layers more effectively, it is preferable to arrange redundant via holes in a staggered manner.

The layouts after the simplification processing used in the present embodiment, ie, the layouts shown in FIGS. 9B, 10B, 10C and 11A are used. The facilitating layouts 13, 31, 32, and 33 may be formed in the semiconductor device in advance. According to this, when a circuit change is made, the wiring length is optimized, the wiring characteristics are improved, and a semiconductor device that can easily cope with the circuit change is realized.

In the above description of each embodiment, three-layer metal wiring is described. However, the present invention is not limited to this, and it is apparent that similar effects can be obtained with two-layer metal wiring or four or more metal wiring. is there.

In each embodiment, when the area to be changed in design is a part of the layout, the division of the metal wiring, the redundant wiring, or the redundant via hole used for the process of facilitating the correction is performed in the layout. It is needless to say that the effectiveness of the present invention does not change even when it is used for parts.

Further, the present invention can be applied to a system LSI. Many system LSIs are manufactured for specific users similarly to ASICs. Therefore, ASI
The problem of the prior art described for C also exists in the current system LSI. Therefore, by applying the present invention to a system LSI, the development time and cost of the system LSI can be reduced.

FIG. 12 schematically shows a top view of the system LSI 50. The system LSI 50 has a plurality of macro blocks (sometimes called IPs or cores) 52 and inter-macro wiring 54. The macro block 52 includes, for example, a CPU, a DSP circuit, a RAM, a ROM,
Examples include a timing circuit and an I / O circuit. Many of the macro block layouts can be saved in a cell library. Therefore, the layout design of the system LSI for a specific user only needs to select the necessary macroblocks from the macro library, and then perform only the layout design of the wiring between the macroblocks.
The layout design method of the present invention can be used for the wiring between macroblocks.

That is, when the inter-macroblock wiring is formed by multi-layer wiring, a layout design of a desired system LSI can be performed only by changing a wiring plane layout located as little as possible and / or as high as possible. As described in the second embodiment, it is preferable to divide a long wiring or provide a redundant wiring (including a redundant via hole) in order to increase the degree of design freedom. Further, it is preferable that the input / output terminals of the redundant transistor be connected in the uppermost wiring layer, and that a switch box for the upper wiring in the channel region is provided.

Hereinafter, an example of a wiring layout including a redundant wiring suitably used for the semiconductor device (including an ASIC and a system LSI) of the present invention will be described with reference to FIGS. explain.

FIGS. 13A and 13B show two wiring plane layouts (via holes interposed) of a conventional semiconductor device layout, and FIGS. 14A and 14B show the present invention. 2 shows two wiring plane layouts of a semiconductor device layout according to the first embodiment. FIGS. 13 (a) and 14
13A shows a state in which two wiring plane layouts are overlapped, and FIGS. 13B and 14B show wiring plane layouts in lower layers.

As shown in FIG. 13A, in the conventional semiconductor device, the upper layer wiring WU and the lower layer wiring WL are connected to each other at a point where they cross each other via a via hole V. Further, as shown in FIG. 13B, no wiring is provided in a region where the lower wiring WL is unnecessary. On the other hand, as shown in FIGS. 14A and 14B, in the semiconductor device of the present invention, the redundant wiring WR
And a redundant via hole VR. As shown in FIG. 14B, the redundant wiring WR1 is formed in a region where no wiring is formed in the conventional lower-layer wiring plane layout (FIG. 13B). Redundant wiring WR2
Are formed in regions where the lower layer wiring WL and the upper layer wiring WU intersect. The redundant wiring WR2 is a single continuous wiring in the conventional layout (FIG. 13).
(B) The wiring WL is divided into two in a region intersecting with the wiring WU in the upper layer, and is formed between the two divided wirings. Further, the redundant wirings WR1 and WR2 have a cross shape. One direction of the cross is parallel to WU and the other is parallel to WL. That is, the redundant wirings WR1 and WR2 have two conductor portions extending in directions intersecting each other (different directions, typically orthogonal directions). These redundant wirings WR1, WR2 and redundant via holes VR
May be generated, for example, in step S1150 shown in FIG.

Next, with reference to FIGS. 15 and 16, it will be described that the use of the above-mentioned cross-shaped redundant wiring makes it easy to change the wiring layout.

FIGS. 15A and 15B show a conventional layout in which two wirings WL and WU intersect with each other. FIG. 15A shows an overlapping state, FIG. 15B shows a lower layer layout, and FIG. 15C shows an upper layer layout. FIGS. 16A and 16B show a layout having a redundant wiring according to the present invention, wherein FIG.
(B) shows the layout of the lower layer, and (c) shows the layout of the upper layer.

As can be seen from a comparison between FIG. 15B and FIG. 16B, in the lower layer layout according to the present invention, the lower layer wiring WL is divided into two at the intersections, and the area between the divided WLs is divided. Has a cross-shaped redundant wiring WR1. On the other hand, FIG.
As shown in FIG. 6C, the upper layer layout according to the present invention has the redundant wiring WR2 provided in a direction orthogonal to the upper wiring WU (to overlap the lower wiring WL). These wirings are formed by using via holes VR as shown in FIG.
As shown in (2), two wires crossing each other are formed by connecting each other.

Using the same pattern as that of FIG. 16B for the lower wiring WL, the pattern of the redundant via hole VR ′ and the upper wiring WU is changed as shown in FIGS. 17B and 17C. By using this, the wiring having the pattern shown in FIG. 17A can be obtained. That is,
By simply changing the via hole pattern and the upper layer wiring pattern, a wiring different from the connection structure shown in FIG. 16A can be realized.

Further, the pattern of the redundant wiring is not limited to a cross, but may be a shape having two conductor portions extending in directions intersecting each other (different directions, typically orthogonal directions). For example, an S-shape as shown in FIG. 18A or an H-shape as shown in FIG. 18B may be used. Also, as shown in FIGS. 18A and 18B, if these redundant wirings WR are arranged so as to have a conductive portion overlapping with the upper layer wiring WU, the wiring layout can be easily changed. Can be.

Further, it is preferable to arrange the above-mentioned redundant wiring in the empty area in the conventional wiring layout unless there is a special reason. For example, as shown in FIGS. 19A and 19B, a plurality of cross-shaped redundant wirings W
What is necessary is just to arrange R regularly. The shape of the redundant wiring WR is
It is not limited to a cross, but may be an S-shape or an H-shape.

[0109]

According to the layout design method of the semiconductor device according to the present invention, when the circuit is changed due to the specification change, the layout can be changed easily, so that the development period of the semiconductor device is shortened. Can be. For example,
For the specification change once the layout design is completed,
Can respond quickly. Further, it is possible to cope with a change in the layout due to a change in the specification by changing the minimum number of wiring plane layouts. Therefore, the time and cost required for manufacturing the mask can be reduced. Furthermore, since the wiring plane layout for changing the layout can be limited to a wiring plane layout of an upper layer as much as possible (corresponding to a mask used in a later step of the semiconductor process), depending on the progress of the manufacturing process, the work in process may be limited. Manufacturing time and manufacturing cost can be reduced without wasting products.

Further, the semiconductor device having the redundant wiring according to the present invention has a structure that facilitates the above-described layout change and easily optimizes the wiring characteristics (delay characteristics, etc.).

According to the present invention, there are provided a layout design method and a recording medium on which a layout design program is recorded, which makes it possible to develop a semiconductor device in a shorter time than before, and a semiconductor device which can be designed in a short time. You.

[Brief description of the drawings]

FIG. 1 is a flowchart of a layout design method according to an embodiment of the present invention.

FIG. 2 is a flowchart of another layout design method according to an embodiment of the present invention.

FIG. 3 is a flowchart of another layout design method according to the embodiment of the present invention;

FIG. 4 is a flowchart of a mask design method according to the first embodiment of the present invention.

FIGS. 5A to 5C are pattern diagrams respectively showing layouts before, during, and after modification of a layout to be changed in design according to the first embodiment.

FIG. 6 is a flowchart showing details of processing for estimating a correction mask in step S1300 of FIG. 4;

FIGS. 7A to 7C are diagrams showing a layout before modification when estimating a modification mask;
It is a pattern figure which shows the layout during correction and after correction, respectively.

FIG. 8 is a flowchart of a mask design method according to a second embodiment of the present invention.

FIGS. 9A to 9D show layouts to be changed in design according to the second embodiment before the simplification processing, after the simplification processing, after the simplification processing and after the design, and after the simplification processing; FIG. 4 is a pattern diagram showing a layout after a circuit change.

FIG. 10A shows an initial layout using one metal layer in a modification of the design method according to the second embodiment;
(B) shows the result of the simplification processing in this modification, and (c)
FIG. 14 is a pattern diagram showing a result of another facilitation process, and FIG. 14D is a pattern diagram showing a layout after designing using FIG.

11A is a diagram illustrating a result of facilitation processing for one metal layer and one interlayer connection layer in another modified example of the design method according to the second embodiment, and FIG. FIG. 4 is a pattern diagram showing a layout after designing.

FIG. 12 is a diagram schematically showing a top view of a system LSI.

FIG. 13 is a diagram showing two wiring plane layouts (via holes interposed) in a layout of a conventional semiconductor device.

FIG. 14 is a diagram showing two wiring plane layouts of the layout of the semiconductor device according to the present invention;

FIG. 15 shows two wirings WL (lower layer) and WU (upper layer)
Is a diagram showing a conventional layout in which.

FIG. 16 shows two wirings WL (lower layer) and WU (upper layer)
FIG. 3 is a diagram showing a layout having redundant wirings of the present invention, in which the lines cross each other.

FIG. 17 shows two wirings WL (lower layer) and WU (upper layer)
FIG. 14 is a diagram showing another layout having the redundant wiring of the present invention, in which crosses are formed.

FIG. 18 is a diagram showing a redundant wiring pattern according to the present invention.

FIG. 19 is a diagram showing an example of the arrangement of a plurality of redundant wirings according to the present invention.

FIG. 20 is a schematic plan view showing a layout of the semiconductor device.

FIG. 21 is a flowchart of a conventional mask design method when a circuit change occurs.

22A shows a wiring plane layout before modification (part of the first layout), FIG. 22B shows a wiring plane layout after rip-up, and FIG. 22C shows rerouting (rewiring). The subsequent wiring plane layout (part of the second layout) is shown.

[Explanation of symbols]

 10, 30 Initial layout 13, 31, 32, 33 Simplified layout 20, 20 ', 20 "Modified layout A, B, C, D terminals

Claims (11)

[Claims] 1. A layout design method for a semiconductor device, comprising: (a) an element layout corresponding to a first netlist and first to n-th layers sequentially stacked on the element layout;
Preparing a first layout having n wiring plane layouts up to (n ≧ 2); (b) receiving a second netlist different from the first netlist; and (c) receiving the first netlist. Selecting at least n-1 or less wiring plane layouts from the n wiring plane layouts in the layout; and (d) changing a physical configuration of the selected at least one wiring plane layout. Generating a second layout corresponding to the second netlist, comprising: the element layout; the unselected wiring plane layout of the first layout; and the changed wiring plane layout. A layout design method that encompasses 2. The method according to claim 1, further comprising: receiving the first netlist before the step (a); and generating the first layout based on the first netlist. Each of the n wiring plane layouts includes a first netlist defined by a first netlist.
A plurality of redundant wiring patterns that are not included in a connection structure and are separated from each other; and the step (d) includes at least one of the plurality of redundant wiring patterns included in the selected wiring plane layout, 2. The layout method according to claim 1, further comprising: generating the second layout included in a second connection structure defined by the second netlist. 3. 3. The layout design method according to claim 1, wherein the element layout defines at least one standard cell. 4. The layout design method according to claim 1, wherein the element layout defines a plurality of macro blocks. 5. The layout method according to claim 1, wherein the step (c) is a step of selecting one wiring plane layout from the n wiring plane layouts of the first layout. . 6. The selected wiring plane layout includes:
The layout method according to claim 5, wherein the layout method is an n-th plane layout. 7. The step (c) of selecting a k-th wiring plane layout (1 ≦ k ≦ n) from the n wiring plane layouts of the first layout; In the above, when the second layout in which the k wiring plane layout is changed is generated, information indicating k and the second layout are output, and the second layout in which the k wiring plane layout is changed is not generated. 6. The layout method according to claim 5, wherein, if k is replaced with k-1, the steps (c) and (d) are repeated until k becomes 1. 8. The step (c) is performed for all combinations, and for all the combinations obtained in the step (c),
Performing the step (d) and outputting a second layout set including information for specifying the selected at least one wiring plane layout and a corresponding second layout for each of all combinations. Claims 1 to 4
Layout method according to any of the above. 9. A computer-readable recording medium, comprising: (a) an element layout corresponding to a first netlist and first to n-th layers sequentially stacked on the element layout;
Preparing a first layout having n wiring plane layouts up to (n ≧ 2); (b) receiving a second netlist different from the first netlist; and (c) receiving the first netlist. Selecting at least n-1 or less wiring plane layouts from the n wiring plane layouts in the layout; and (d) changing a physical configuration of the selected at least one wiring plane layout. Generating a second layout corresponding to the second netlist, comprising: the element layout; the unselected wiring plane layout of the first layout; and the changed wiring plane layout. A storage medium in which a program for causing a computer to execute a layout design method for a semiconductor device, including: 10. An element layer for forming a plurality of elements, and a plurality of wiring layers stacked on the element layer and forming a wiring for electrically connecting the plurality of elements to each other, At least one of the wiring layers of
A redundant wiring provided in a region intersecting with a wiring formed in an upper layer of the at least one wiring layer, wherein the redundant wiring has at least two conductor portions extending in directions intersecting with each other; Semiconductor device. 11. An element layer for forming a plurality of elements, and a plurality of wiring layers laminated on the element layer and forming a wiring for electrically connecting the plurality of elements to each other, A plurality of redundant wirings regularly arranged between wirings formed in at least one of the wiring layers.