JP2012243791A - Layout design method and layout design program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrict increase in a chip area while also cutting down man-hours required for the placement of dummy wiring patterns.SOLUTION: A layout design method involves extracting bulk cells placed in a layout region (S2) after a layout design apparatus has carried out semiconductor integrated circuit placement and wiring in the layout region (S1) and searching the layout region to check whether a blank wiring region of a prescribed size exists around any extracted bulk cell (S3). If a blank wiring region of the prescribed size is detected by the search, a dummy wiring pattern is placed in the detected blank wiring region on the basis of the coordinates of the extracted bulk cell (S4).

Description

  The present invention relates to a layout design method for a semiconductor integrated circuit and a layout design program.

  When there is a design change in the semiconductor integrated circuit and the wiring pattern arrangement is changed (wiring revision), it is necessary to newly create a mask for generating a wiring layer for changing the wiring pattern arrangement. Since the creation of the mask is costly, if the change in the arrangement of the wiring pattern extends over a large number of wiring layers, the number of newly created masks increases, and the cost increases significantly.

  On the other hand, by arranging dummy wiring patterns in the semiconductor integrated circuit in advance and using this dummy wiring pattern when changing the design, the number of wiring layers for changing the wiring pattern arrangement can be reduced. There is technology to suppress. For example, the dummy wiring pattern is arranged with reference to coordinates such as a dedicated cell or a power supply wiring pattern.

JP 2007-273847 A JP-A-6-216247 JP 2000-252360 A JP 2008-250490 A

  However, in the method of arranging the dummy wiring pattern on the basis of the coordinates of the dedicated cell, an area for arranging the dedicated cell is required, which may increase the chip area. Further, in the method of arranging the dummy wiring pattern with reference to the coordinates of the power supply wiring pattern, since the number of points serving as reference points is enormous, it may take a lot of man-hours to narrow down the reference points. .

According to one aspect of the invention, the following layout design method is provided.
In this layout design method, the layout design apparatus performs placement and wiring of the semiconductor integrated circuit on the layout area, and then extracts the bulk cells arranged in the layout area, and around the extracted bulk cells in the layout area. If a free wiring area having a predetermined size is found and a free wiring area having a predetermined size is detected as a result of the search, the detected free space is determined based on the coordinates of the extracted bulk cell. A dummy wiring pattern is arranged in the wiring area.

  According to the disclosed layout design method and layout design program, it is possible to reduce the man-hour required for arranging the dummy wiring pattern while suppressing an increase in the chip area.

It is a flowchart which shows an example of the layout design procedure which concerns on 1st Embodiment. It is a figure which shows an example of the hardware of the layout design apparatus which concerns on 2nd Embodiment. It is a flowchart which shows an example of the layout design procedure which concerns on 2nd Embodiment. It is a figure which shows an example of the layout area | region where arrangement | positioning wiring was performed. It is a flowchart which shows an example of the arrangement | positioning procedure of the dummy short wiring pattern which concerns on 2nd Embodiment. It is a figure which shows an example of the layout area | region where the dummy short wiring pattern is arrange | positioned. It is a flowchart which shows an example of the connection procedure of the dummy short wiring pattern which concerns on 2nd Embodiment. It is a flowchart which shows an example of the connection procedure of the dummy short wiring pattern which concerns on 2nd Embodiment. It is a flowchart which shows an example of the connection procedure of the dummy short wiring pattern which concerns on 2nd Embodiment. It is a figure which shows an example of the connection process of a dummy short wiring pattern. It is a figure which shows an example of the connection of a dummy short wiring pattern. It is a figure which shows an example of the connection of a dummy short wiring pattern. It is a figure which shows an example of the connection process of a dummy short wiring pattern. It is a figure which shows an example of the search route of a terminal. It is a figure which shows an example of the layout area | region where the dummy wiring pattern is arrange | positioned. It is a flowchart which shows an example of the wiring change procedure which concerns on 2nd Embodiment. It is a figure which shows an example of a wiring change process. It is a figure which shows an example of the layout area | region where wiring change was performed.

Hereinafter, embodiments will be described with reference to the drawings.
[First Embodiment]
The first embodiment relates to a layout design method for a semiconductor integrated circuit.

FIG. 1 is a flowchart showing an example of a layout design procedure according to the first embodiment. The process shown in FIG. 1 is executed by the layout design apparatus.
[Step S1] The layout design apparatus performs placement and routing of the semiconductor integrated circuit in the layout region. Here, the layout area indicates a chip area expressed on the design data. In this step, a plurality of functional cells and bulk cells are arranged, and further, wirings connecting the functional cells are drawn.

  Here, the functional cell is a cell for realizing a predetermined function (for example, an OR gate, an AND gate, etc.), and includes a bulk layer (a semiconductor substrate, and a gate electrode layer formed on the semiconductor substrate, A cell including a layer in which a plurality of transistors are formed) and a wiring layer (for example, a metal wiring layer).

  A bulk cell is a cell that is used when changing the logic of a semiconductor integrated circuit, and includes a bulk layer and does not include a wiring layer. An example of a bulk cell is a gate array, for example.

[Step S2] The layout design apparatus extracts bulk cells arranged in the layout area.
[Step S3] The layout design apparatus searches for a free wiring area having a predetermined size around the extracted bulk cell in the layout area.

  [Step S4] When the layout design apparatus detects an empty wiring area having a predetermined size as a result of the search, a dummy wiring pattern is arranged in the detected empty wiring area with reference to the coordinates of the extracted bulk cell.

In this way, the dummy wiring pattern is arranged in the layout area.
As described above, in the first embodiment, the coordinates of the bulk cell are used as the reference points for arranging the dummy wiring patterns. According to this configuration, for example, it is not necessary to provide a dedicated cell in order to form a dummy wiring pattern, so that an increase in chip area can be suppressed.

  Furthermore, since the number of points serving as reference points is limited to the number of bulk cells, it is possible to easily set the reference points and reduce the man-hours required for arranging the dummy wiring patterns.

  In addition, since the bulk cell is usually not connected to other functional cells or the like by wiring, there is a high possibility that an empty wiring area is detected around the bulk cell. On the other hand, for example, wirings connecting with other functional cells are complicatedly drawn around the functional cells, so that the possibility of detecting an empty wiring region is low. In the first embodiment, since the empty wiring area is searched around the bulk cell, the empty wiring area can be found efficiently, and as a result, many dummy wiring patterns can be arranged. Become.

[Second Embodiment]
Next, a more specific embodiment of the layout design method of the first embodiment will be described as a second embodiment.

The layout design of the second embodiment is performed by a layout design apparatus.
FIG. 2 is a diagram illustrating an example of hardware of the layout design apparatus according to the second embodiment.

  The entire layout design apparatus 10 is controlled by a CPU (Central Processing Unit) 11. A RAM (Random Access Memory) 12 and a plurality of peripheral devices are connected to the CPU 11 via a bus 18.

  The RAM 12 is used as a main storage device of the layout design apparatus 10. The RAM 12 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 11. The RAM 12 stores various data necessary for processing by the CPU 11.

  Peripheral devices connected to the bus 18 include a hard disk drive (HDD) 13, a graphic processing device 14, an input interface 15, an optical drive device 16, and a communication interface 17.

  The HDD 13 magnetically writes and reads data to and from the built-in disk. The HDD 13 is used as a secondary storage device of the layout design apparatus 10. The HDD 13 stores an OS program, application programs, and various data. As the secondary storage device, a semiconductor storage device such as a flash memory can be used.

  A monitor 14 a is connected to the graphic processing device 14. The graphic processing device 14 displays an image on the screen of the monitor 14 a in accordance with a command from the CPU 11. Examples of the monitor 14a include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 15 a and a mouse 15 b are connected to the input interface 15. The input interface 15 transmits signals sent from the keyboard 15a and the mouse 15b to the CPU 11. The mouse 15b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 16 reads data recorded on the optical disc 16a using a laser beam or the like. The optical disk 16a is a portable recording medium on which data is recorded so that it can be read by reflection of light. The optical disc 16a includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (ReWritable), and the like.

  The communication interface 17 is connected to the network 19. The communication interface 17 transmits and receives data to and from other computers or communication devices via the network 19.

  The processing functions of the second embodiment can be realized by the hardware as described above. Note that the processing functions of the layout design apparatus 10 may be realized by a plurality of layout design apparatuses.

Next, a layout design procedure according to the second embodiment will be described.
FIG. 3 is a flowchart showing an example of a layout design procedure according to the second embodiment.

  [Step S11] The layout design apparatus 10 performs placement and routing of the semiconductor integrated circuit in the layout area. Here, the layout area indicates a chip area expressed on the design data. In addition, the layout region includes a plurality of wiring layer regions (multilayer wiring layer regions) stacked. In this step, a plurality of functional cells and a plurality of bulk cells having different sizes are arranged, and further, wirings connecting the functional cells are drawn. The wiring is, for example, metal wiring such as aluminum (Al) wiring or copper (Cu) wiring.

  Here, the functional cell is a cell for realizing a predetermined function (for example, an OR gate, an AND gate, etc.), and includes a bulk layer (a semiconductor substrate, and a gate electrode layer formed on the semiconductor substrate, A layer in which a plurality of transistors are formed) and a wiring layer (for example, a metal wiring layer such as an aluminum wiring or a copper wiring).

  A bulk cell is a cell that is used when changing the logic of a semiconductor integrated circuit, and includes a bulk layer and does not include a wiring layer. An example of a bulk cell is a gate array, for example.

  FIG. 4 is a diagram illustrating an example of a layout area where placement and routing has been performed. In FIG. 4, a plurality of functional cells and a plurality of bulk cells having different sizes are arranged in the layout region 100, and a plurality of wirings are drawn. Note that dotted lines drawn in a matrix form in the drawing indicate wiring arrangement positions (also referred to as wiring tracks). The interval between dotted lines drawn in a matrix corresponds to the wiring pitch.

[Step S12] The layout design apparatus 10 sets the size of the bulk cell to be extracted.
[Step S13] The layout design apparatus 10 extracts a bulk cell having a set size or larger from among the bulk cells arranged in the layout area. As described above, by selectively extracting bulk cells having a size larger than the set size, the number of bulk cells to be extracted can be adjusted. When all the bulk cells arranged in the layout area are extracted, step S12 may be omitted.

[Step S14] The layout design device 10 arranges a dummy short wiring pattern in the layout area.
[Step S15] The layout design apparatus 10 connects the dummy short wiring pattern arranged in the layout area and ends the process.

Next, the arrangement of the dummy short wiring pattern in step S14 shown in FIG. 3 will be described in detail.
FIG. 5 is a flowchart showing an example of the arrangement procedure of the dummy short wiring pattern according to the second embodiment.

[Step S21] The layout design apparatus 10 selects one of the bulk cells extracted in step S13 shown in FIG.
[Step S22] The layout design apparatus 10 sets a reference point in the selected bulk cell. For example, the reference point is set at the intersection of the wiring tracks closest to the center coordinates of the bulk cell.

  [Step S23] The layout design apparatus 10 selects a search direction for searching for an empty wiring area. The search direction is selected from, for example, four directions of up / down / left / right. Note that the direction once selected in the series of processes is excluded from the options.

  In addition, how to change the coordinate (X, Y) at the time of the search of each direction is as follows. That is, in the upward direction, the X coordinate is not changed, and the Y coordinate is changed in the “+” direction. In the downward direction, the X coordinate is not changed, and the Y coordinate is changed in the “−” direction. In the case of the left direction, the X coordinate is changed in the “−” direction, and the Y coordinate is not changed. In the case of the right direction, the X coordinate is changed in the “+” direction, and the Y coordinate is not changed.

  [Step S24] The layout design apparatus 10 selects a wiring layer region to be searched from among the plurality of stacked wiring layer regions. Here, among the plurality of wiring layer regions, the lowermost wiring layer region is selected with the highest priority, and then the wiring layer region closer to the lowermost wiring layer region is selected with priority.

[Step S25] The layout design apparatus 10 calculates the length (L) of the wiring area necessary for the placement of the dummy short wiring pattern. The length (L) is calculated by the following equation, for example.
L = a + (e1 × 3) + (e2 × 2)
Here, (a) shows the length from the reference point to the end of the bulk cell, (e1) shows the length (minimum wiring interval) obtained by rounding up the length of the minimum spacing error to a multiple of the wiring pitch, (E2) indicates a length (minimum wiring width) obtained by rounding up the length of the minimum width error to a multiple of the wiring pitch.

Note that step S25 can be omitted if the length (L) is calculated in advance.
[Step S26] The layout design apparatus 10 searches for a free wiring area having a length (L) in the selected search direction starting from the reference point. If there is a free wiring area, the layout design device 10 advances the process to step S27. If there is no free wiring area, the layout design device 10 advances the process to step S28.

  [Step S27] The layout design apparatus 10 places a dummy short wiring pattern in the detected empty wiring area. For example, the dummy short wiring pattern is arranged with a length of (e1 + (e2 × 2)) from a coordinate separated by (a + e1) from the reference point.

  [Step S28] The layout design apparatus 10 determines whether all wiring layer regions have been selected. When all the wiring layer regions are selected, the layout design device 10 advances the process to step S29. If not all the wiring layer regions have been selected, the layout design device 10 returns the process to step S24.

  [Step S29] It is determined whether the layout design apparatus 10 has selected all search directions (up, down, left, and right). When all the search directions are selected, the layout design device 10 advances the process to step S30. If all the search directions have not been selected, the layout design device 10 returns the process to step S23.

  [Step S30] The layout design apparatus 10 determines whether all the extracted bulk cells have been selected. When all the bulk cells are selected, the layout design device 10 ends the process. If all the bulk cells have not been selected, the layout design device 10 returns the process to step S21.

In this way, the dummy short wiring pattern is arranged in the layout area.
FIG. 6 is a diagram illustrating an example of a layout area in which dummy short wiring patterns are arranged. In FIG. 6, the bulk cell 110 is arranged in the layout region 100. A reference point 111 is set in the bulk cell 110.

  Further, a dummy short wiring pattern 120 is disposed in the second wiring layer region in the downward direction of the reference point 111. The dummy short wiring pattern 120 is arranged away from the reference point 111 by (a + e1), and has a length of (e1 + (e2 × 2)).

  Further, a dummy short wiring pattern 130 is arranged in the first wiring layer region (lowermost wiring layer region) in the right direction of the reference point 111. The dummy short wiring pattern 130 is arranged away from the reference point 111 by (a + e1), and has a length of (e1 + (e2 × 2)).

Here, the dummy short wiring pattern 140 in the drawing is a dummy short wiring pattern arranged in the second wiring layer region with reference to another bulk cell.
In the semiconductor integrated circuit designed and generated by the processes shown in FIGS. 3 and 5, the size set in step S12 in FIG. 3 among the plurality of bulk cells having different sizes arranged in the chip region. The dummy short wiring pattern is selectively arranged with respect to a large bulk cell by being separated by the minimum wiring interval.

Next, the connection of the dummy short wiring pattern in step S15 shown in FIG. 3 will be described in detail.
7 to 9 are flowcharts showing an example of a procedure for connecting the dummy short wiring pattern according to the second embodiment.

  [Step S41] The layout design apparatus 10 sets both ends of all dummy short wiring patterns arranged in the layout area as terminals. Here, the layout design apparatus 10 gives the same attribute to all the dummy short wiring patterns.

[Step S42] The layout design apparatus 10 extracts all the dummy short wiring patterns arranged in the layout area.
[Step S43] The layout design apparatus 10 selects one of the extracted dummy short wiring patterns.

  [Step S44] The layout design apparatus 10 determines one terminal of the selected dummy short wiring pattern as a terminal (L1P1) as a starting point. Note that the other terminal of the selected dummy short wiring pattern is set as a terminal (L1P2) which is an end point.

  [Step S45] The layout design device 10 searches for a terminal (L2P1) having a short distance from the terminal (L1P1). The search is performed, for example, by widening a rectangular ring-shaped search range at a wiring pitch interval. The inclination and direction for starting the search are arbitrarily set.

[Step S46] The layout design apparatus 10 calculates the slope (AG1) of a straight line connecting the terminal (L1P1) and the terminal (L2P1).
FIG. 10 is a diagram illustrating an example of a connection process of dummy short wiring patterns. FIG. 10 corresponds to the example shown in FIG. 6 and shows the process up to step S46.

  In FIG. 10, one terminal 121 of the dummy short wiring pattern 120 is set as a terminal (L1P1) as a starting point, and the other terminal 122 is set as a terminal (L1P2) as an end point.

  Then, the terminal (L2P1) is searched from the terminal 121 (L1P1) as a starting point. A multi-stage rectangular frame in the figure indicates a search range 200 that is widened with a wiring pitch interval. A slope 201 in the figure indicates a search start slope.

As a result of the search, one terminal 131 of the dummy short wiring pattern 130 is set as a terminal (L2P1). An inclination 202 in the figure indicates an inclination (AG1).
[Step S47] The layout design apparatus 10 connects the terminal (L1P1) and the terminal (L2P1) using a dummy connection wiring pattern. When connecting, the uppermost wiring layer region is used with the highest priority in each wiring direction, and then the wiring layer region closer to the uppermost wiring layer region is used with priority.

Here, in the description, when simply referred to as a dummy wiring pattern, both a dummy short wiring pattern and a dummy connection wiring pattern are included.
11 and 12 are diagrams showing an example of connection of dummy short wiring patterns. 11 and 12 correspond to the example shown in FIG.

  In the example shown in FIG. 11, the terminal 121 (L1P1) of the dummy short wiring pattern 120 and the terminal 131 (L2P1) of the dummy short wiring pattern 130 are a dummy connection wiring pattern 150 extending in the left-right direction and a vertical direction. Are connected by a dummy connection wiring pattern 160 extending in a horizontal direction. The dummy connection wiring pattern 150 is arranged in the third wiring layer region, and the dummy connection wiring pattern 160 is arranged in the fourth wiring layer region. Each dummy wiring pattern is connected via a contact pattern.

  Further, in the example shown in FIG. 12, the terminal 121 (L1P1) of the dummy short wiring pattern 120 and the terminal 131 (L2P1) of the dummy short wiring pattern 130 are a dummy connection wiring pattern 170 extending in the vertical direction, and They are connected by a dummy connection wiring pattern 180 extending in the left-right direction. The dummy connection wiring pattern 170 is disposed in the fourth wiring layer region, and the dummy connection wiring pattern 180 is disposed in the third wiring layer region. Each dummy wiring pattern is connected via a contact pattern.

[Step S48] The layout design apparatus 10 determines the other terminal of the dummy short wiring pattern in which the terminal (L2P1) is set as the terminal (L2P2) serving as the starting point.
[Step S49] The layout design device 10 searches for a terminal (L3P1) having a short distance from the terminal (L2P2). The search is performed, for example, by widening a rectangular ring-shaped search range at a wiring pitch interval. The inclination for starting the search is the inclination (AG1), and the search is performed clockwise.

[Step S50] The layout design device 10 calculates the slope (AG2) of a straight line connecting the terminal (L2P2) and the terminal (L3P1).
FIG. 13 is a diagram illustrating an example of a connection process of dummy short wiring patterns. FIG. 13 corresponds to the example shown in FIG. 12, and shows the process up to step S50.

In FIG. 13, the other terminal 132 of the dummy short wiring pattern 130 is set as a terminal (L2P2) as a starting point.
Then, the terminal (L3P1) is searched from the terminal 132 (L2P2) as a starting point. A multi-stage rectangular frame in the figure indicates a search range 200 that is widened with a wiring pitch interval. In addition, the inclination 202 (AG1) is the search start inclination.

  As a result of the search, one terminal 141 of the dummy short wiring pattern 140 is set as a terminal (L3P1). An inclination 203 in the figure indicates an inclination (AG2). The other terminal 142 of the dummy short wiring pattern 140 is set to a terminal (L3P2) that is the next starting point.

  FIG. 14 is a diagram illustrating an example of a terminal search route. FIG. 14 corresponds to the example shown in FIG. 13 and shows a search route 210 when searching for a terminal (L3P1).

  The search route 210 is set clockwise from the inclination 202 (AG1) as a starting point along the search range 200 indicated by the multi-stage rectangular frame in FIG. In addition, the search route 210 moves to the outer stage after one round of the search range 200.

  [Step S51] The layout design apparatus 10 connects the terminal (L2P2) and the terminal (L3P1) using a dummy connection wiring pattern. When connecting, the uppermost wiring layer region is used with the highest priority in each wiring direction, and then the wiring layer region closer to the uppermost wiring layer region is used with priority.

  [Step S52] The layout design apparatus 10 determines whether or not a direction for searching for terminals has been determined. If the search direction is determined, the layout design device 10 advances the process to step S54. If the search direction has not been determined, the layout design device 10 advances the process to step S53.

  [Step S53] The layout design device 10 compares the inclination (AG1) and the inclination (AG2), and determines the search direction based on the comparison result. Specifically, when the inclination (AG2) is within 180 ° clockwise with respect to the inclination (AG1), the search direction is clockwise, and in other cases, the search direction is counterclockwise. To do.

[Step S54] The layout design apparatus 10 sets the inclination (AG2) to the inclination (AGn-1).
[Step S55] The layout design apparatus 10 determines the other terminal of the dummy short wiring pattern connected in the previous stage as a terminal (LnP2) as a starting point.

  [Step S56] The layout design apparatus 10 searches for a terminal (Ln′P1) that is close to the terminal (LnP2). The search direction is the previously determined clockwise or counterclockwise direction.

[Step S57] The layout design apparatus 10 calculates the slope (AGn) of a straight line connecting the terminal (LnP2) and the terminal (Ln′P1).
[Step S58] The layout design apparatus 10 calculates an inclination (AGx) that is a difference in the search direction between the inclination (AGn) and the inclination (AGn-1).

  [Step S59] The layout design apparatus 10 determines whether the inclination (AGx) is within 90 °. If the angle is within 90 °, the layout design device 10 advances the process to step S61. If the angle is not within 90 °, the layout design device 10 advances the process to step S60.

[Step S60] The layout design apparatus 10 sets the inclination (AGn) to the inclination (AGn-1).
[Step S61] The layout design apparatus 10 connects the terminal (LnP2) and the terminal (Ln′P1) using a dummy connection wiring pattern. When connecting, the uppermost wiring layer region is used with the highest priority in each wiring direction, and then the wiring layer region closer to the uppermost wiring layer region is used with priority.

  [Step S62] The layout design apparatus 10 determines whether or not the connection to the terminal (L1P2) that is the end point has been completed. If the connection is completed, the layout design device 10 advances the process to step S63. If the connection has not been completed, the layout design device 10 returns the process to step S55.

  [Step S63] The layout design apparatus 10 determines whether all the extracted dummy short wiring patterns have been connected. When all the dummy short wiring patterns are connected, the layout design apparatus 10 ends the process. If all the dummy short wiring patterns are not connected, the layout design device 10 returns the process to step S43.

  In this way, the dummy short wiring pattern is connected. Thereafter, logical verification and physical verification are performed. Here, the connected dummy short wiring pattern and the connection body of the dummy connection wiring pattern are formed in a loop shape.

FIG. 15 is a diagram illustrating an example of a layout area in which dummy wiring patterns are arranged.
In the example shown in FIGS. 15A and 15B, connection bodies 190 and 191 in which a plurality of dummy short wiring patterns and a plurality of dummy connection wiring patterns are connected are arranged in a loop shape in the layout region 100, respectively. Has been.

  Next, with respect to the layout designed by the process shown in FIG. 3, a method of changing a wiring (adding a new wiring or changing an existing wiring connection route) using a dummy wiring pattern in accordance with the design change will be described. To do.

FIG. 16 is a flowchart illustrating an example of a wiring change procedure according to the second embodiment.
[Step S71] The layout design apparatus 10 extracts the connection source cell terminal (C1) and the connection destination cell terminal (C2) from the layout area. In addition, when there are a plurality of connection destination cell terminals (C2), an intermediate coordinate (Ca) obtained by averaging the coordinates of the plurality of cell terminals (C2) is calculated.

  [Step S72] The layout design device 10 determines the slope (CAG1) of the straight line connecting the cell terminal (C1) and the cell terminal (C2) or the intermediate coordinate (Ca), and the cell terminal (C1) and the cell terminal (C2). ) Or a distance (CDS1) from the intermediate coordinates (Ca).

  [Step S73] The layout design apparatus 10 searches for a dummy wiring pattern having a short distance from the cell terminal (C1). The search is performed, for example, by widening a rectangular ring-shaped search range at a wiring pitch interval. The search range is from the cell terminal (C1) to the distance (CDS1). The inclination and direction for starting the search are arbitrarily set.

  Here, the lowest wiring layer region is searched with the highest priority, and then the wiring layer region closer to the lowest wiring layer region is searched with priority. In addition, when the wiring layer which can be used is limited, it searches to the limited wiring layer.

When a plurality of dummy wiring patterns are detected at the same distance from the cell terminal (C1), the one closer to the cell terminal (C2) or the intermediate coordinate (Ca) is detected.
FIG. 17 is a diagram illustrating an example of a wiring change process. FIG. 17 shows the process up to step S73.

  In FIG. 17, bulk cells 310 and 320 and a connection body 300 in which a plurality of dummy wiring patterns are connected in a loop shape are arranged in the layout region 100. The cell terminal 311 of the bulk cell 310 is extracted as the cell terminal (C1), and the cell terminal 321 of the bulk cell 320 is extracted as the cell terminal (C2).

  Then, a search for a dummy wiring pattern having a short distance is performed starting from the cell terminal 311 (C1). A multi-stage rectangular frame in the figure indicates a search range 200 that is widened with a wiring pitch interval.

  As a result of the search, the dummy short wiring pattern 330 arranged in the first wiring layer region included in the connection body 300 is detected as a dummy wiring pattern having a short distance. An inclination 301 in the figure indicates an inclination (CAG1).

  [Step S74] The layout design apparatus 10 cuts the detected dummy wiring pattern. Thereby, since the connection body including the cut dummy wiring pattern is not in a loop shape, the connection body can function as a wiring.

  [Step S75] The layout design apparatus 10 connects the cell terminal (C1) and the cut dummy wiring pattern using the wiring pattern, and ends the process. For connection, the lowermost wiring layer region is used with the highest priority, and then the wiring layer region closer to the lowermost wiring layer region is used with priority. Here, the same NET name as the wiring pattern used for the connection is given to the connected body including the connected dummy wiring pattern.

FIG. 18 is a diagram illustrating an example of a layout area in which a wiring change has been performed. FIG. 18 corresponds to FIG.
In FIG. 18, the dummy short wiring pattern 330 detected as a dummy wiring pattern that is close to the cell terminal 311 (C1) is cut and divided into a dummy short wiring pattern 330a and a dummy short wiring pattern 330b. Thereby, the loop-like connection body 300 including the dummy short wiring pattern 330 is divided into the connection body 300a and the connection body 300b, and each functions as a wiring.

  And the cut | disconnected dummy short wiring pattern 330b and the cell terminal 311 (C1) are connected via the wiring patterns 341-343. The wiring patterns 341 and 343 extend in the vertical direction and are arranged in the second wiring layer region. The wiring pattern 342 extends in the left-right direction and is disposed in the first wiring layer region.

  The same NET name is given to the wiring patterns 341 to 343 and the connection body 300b. That is, the wiring patterns 341 to 343 and the connection body 300b are wirings (actual wirings) that are part of the semiconductor integrated circuit.

In this way, the wiring is changed using the dummy wiring pattern. Thereafter, logical verification and physical verification are performed.
As described above, in the second embodiment, the coordinates of the bulk cell are used as the reference points for arranging the dummy short wiring patterns (steps S22 and S27 in FIG. 5). According to this configuration, for example, it is not necessary to provide a dedicated cell in order to form a dummy short wiring pattern, so that an increase in chip area can be suppressed.

  Furthermore, since the number of points serving as reference points is limited to the number of bulk cells, it is possible to easily set the reference points and reduce the man-hours required for arranging the dummy short wiring patterns.

  In addition, since the bulk cell is usually not connected to other functional cells or the like by wiring, there is a high possibility that an empty wiring area is detected around the bulk cell. On the other hand, for example, wirings connecting to other functional cells are complicatedly drawn around the functional cells, so that the possibility of detecting an empty wiring region is low (see, for example, FIG. 4). ).

  In the second embodiment, since the empty wiring area is searched around the bulk cell, the empty wiring area can be found efficiently, and as a result, many dummy wiring patterns can be arranged. Become.

  Furthermore, in the second embodiment, when the dummy short wiring pattern is arranged in the layout area, the lowest wiring layer area is given the highest priority among the plurality of wiring layer areas included in the layout area, and then the lowest wiring layer. A dummy short wiring pattern is arranged giving priority to the wiring layer region closer to the region (step S24 in FIG. 5).

  According to this configuration, the wiring pattern or contact pattern used for connecting the dummy short wiring pattern and the terminal such as the bulk cell is arranged using the wiring layer region closer to the lowermost wiring layer region in accordance with the wiring change. (For example, see FIG. 18). Thereby, the number of wiring layers whose wiring is changed can be suppressed.

  Further, in the second embodiment, when the dummy connection wiring pattern is arranged in the layout area, the top wiring layer area is given the highest priority among the plurality of wiring layer areas included in the layout area, and then the top wiring layer area is used. A dummy connection wiring pattern is arranged giving priority to the near wiring layer region (step S47 in FIG. 7, step S51 in FIG. 8, and step S61 in FIG. 9).

  According to this configuration, a wiring space can be secured in a wiring layer region closer to the lowermost wiring layer region, and a wiring pattern used when connecting a dummy short wiring pattern and a terminal such as a bulk cell in accordance with a wiring change Alternatively, the contact pattern can be arranged using a wiring layer region closer to the lowermost wiring layer region (see, for example, FIG. 18). Thereby, the number of wiring layers whose wiring is changed can be further suppressed.

Furthermore, in the second embodiment, the connection body of the dummy short wiring pattern and the dummy connection wiring pattern is formed in a loop shape (see, for example, FIG. 15).
According to this configuration, one terminal of the dummy short wiring pattern can be used as the connection start point, and the other terminal of the same dummy short wiring pattern can be used as the connection end point. That is, if the start point of the connection is determined, the end point can be automatically determined. Thereby, it becomes possible to reduce the man-hour for setting the end point of the connection.

Furthermore, in the second embodiment, the dummy short wiring pattern has a length obtained by adding the minimum wiring interval and twice the minimum wiring width (see, for example, FIG. 6).
According to this configuration, when the dummy short wiring pattern is divided along with the wiring change, the interval between the divided dummy short wiring patterns can be set to be equal to or larger than the minimum wiring interval. The width of the wiring pattern can be made equal to or larger than the minimum wiring width (see, for example, FIG. 18). Thereby, it is possible to change the wiring without violating the design rule.

  Furthermore, in the second embodiment, when extracting the bulk cells arranged in the layout area, the bulk cells to be extracted are selected based on the size of the bulk cells (steps S12 and S13 in FIG. 3).

  According to this configuration, the number of bulk cells to be extracted can be easily adjusted. That is, it is possible to easily adjust the number of dummy short wiring patterns arranged with reference to the coordinates of the extracted bulk cells.

  The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions that the layout design apparatus 10 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic storage device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Magnetic storage devices include hard disk devices (HDD), flexible disks (FD), magnetic tapes, and the like. Optical discs include DVD, DVD-RAM, CD-ROM / RW, and the like. Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time a program is transferred from a server computer connected via a network, the computer can sequentially execute processing according to the received program.

  Further, at least a part of the above processing functions can be realized by an electronic circuit such as a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device).

The following additional notes are further disclosed with respect to the embodiments including the first and second embodiments described above.
(Appendix 1) The layout design device
After layout and wiring of the semiconductor integrated circuit to the layout area,
Extracting bulk cells arranged in the layout area,
In the layout area, search whether there is a free wiring area having a predetermined size around the extracted bulk cell,
As a result of the search, when a free wiring area having the predetermined size is detected, a dummy wiring pattern is arranged in the detected free wiring area on the basis of the coordinates of the extracted bulk cell.
A layout design method characterized by that.

(Additional remark 2) The dummy wiring pattern arrange | positioned in the said dummy wiring pattern arrangement | positioning process has a design change in the said semiconductor integrated circuit, and is used as a part of the said semiconductor integrated circuit when changing wiring,
The layout design method according to appendix 1, wherein:

(Supplementary Note 3) The layout design apparatus includes:
In the dummy wiring pattern placement step,
Among the plurality of wiring layer regions provided in the layout region, the lowermost wiring layer region is given the highest priority, and then the wiring layer region closer to the lowermost wiring layer region is given priority, and the dummy wiring pattern is disposed.
The layout design method according to appendix 1 or 2, wherein:

(Supplementary Note 4) The layout design apparatus includes:
A dummy connection wiring pattern connected to the dummy wiring pattern arranged in the detected empty wiring area is arranged in the layout area;
The layout design method according to any one of appendices 1 to 3, wherein:

(Supplementary Note 5) The layout design apparatus includes:
In the dummy connection wiring pattern arrangement step,
Among the plurality of wiring layer regions provided in the layout region, the uppermost wiring layer region is given the highest priority, and then the wiring layer region closer to the uppermost wiring layer region is given priority, and the dummy connection wiring pattern is disposed.
The layout design method according to appendix 4, characterized in that:

(Supplementary Note 6) The layout design apparatus includes:
In the dummy connection wiring pattern arrangement step,
The dummy connection wiring pattern is arranged in the layout region so that the connection body of the dummy wiring pattern and the dummy connection wiring pattern is in a loop shape.
The layout design method according to appendix 4 or 5, characterized in that:

(Additional remark 7) The dummy wiring pattern arrange | positioned at the said dummy wiring pattern arrangement | positioning process has the length which added the length of 2 times the minimum wiring space | interval and the minimum wiring width,
The layout design method according to any one of supplementary notes 1 to 6, wherein:

(Appendix 8) The layout design apparatus
In the bulk cell extraction step, a bulk cell to be extracted is selected based on the size of the bulk cell.
The layout design method according to any one of supplementary notes 1 to 7, wherein

(Supplementary note 9)
After layout and wiring of the semiconductor integrated circuit to the layout area,
Extracting bulk cells arranged in the layout area,
In the layout area, search whether there is a free wiring area having a predetermined size around the extracted bulk cell,
As a result of the search, when a free wiring area having the predetermined size is detected, a dummy wiring pattern is arranged in the detected free wiring area on the basis of the coordinates of the extracted bulk cell.
A layout design program characterized by causing processing to be executed.

(Supplementary Note 10) Bulk cells arranged in the chip region;
In the chip region, a dummy wiring pattern disposed away from the bulk cell by a minimum wiring interval; and
A semiconductor integrated circuit comprising:

(Appendix 11) The dummy wiring pattern has a length obtained by adding a minimum wiring interval and twice the minimum wiring width.
The semiconductor integrated circuit according to appendix 10, wherein

(Additional remark 12) It further has the dummy connection wiring pattern arrange | positioned in the said chip area | region and connected with the said dummy wiring pattern,
The dummy connection wiring pattern is disposed in an upper wiring layer than the dummy wiring pattern,
12. The semiconductor integrated circuit according to appendix 10 or 11, wherein

(Additional remark 13) The connection body of the said dummy wiring pattern and the said dummy connection wiring pattern is formed in the loop shape,
14. The semiconductor integrated circuit according to any one of appendices 10 to 12, characterized in that:

(Supplementary Note 14) A plurality of bulk cells having different sizes are arranged in the chip region,
Among the plurality of bulk cells, a dummy wiring pattern is selectively arranged with respect to a bulk cell larger than a predetermined size and is spaced apart by a minimum wiring interval.
14. The semiconductor integrated circuit according to any one of appendices 10 to 13, characterized in that:

100 Layout region 110, 310, 320 Bulk cell 111 Reference point 120, 130, 140, 330, 330a, 330b Dummy short wiring pattern 121, 122, 131, 132, 141, 142 Terminal 150, 160, 170, 180 Dummy connecting wiring pattern 190, 191, 300, 300a, 300b Wiring body 200 Search range 201, 202, 203, 301 Slope 210 Search route 311, 321 Cell terminal 341-343 Wiring pattern

Claims (7)

Layout design equipment
After layout and wiring of the semiconductor integrated circuit to the layout area,
Extracting bulk cells arranged in the layout area,
In the layout area, search whether there is a free wiring area having a predetermined size around the extracted bulk cell,
As a result of the search, when a free wiring area having the predetermined size is detected, a dummy wiring pattern is arranged in the detected free wiring area on the basis of the coordinates of the extracted bulk cell.
A layout design method characterized by that. The dummy wiring pattern placed in the dummy wiring pattern placement step has a design change in the semiconductor integrated circuit, and is used as a part of the semiconductor integrated circuit when changing the wiring.
The layout design method according to claim 1, wherein: The layout design apparatus comprises:
In the dummy wiring pattern placement step,
Among the plurality of wiring layer regions provided in the layout region, the lowermost wiring layer region is given the highest priority, and then the wiring layer region closer to the lowermost wiring layer region is given priority, and the dummy wiring pattern is disposed.
3. The layout design method according to claim 1 or 2, wherein The layout design apparatus comprises:
A dummy connection wiring pattern connected to the dummy wiring pattern arranged in the detected empty wiring area is arranged in the layout area;
The layout design method according to claim 1, wherein: The layout design apparatus comprises:
In the dummy connection wiring pattern arrangement step,
Among the plurality of wiring layer regions provided in the layout region, the uppermost wiring layer region is given the highest priority, and then the wiring layer region closer to the uppermost wiring layer region is given priority, and the dummy connection wiring pattern is disposed.
The layout design method according to claim 4. The layout design apparatus comprises:
In the dummy connection wiring pattern arrangement step,
The dummy connection wiring pattern is arranged in the layout region so that the connection body of the dummy wiring pattern and the dummy connection wiring pattern is in a loop shape.
6. The layout design method according to claim 4 or 5, wherein: On the computer,
After layout and wiring of the semiconductor integrated circuit to the layout area,
Extracting bulk cells arranged in the layout area,
In the layout area, search whether there is a free wiring area having a predetermined size around the extracted bulk cell,
As a result of the search, when a free wiring area having the predetermined size is detected, a dummy wiring pattern is arranged in the detected free wiring area on the basis of the coordinates of the extracted bulk cell.
A layout design program characterized by causing processing to be executed.

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