JPH03163851A - Automatic layout system - Google Patents

Automatic layout system

Info

Publication number
JPH03163851A
JPH03163851A JP1304043A JP30404389A JPH03163851A JP H03163851 A JPH03163851 A JP H03163851A JP 1304043 A JP1304043 A JP 1304043A JP 30404389 A JP30404389 A JP 30404389A JP H03163851 A JPH03163851 A JP H03163851A
Authority
JP
Japan
Prior art keywords
redundant
layout
wiring
cells
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1304043A
Other languages
Japanese (ja)
Inventor
Naoya Takahashi
直哉 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1304043A priority Critical patent/JPH03163851A/en
Publication of JPH03163851A publication Critical patent/JPH03163851A/en
Pending legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To enable a layout to be corrected by a partial correction only without resorting to a notable layout alteration after completion of the layout by a method wherein redundant cells are previously arrayed in a layout while a means to make redundant wirings is provided. CONSTITUTION:Cells 12-26 corresponding to the data of a circuit connection data part 8 in an arrangement processor 1 are arranged on cell rows 9-11 quoted from a cell library 7. The kinds, quantities and positions of redundant cells to be arranged in a redundant cell arrangement part 2 are inputted from an arrangement designation part 5 so as to arrange the redundant cells 27-29 between the cells 12-26 previously arranged in the arrangement processor 1. Next, the positions and quantities of wirings in the redundant wiring formation parts are inputted from a wiring designation part 8 so as to make redundant wirings 30-33 according to said input. Finally, wirings 36-38, 42-45 to connect terminals 34, 35, 39-41 according to the data from the circuit data part 8 are made. Through these procedures, the layout can be corrected by partial correction only without resorting to a notable layout alteration after the completion of the layout.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は自動レイアウトシステムに関し、特にほぼ一定
の高さに作成された基本機能セルを主な対象としてレイ
アウトを行うスタンダードセルの自動レイアウトシステ
ムに関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an automatic layout system, and more particularly to an automatic layout system for standard cells that performs layout mainly for basic functional cells created at a substantially constant height. .

〔従来の技術〕[Conventional technology]

従来この種の自動レイアウトシステムは、第9図に示す
ように回路接続情報部77中のデータに対応した基本機
能セル(以下セルと称す)を第2図に示すようなセル列
上に隣接して配置する配置処理部74と、回路接続情報
部77に示される各素子間の接続に従って、配置したセ
ル間の配線を生戒ずる配線処理部75よりなる。ここで
行われるセル力配置、配線の生成は基本的に回路接続情
報77中の素子、信号線と1対1に対応したものであり
、回路接続情報と対応しない余分なセル、配線は1つも
存在しない。
Conventionally, this type of automatic layout system arranges basic functional cells (hereinafter referred to as cells) corresponding to data in the circuit connection information section 77 as shown in FIG. 9 adjacently on a cell column as shown in FIG. and a wiring processing section 75 that carefully arranges wiring between placed cells according to the connections between each element shown in the circuit connection information section 77. The cell placement and wiring generation performed here basically corresponds one-to-one with the elements and signal lines in the circuit connection information 77, and there is no extra cell or wiring that does not correspond to the circuit connection information. not exist.

〔発明の解決しようとする課題〕[Problem to be solved by the invention]

このようなシスデl\によって牛成されたレイアウトは
、セルと配線が隙間なく並べられ、後になって回路にミ
スが発見され回路接続情報が変更された場合など新たに
セル、配線を追加、変更することは難しく実質的に最初
からレイアウトのやり直しになってしまう。
In the layout created by this system, cells and wiring are lined up without gaps, and if a mistake is discovered in the circuit later and the circuit connection information is changed, new cells or wiring can be added or changed. It is difficult to do this, and you will essentially have to redo the layout from the beginning.

本発明の目的は、レイアウト完成後に、大幅なレイアウ
ト変更を行うことなく、部分的な修正だけでレイアウト
修正が可能な自動レイアウトシステムを提供することに
なる。
An object of the present invention is to provide an automatic layout system that can correct the layout by only making partial corrections after the layout is completed, without making major changes to the layout.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の自動レイアウトシステムは、基本機能セルをセ
ル列内に隣接して配置する手段と、前記基本機能セル相
互を接続する配線を前記セル列間に生成する手段とを有
する自動レイアウトシステムにおいて、前記基本機能セ
ルのいずれとも接続関係を持たない所望の基本機能セル
を予めセル列内に配置する手段と、前記基本機能セルの
いずれとも接続されない所望の配線を予め生成する手段
とを有することを特徴とする。
An automatic layout system of the present invention includes means for arranging basic functional cells adjacent to each other in cell rows, and means for generating wiring between the cell rows to connect the basic functional cells to each other, the automatic layout system comprising: The present invention includes means for pre-arranging a desired basic functional cell that has no connection relationship with any of the basic functional cells in a cell column, and means for generating in advance a desired wiring that is not connected to any of the basic functional cells. Features.

〔実施例〕〔Example〕

次に本発明について図面を参照して詳細に説明する。第
1図は本発明の一実施例を説明するためのブロック図、
第2図〜第5図はこれによりレイアウトの過程を示した
図、第6図は本発明により生戒されたレイアウトに対じ
人修正を行った場合の例を示す図である。
Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram for explaining one embodiment of the present invention,
FIGS. 2 to 5 are diagrams showing the layout process using this method, and FIG. 6 is a diagram showing an example of a case where personal corrections are made to the layout prepared according to the present invention.

第1図に示すように、配置処理部1ては従来の自動レイ
アウトシステムと同様に回路接続情報部8のテータに対
応するセルを、セルライブラリ7より引用したセル列上
に配置を行う。第2図はセル列上にセルが配置された状
態を示し、9〜1]がセル列、12〜26が配置された
セルである。
As shown in FIG. 1, the placement processing section 1 places cells corresponding to the data in the circuit connection information section 8 on the cell rows quoted from the cell library 7, similar to the conventional automatic layout system. FIG. 2 shows a state in which cells are arranged on cell columns, where 9 to 1] are cell columns and 12 to 26 are arranged cells.

この通常の配置が終了した後、予備的にセル(以下冗長
セルという)配置2を行う。ここでは配置する冗長セル
の種類、個数及び場所を配置指定5から人間が入力しそ
れに従って配置処理部1により既に配置されているセル
の間に冗長セルの配置を行う。第3図において27〜2
9はセルの間に挿入された冗長セルを示している。
After this normal placement is completed, preliminary cell (hereinafter referred to as redundant cell) placement 2 is performed. Here, a person inputs the type, number, and location of redundant cells to be placed from the placement specification 5, and the placement processing unit 1 places the redundant cells between the cells that have already been placed. 27-2 in Figure 3
9 indicates a redundant cell inserted between cells.

次に予備的な配線すなわち冗長配線生戒3を行うが、こ
の配線の位置及び本数の指定は配線指定6から人間が入
力する。この冗長配線が行われた後のレイアウトが第4
図であり、30〜33が生成された冗長配線である。
Next, preliminary wiring, that is, redundant wiring planning 3, is performed, and the designation of the position and number of wiring is entered by a human through wiring designation 6. The layout after this redundant wiring is
In the figure, 30 to 33 are generated redundant wirings.

次に、配線処理4を行う。この配線は従来の自動レイア
ウトシステムと同様であり、回路接続情報部8のテータ
に従ってセルの端子間を結ぶ配線を生成する。こうして
作成されたレイアウトが第5図であり、通常のセル34
.35等、配線36 37.38等の他に、冗長セル3
9〜41、冗長配線42〜45が存在している。
Next, wiring processing 4 is performed. This wiring is similar to the conventional automatic layout system, and generates wiring that connects the terminals of the cells according to the data in the circuit connection information section 8. The layout created in this way is shown in FIG. 5, with normal cells 34
.. 35 etc., wiring 36 37. In addition to 38 etc., redundant cell 3
9 to 41 and redundant wiring lines 42 to 45 are present.

こうして完成したレイアウトに対し、その後、人手で修
正を加える必要が生した場合、例えば第5図のセル34
からセル35につながる配線を途中冗長セル40を経由
するように変更した例が第6図である。ここでは第5図
の配線38のかわりに配線46を、さらに配線47.4
8を加えることによって容易に所望の回路変更が実現で
きている。
If it becomes necessary to make manual corrections to the layout completed in this way, for example, cell 34 in FIG.
FIG. 6 shows an example in which the wiring connected from the cell 35 to the cell 35 is changed to pass through a redundant cell 40 on the way. Here, wiring 46 is used instead of wiring 38 in FIG. 5, and wiring 47.4 is also used.
By adding 8, the desired circuit change can be easily realized.

第7図は本発明の第2の実施例を説明するためのブロッ
ク図である。
FIG. 7 is a block diagram for explaining a second embodiment of the present invention.

本実施例では第■の実施例に加え、冗長配線本数見積り
処理51が加えられている。第1の実施例では冗長配線
の指定は人間が行っていたが、こ5 こでは各配線チャネル毎に配置されている冗長セルの種
類、個数によって必要とされる冗長配線の本数を計算し
、決定する。例えば第8図に示したレイアウトの場合、
配線チャネル57には冗長セル59の端子64,65、
冗長セル60の端子66,67、計4端子が存在する。
In this embodiment, in addition to the second embodiment, a process 51 for estimating the number of redundant wirings is added. In the first embodiment, redundant wiring was specified by humans, but in this case, the number of redundant wiring required is calculated based on the type and number of redundant cells arranged for each wiring channel. decide. For example, in the case of the layout shown in Figure 8,
The wiring channel 57 has terminals 64, 65 of the redundant cell 59,
There are terminals 66 and 67 of the redundant cell 60, a total of four terminals.

従ってこれらのセルをすべて使用した場合でも配線は4
本用意しておけば足りることになるが、この例で使用し
ているセルは、セルの上下に等価な端子(例えばセル5
9の端子62と64など)を設けているので実際にはこ
の半分の2本の配線を用意しておけば充分と思われる。
Therefore, even if all these cells are used, the wiring will be 4
It is sufficient to prepare this book, but the cell used in this example has equivalent terminals above and below the cell (for example, cell 5
9 terminals 62 and 64, etc.), it would actually be sufficient to prepare two half the number of wires.

従って各配線チャネル毎に(冗長セルの端子数の和〉÷
2の計算の冗長配線見積り処理51で行い、その結果に
基づき冗長配線の生成52を行う。このように使用する
セルライブラリ、用途に応じた計算式を用意しておくこ
とにより、自動的に冗長配線本数の決定が行われる。
Therefore, for each wiring channel (sum of number of terminals of redundant cells) ÷
The redundant wiring estimation process 51 of calculation 2 is performed, and the redundant wiring generation 52 is performed based on the result. By preparing calculation formulas according to the cell library to be used and the application in this way, the number of redundant wirings can be automatically determined.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、予めレイアウト6 中に冗長なセルを配置し、冗長な配線を生成する手段を
有することにより、レイアウト完成後の回路修正に対応
したレイアウト修正を行う場き、大幅なレイアウト変更
を行わずに部分的な修正だけで対応できる場合が多くな
るという結果がある。
As explained above, the present invention has a means for arranging redundant cells in the layout 6 in advance and generating redundant wiring, so that when the layout is modified in response to circuit modification after the layout is completed, it is possible to significantly reduce the The result is that in many cases it is possible to respond with only partial modifications without major layout changes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を説明するためのブロック図
、第2図及至第5図は本発明により作戒されるレイアウ
1−の過程を示す図、第6図は本発明により作成された
レイアウトに対し人手で修正を加えた場合の例を示す図
、第7図は本発明の第2の実施例を説明するためのブロ
ック図、第8図はその処理対象となるレイアウト例を示
す図、第9図は従来を説明するためのブロック図である
。 1,49.74・・・配線処理部、2.50・・・冗長
セル配置部、3,52・・・冗長配線生成部、4.53
 75・・・配線処理部、5.54・・・配置指定、6
・・・配線指定、7,.55.76・・・セルライブラ
イ、8,56.77・・・回路接続情報部、9〜11・
・・セル列、12〜26,34.35・・・セル、27
〜29 39〜41.59〜61・・・冗長セル、30
〜33 42〜45・・・冗長配線、36〜38,46
〜48・・・配線、51・・・冗長配線見積り、57,
58・・・配線チャネル、62〜73・・・端子。
FIG. 1 is a block diagram for explaining one embodiment of the present invention, FIGS. 2 to 5 are diagrams showing the process of layout 1- created according to the present invention, and FIG. 6 is a diagram created according to the present invention. 7 is a block diagram for explaining the second embodiment of the present invention, and FIG. 8 is a diagram showing an example of the layout to be processed. The figure shown in FIG. 9 is a block diagram for explaining the conventional method. 1,49.74... Wiring processing unit, 2.50... Redundant cell arrangement unit, 3,52... Redundant wiring generating unit, 4.53
75... Wiring processing section, 5.54... Placement specification, 6
...Wiring specification, 7,. 55.76...Cell live, 8,56.77...Circuit connection information department, 9-11.
...Cell row, 12-26, 34.35...Cell, 27
~29 39~41.59~61...redundant cell, 30
~33 42~45...Redundant wiring, 36~38,46
~48...Wiring, 51...Redundant wiring estimate, 57,
58... Wiring channel, 62-73... Terminal.

Claims (1)

【特許請求の範囲】[Claims] 基本機能セルをセル列内に隣接して配置する手段と、前
記基本機能セル相互を接続する配線を前記セル列間に生
成する手段とを有する自動レイアウトシステムにおいて
、前記基本機能セルのいずれとも接続関係を持たない所
望の基本機能セルを予めセル列内に配置する手段と、前
記基本機能セルのいずれとも接続されない所望の配線を
予め生成する手段とを有することを特徴とする自動レイ
アウトシステム。
In an automatic layout system comprising means for arranging basic functional cells adjacent to each other in a cell row, and means for generating wiring between the cell rows that connects the basic functional cells, the wiring is connected to any of the basic functional cells. An automatic layout system comprising: means for pre-arranging unrelated desired basic functional cells in a cell column; and means for pre-generating desired wiring that is not connected to any of the basic functional cells.
JP1304043A 1989-11-21 1989-11-21 Automatic layout system Pending JPH03163851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1304043A JPH03163851A (en) 1989-11-21 1989-11-21 Automatic layout system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1304043A JPH03163851A (en) 1989-11-21 1989-11-21 Automatic layout system

Publications (1)

Publication Number Publication Date
JPH03163851A true JPH03163851A (en) 1991-07-15

Family

ID=17928364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1304043A Pending JPH03163851A (en) 1989-11-21 1989-11-21 Automatic layout system

Country Status (1)

Country Link
JP (1) JPH03163851A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08186177A (en) * 1994-12-28 1996-07-16 Nec Corp Semiconductor integrated circuit
JP2012043894A (en) * 2010-08-17 2012-03-01 Toshiba Corp Design method of semiconductor integrated circuit
JP2012243791A (en) * 2011-05-16 2012-12-10 Fujitsu Semiconductor Ltd Layout design method and layout design program

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08186177A (en) * 1994-12-28 1996-07-16 Nec Corp Semiconductor integrated circuit
JP2012043894A (en) * 2010-08-17 2012-03-01 Toshiba Corp Design method of semiconductor integrated circuit
JP2012243791A (en) * 2011-05-16 2012-12-10 Fujitsu Semiconductor Ltd Layout design method and layout design program

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