WO2024057763A1 - I/o circuit, semiconductor device, cell library, and method for designing circuit of semiconductor device - Google Patents

I/o circuit, semiconductor device, cell library, and method for designing circuit of semiconductor device Download PDF

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WO2024057763A1
WO2024057763A1 PCT/JP2023/028414 JP2023028414W WO2024057763A1 WO 2024057763 A1 WO2024057763 A1 WO 2024057763A1 JP 2023028414 W JP2023028414 W JP 2023028414W WO 2024057763 A1 WO2024057763 A1 WO 2024057763A1
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Prior art keywords
circuit
transistor
protection element
cell
line
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PCT/JP2023/028414
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French (fr)
Japanese (ja)
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俊太 山岡
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ローム株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Definitions

  • the invention disclosed herein relates to an I/O [input/output] circuit, a semiconductor device, a cell library, and a circuit design method for a semiconductor device.
  • circuit design of a semiconductor device is performed by arbitrarily combining multiple types of standard cells included in a cell library.
  • Patent Documents 1 and 2 can be cited as prior art related to the above.
  • JP2010-28126A Japanese Patent Application Publication No. 2010-192932
  • the I/O circuit disclosed in this specification is formed by arbitrarily combining multiple types of standard cells included in a cell library, and the I/O circuit included in the multiple types of standard cells is
  • the I/O cell includes a first protection element connected between a signal line and a power line, and a second protection element connected between the signal line and a ground line. a second element formation area configured such that a third protection element connected between the power supply line and the ground line is formed; All three protection elements are formed in a common well.
  • FIG. 1 is a diagram showing an example of the configuration of a semiconductor device.
  • FIG. 2 is a diagram showing a first comparative example of an I/O circuit.
  • FIG. 3 is a diagram showing a second comparative example of the I/O circuit.
  • FIG. 4 is a diagram showing a planar layout of an I/O circuit in a second comparative example.
  • FIG. 5 is a diagram showing a vertical cross section of an I/O circuit in a second comparative example.
  • FIG. 6 is a diagram illustrating a novel embodiment of an I/O circuit.
  • FIG. 7 is a diagram showing a planar layout of the I/O circuit in the embodiment.
  • FIG. 8 is a diagram showing a vertical cross section of the I/O circuit in the embodiment.
  • FIG. 1 is a diagram showing an example of the configuration of a semiconductor device.
  • the semiconductor device 1 of this configuration example is an LSI [large scale integrated circuit] that integrates a CMOS [complementary metal oxide semiconductor] circuit (logic/analog mixed circuit) that is mainly driven at 5 V or less.
  • CMOS complementary metal oxide semiconductor
  • I/O circuit 10 having an ESD protection function and a signal input/output function is arranged.
  • the semiconductor device 1 includes various internal circuits such as a logic circuit LOGIC, an analog circuit ANALOG, an interface circuit I/F, a nonvolatile memory NVM, and a volatile memory SRAM. , a digital/analog converter DAC, an analog/digital converter ADC, and a regulator LDO are integrated.
  • the I/O circuit 10 may be arranged along the four sides of the semiconductor device 1 so as to surround the above-mentioned internal circuit in a plan view of the semiconductor device 1.
  • the semiconductor device 1 controls a controller (such as an ECU [electronic control unit]) installed in various terminal devices (such as an LED [light emitting diode] lamp, a motor, or a switch) in response to a command via an in-vehicle network.
  • a controller such as an ECU [electronic control unit]
  • terminal devices such as an LED [light emitting diode] lamp, a motor, or a switch
  • an in-vehicle network such as an LED [light emitting diode] lamp, a motor, or a switch
  • IC integrated circuit
  • the interface circuit I/F may be compliant with any in-vehicle network (for example, LIN [local interconnect network], CXPI [clock extension peripheral interface], and CAN [controller area network]).
  • the I/O circuit 10 of the first comparative example is formed by arbitrarily combining multiple types of standard cells included in the I/O cell library 100.
  • the I/O cell library 100 is read from a circuit design program executed by a computer, and can be understood as a type of circuit design database.
  • each of the plurality of types of standard cells described above is provided with an interface function (ESD protection function and signal input/output function) with the outside of the device.
  • interface function ESD protection function and signal input/output function
  • the multiple types of standard cells listed above have their own shapes and layouts so that even if one standard cell is replaced with another standard cell, there is no need to make any modifications to the standard cells placed around it. has been standardized.
  • a circuit design method for the semiconductor device 1 (particularly the I/O circuit 10) using the I/O cell library 100 will be briefly described. First, a step of selecting and arranging a plurality of types of standard cells included in the I/O cell library 100 and combining them arbitrarily is carried out. Next, a step of laying power supply lines, signal lines, etc. to connect the arbitrarily combined plural types of standard cells and other circuit blocks is carried out. Finally, a step is performed to verify whether the designed circuit satisfies desired conditions (electrical characteristics, etc.).
  • the I/O circuit 10 of this comparative example is formed by combining the I/O cell 110, the VCC cell 120, and the GND cell 130 as the plurality of types of standard cells described above. There is.
  • the I/O cell 110 is one of the standard cells arranged in the immediate vicinity of the signal terminal T1 connected to the signal line L1.
  • the I/O cell 110 includes a transistor P1 (for example, a PMOSFET [P-channel type MOS field effect transistor]), a transistor N1 (for example, an NMOSFET [N-channel type MOSFET]), and a diode. D1 and D2.
  • the source and back gate of the transistor P1 are both connected to the power supply line L2.
  • the source and back gate of transistor N1 are both connected to ground line L3.
  • the drains of transistors P1 and N1 are both connected to an internal circuit (not shown).
  • the gates of transistors P1 and N1 are both connected to signal terminal T1 via signal line L1.
  • Transistors P1 and N1 connected in this way form a CMOS inverter (so-called input buffer). Note that an output buffer or an input/output buffer may be formed in the I/O cell 110 instead of the input buffer.
  • the anode of the diode D1 and the cathode of the diode D2 are both connected to the signal line L1.
  • the cathode of the diode D1 is connected to the power supply line L2.
  • the anode of diode D2 is connected to ground line L3.
  • the diodes D1 and D2 connected in this manner each function as an ESD protection element for protecting protected elements (transistors P1 and N1 in this figure) each having a gate electrically connected to the signal terminal T1.
  • the diodes D1 and D2 may each be a body diode of a transistor whose gate and source are shorted.
  • the VCC cell 120 includes a transistor N2 (eg, NMOSFET) and a resistor R2.
  • the drain of the transistor N2 is connected to the power supply line L2.
  • the gate of transistor N2 is connected to the first end of resistor R2.
  • the source and back gate of the transistor N2 and the second end of the resistor R2 are both connected to the ground line L3. Note that the resistor R2 for pulling down the gate of the transistor N2 may be omitted.
  • Transistor N2 connected in this manner functions as an ESD protection element between power supply and ground.
  • the GND cell 130 includes a transistor N3 (eg, NMOSFET) and a resistor R3.
  • the drain of the transistor N3 is connected to the power supply line L2.
  • the gate of transistor N3 is connected to the first end of resistor R3.
  • the source and back gate of the transistor N3 and the second end of the resistor R3 are both connected to the ground line L3. Note that the resistor R3 for pulling down the gate of the transistor N3 may be omitted.
  • the transistor N3 connected in this manner functions as an ESD protection element between the power supply and ground, like the transistor N2 mentioned above.
  • the I/O circuit 10 of the first comparative example when the distance between the signal terminal T1 and the power supply terminal T2 or the ground terminal T3 is long, the current path from the I/O cell 110 to the VCC cell 120 and the GND cell 130 is Wiring impedance increases. As a result, there is a possibility that the ESD protection function of the I/O cell 110 will not be achieved.
  • FIG. 3 is a diagram showing a second comparative example of the I/O circuit.
  • the I/O circuit 10 of the second comparative example is based on the previously mentioned first comparative example (FIG. 2), but in addition to the previously mentioned I/O cell 110, VCC cell 120, and GND cell 130, It further includes an NC [non-connected] cell 140.
  • the NC cell 140 is one of the standard cells that is not directly connected to any terminal provided on the semiconductor device 1.
  • the NC cell 140 is arranged mainly to fill in the space between a plurality of standard cells. Referring to the figure, the NC cell 140 is placed in the immediate vicinity of the I/O cell 110 (specifically, between the I/O cell 110 and the VCC cell 120).
  • NC cell 140 includes a transistor N4 (eg, NMOSFET) and a resistor R4.
  • the drain of the transistor N4 is connected to the power supply line L2.
  • the gate of transistor N4 is connected to the first end of resistor R4.
  • the source and back gate of the transistor N4 and the second end of the resistor R4 are both connected to the ground line L3. Note that the resistor R4 for pulling down the gate of the transistor N4 may be omitted.
  • Transistor N4 connected in this manner functions as an ESD protection element between the power supply and ground, like the transistors N2 and N3 described above.
  • the NC cell 140 is arranged immediately (or in the vicinity) of the I/O cell 110.
  • a current may flow in a current path from the signal terminal T1 to the ground terminal T3 via the signal line L1, the diode D1, the power line L2, the transistor N4, and the ground line L3.
  • the I/O circuit 10 of the second comparative example even if the distance between the signal terminal T1 and the power supply terminal T2 or the ground terminal T3 is long, the influence of wiring impedance can be suppressed to a small level. As a result, the ESD protection function of the I/O cell 110 is less likely to be impaired.
  • the location where the NC cell 140 is arranged also differs depending on the model. Therefore, it is inevitable that some wiring impedance is attached to the current path for escaping the ESD pulse. Therefore, it is necessary to design the protection element size and arrange the cells in consideration of the wiring impedance.
  • the NC cell 140 cannot be placed immediately (or in the vicinity) of the I/O cell 110, the wiring impedance of the above-described current path may increase. As a result, there is a possibility that the ESD protection function of the I/O cell 110 will not be achieved.
  • FIG. 4 is a diagram showing a planar layout of the I/O circuit 10 in the second comparative example.
  • the I/O cell 110 and the NC cell 140 are individually arranged as independent standard cells. Referring to the figure, the I/O cell 110 and the NC cell 140 are arranged side by side in the left-right direction in the drawing when the semiconductor device 1 is viewed from above.
  • the I/O cell 110 and the NC cell 140 are each independent standard cells.
  • PW type well
  • the distance between the elements separating the diode D2 and the transistor N4 becomes long, which may hinder the reduction in area of the I/O circuit 10 (and by extension, the semiconductor device 1).
  • FIG. 6 is a diagram illustrating a new embodiment of an I/O circuit.
  • the I/O circuit 10 of this embodiment is formed by combining multiple types of standard cells included in the I/O cell library 100.
  • the I/O circuit 10 of this embodiment includes at least an I/O cell 150 as a plurality of types of standard cells.
  • the I/O circuit 10 may include a combination of the previously mentioned VCC cell 120, GND cell 130, and the like.
  • the I/O cell 150 includes a first element formation region 151, a second element formation region 152, and a third element formation region 153.
  • the first element formation region 151 is arranged immediately (or in the vicinity) of the signal terminal T1 connected to the signal line L1. Note that in the first element formation region 151, a transistor P11 (for example, PMOSFET), a transistor N11 (for example, NMOSFET), and a resistor R11 are formed.
  • a transistor P11 for example, PMOSFET
  • a transistor N11 for example, NMOSFET
  • a resistor R11 are formed in the first element formation region 151.
  • the drains of transistors P11 and N11 are both connected to signal line L1.
  • the source, gate, and back gate of the transistor P11 are all connected to the power supply line L2.
  • the gate of transistor N11 is connected to the first end of resistor R11.
  • the source and back gate of the transistor N11 and the second end of the resistor R11 are both connected to the ground line L3. Note that the resistor R11 for pulling down the gate of the transistor N11 may be omitted.
  • the transistors P11 and N11 whose gates and sources are short-circuited are connected to the first ESD protection element connected between the signal line L1 and the power line L2, and the first ESD protection element connected between the signal line L1 and the ground line L3, respectively. It functions as a second ESD protection element connected between.
  • These first and second ESD protection elements each protect protected elements (in this figure, transistors P12 and N13, which will be described later) connected to the signal line L1 from ESD pulses.
  • the transistors P11 and N11 may be replaced with diodes, respectively, as in the first comparative example (FIG. 2) and the second comparative example (FIG. 3).
  • the second element formation region 152 is arranged immediately (or in the vicinity) of the first element formation region 151.
  • the second element formation region 152 is arranged adjacent to the first element formation region 151.
  • the second element formation region 152 is arranged between the signal terminal T1 and the first element formation region 151.
  • a transistor N12 for example, NMOSFET
  • a resistor R12 are formed in the second element formation region 152.
  • the drain of the transistor N12 is connected to the power supply line L2.
  • the gate of transistor N12 is connected to the first end of resistor R12.
  • the source and back gate of the transistor N12 and the second end of the resistor R12 are both connected to the ground line L3. Note that the resistor R12 for pulling down the gate of the transistor N12 may be omitted.
  • the transistor N12 whose gate and source are short-circuited functions as a third ESD protection element connected to the power supply line L2 and the ground line L3. Note that the transistor N12 may be replaced with a diode.
  • the second element formation region 152, the first element formation region 151, and the third element formation region 153 are arranged in order from the side closer to the signal terminal T1.
  • a transistor P12 for example, PMOSFET
  • a transistor N13 for example, NMOSFET
  • the source and back gate of the transistor P12 are both connected to the power supply line L2.
  • the source and back gate of transistor N13 are both connected to ground line L3.
  • the drains of transistors P12 and N13 are both connected to an internal circuit (not shown).
  • the gates of transistors P12 and N13 are both connected to signal terminal T1 via signal line L1.
  • Transistors P12 and N13 connected in this way form a CMOS inverter (so-called input buffer). Note that an output buffer or an input/output buffer may be formed in the third element formation region 153 instead of the input buffer.
  • a current may flow in a current path from the signal terminal T1 to the ground terminal T3 via the signal line L1, the transistor P11, the power supply line L2, the transistor N12, and the ground line L3.
  • the I/O circuit 10 of this embodiment even if the distance between the signal terminal T1 and the power supply terminal T2 or the ground terminal T3 is long, the influence of wiring impedance can be suppressed.
  • the I/O cell 150 can be understood as a combination of the I/O cell 110 and the NC cell 140 of the second comparative example (FIG. 3) into one standard cell. Therefore, it is not necessary to design the protection element size and arrange the cells in consideration of the wiring impedance. Furthermore, there is no need to worry about the ESD protection function failing due to the circuit designer of the semiconductor device 1 forgetting to place the NC cell 140.
  • FIG. 7 is a diagram showing a planar layout of the I/O circuit 10 in this embodiment. As shown in this figure, transistors P11, N11, and N12 (corresponding to the first to third ESD protection elements) are each arranged as one of the components forming a single I/O cell 150. be done.
  • the I/O cell 150 can be understood as a combination of the I/O cell 110 and the NC cell 140 of the second comparative example (FIG. 3) into one standard cell.
  • the inter-element distance separating the transistor N11 and the transistor N12 is shortened, the area of the I/O circuit 10 (and thus the semiconductor device 1) can be reduced.
  • the I/O circuit disclosed in this specification is formed by arbitrarily combining multiple types of standard cells included in a cell library, and the I/O circuit included in the multiple types of standard cells is
  • the I/O cell includes a first protection element connected between a signal line and a power line, and a second protection element connected between the signal line and a ground line. a second element formation area configured such that a third protection element connected between the power supply line and the ground line is formed;
  • the three protection elements are all formed in a common well (first configuration).
  • the I/O circuit according to the first configuration may have a configuration (second configuration) further including a third element formation region configured to form a protected element connected to the signal line. .
  • the protected element may be configured to form an input buffer, an output buffer, or an input/output buffer (third configuration).
  • the first protection element is a P-channel type first transistor, and the source, gate, and back gate of the first transistor are all connected to the power source.
  • a configuration (fourth configuration) may be adopted in which the drain of the first transistor is connected to the signal line and the drain of the first transistor is connected to the signal line.
  • the second protection element is an N-channel type second transistor, and the source, gate, and back gate of the second transistor are all directly connected to each other. Alternatively, it may be indirectly connected to the ground line, and the drain of the second transistor may be connected to the signal line (fifth configuration).
  • the third protection element is an N-channel type third transistor, and the source, gate, and back gate of the third transistor are all directly connected to each other.
  • the third transistor may be indirectly connected to the ground line, and the drain of the third transistor may be connected to the power supply line (sixth configuration).
  • the semiconductor device disclosed in this specification includes an I/O circuit having any one of the first to sixth configurations, an external terminal configured to be connected to the signal line, (seventh configuration).
  • the I/O cell may be arranged in a region immediately below a pad connected to the external terminal (eighth configuration).
  • the cell library disclosed herein includes multiple types that can be read out from a circuit design program executed by a computer and arbitrarily combined to form an I/O circuit of a semiconductor device.
  • the I/O cells included in the plurality of types of standard cells include a first protection element connected between a signal line and a power line and a first protection element connected between the signal line and a ground line. a first element formation region configured such that a second protection element connected therebetween is formed; and a third protection element connected between the power supply line and the ground line
  • the second protective element and the third protective element are both formed in a common well (a ninth configuration).
  • the method for designing a circuit for a semiconductor device disclosed in this specification uses the ninth cell library, and includes selecting and arranging the plurality of types of standard cells included in the cell library. and a step of laying the power supply line, the ground line, and the signal line so as to connect the arbitrarily combined plurality of types of standard cells and other circuit blocks. (10th configuration).

Abstract

This I/O circuit 10 is formed by discretionarily combining a plurality of types of standard cells included in a cell library 100. A standard cell 150 included in the plurality of types of standard cells includes: a first element formation region 151 configured such that a first protection element P11 connected between a signal line and a power supply line and a second protection element N11 connected between the signal line and a ground line are formed; and a second element formation region 152 configured such that a third protection element N12 connected between the power supply line and the ground line is formed. Both the second protection element N11 and the third protection element N12 are formed in a common well.

Description

Ｉ／Ｏ回路、半導体装置、セルライブラリ、半導体装置の回路設計方法I/O circuits, semiconductor devices, cell libraries, circuit design methods for semiconductor devices
　本明細書中に開示されている発明は、Ｉ／Ｏ［input/output］回路、半導体装置、セルライブラリ、及び、半導体装置の回路設計方法に関する。 The invention disclosed herein relates to an I/O [input/output] circuit, a semiconductor device, a cell library, and a circuit design method for a semiconductor device.
　従来、セルライブラリに含まれる複数種類の標準セルを任意に組み合わせることにより半導体装置の回路設計を行う手法が知られている。 Conventionally, a method is known in which circuit design of a semiconductor device is performed by arbitrarily combining multiple types of standard cells included in a cell library.
　なお、上記に関連する従来技術としては、特許文献１及び２を挙げることができる。 Note that Patent Documents 1 and 2 can be cited as prior art related to the above.
特開２０１０－２８１２６号公報JP2010-28126A 特開２０１０－１９２９３２号公報Japanese Patent Application Publication No. 2010-192932
　しかしながら、従来のＩ／Ｏ回路では、信号端子と電源端子又は接地端子との距離が遠いほど信号端子に印加されるＥＳＤ［electro　static　discharge］パルスを逃がし難くなってＥＳＤ耐性の低下を招くおそれがあった。 However, in conventional I/O circuits, the greater the distance between the signal terminal and the power supply terminal or the ground terminal, the more difficult it becomes to escape the ESD [electro static discharge] pulse applied to the signal terminal, which may lead to a decrease in ESD resistance. there were.
　例えば、本明細書中に開示されているＩ／Ｏ回路は、セルライブラリに含まれる複数種類の標準セルを任意に組み合わせることにより形成されるものであって、前記複数種類の標準セルに含まれるＩ／Ｏセルは、信号線と電源線との間に接続される第１保護素子及び前記信号線と接地線との間に接続される第２保護素子が形成されるように構成された第１素子形成領域と、前記電源線と前記接地線との間に接続される第３保護素子が形成されるように構成された第２素子形成領域と、を含み、前記第２保護素子及び第３保護素子は、いずれも共通のウェルに形成されている。 For example, the I/O circuit disclosed in this specification is formed by arbitrarily combining multiple types of standard cells included in a cell library, and the I/O circuit included in the multiple types of standard cells is The I/O cell includes a first protection element connected between a signal line and a power line, and a second protection element connected between the signal line and a ground line. a second element formation area configured such that a third protection element connected between the power supply line and the ground line is formed; All three protection elements are formed in a common well.
　なお、その他の特徴、要素、ステップ、利点、及び、特性については、以下に続く発明を実施するための形態及びこれに関する添付の図面によって、さらに明らかとなる。 Note that other features, elements, steps, advantages, and characteristics will become clearer from the detailed description and accompanying drawings that follow.
　本開示によれば、ＥＳＤ耐性の高いＩ／Ｏ回路を提供することが可能となる。 According to the present disclosure, it is possible to provide an I/O circuit with high ESD resistance.
図１は、半導体装置の一構成例を示す図である。FIG. 1 is a diagram showing an example of the configuration of a semiconductor device. 図２は、Ｉ／Ｏ回路の第１比較例を示す図である。FIG. 2 is a diagram showing a first comparative example of an I/O circuit. 図３は、Ｉ／Ｏ回路の第２比較例を示す図である。FIG. 3 is a diagram showing a second comparative example of the I/O circuit. 図４は、第２比較例におけるＩ／Ｏ回路の平面レイアウトを示す図である。FIG. 4 is a diagram showing a planar layout of an I/O circuit in a second comparative example. 図５は、第２比較例におけるＩ／Ｏ回路の縦断面を示す図である。FIG. 5 is a diagram showing a vertical cross section of an I/O circuit in a second comparative example. 図６は、Ｉ／Ｏ回路の新規な実施形態を示す図である。FIG. 6 is a diagram illustrating a novel embodiment of an I/O circuit. 図７は、実施形態におけるＩ／Ｏ回路の平面レイアウトを示す図である。FIG. 7 is a diagram showing a planar layout of the I/O circuit in the embodiment. 図８は、実施形態におけるＩ／Ｏ回路の縦断面を示す図である。FIG. 8 is a diagram showing a vertical cross section of the I/O circuit in the embodiment.
＜半導体装置＞
　図１は、半導体装置の一構成例を示す図である。本構成例の半導体装置１は、主に５Ｖ以下で駆動するＣＭＯＳ［complementary　metal　oxide　semiconductor］回路（ロジック／アナログ混載回路）を集積化したＬＳＩ［large　scale　integrated　circuit］である。半導体装置１の最外周部には、ＥＳＤ保護機能及び信号入出力機能を担うＩ／Ｏ回路１０が配置されている。 <Semiconductor device>
FIG. 1 is a diagram showing an example of the configuration of a semiconductor device. The semiconductor device 1 of this configuration example is an LSI [large scale integrated circuit] that integrates a CMOS [complementary metal oxide semiconductor] circuit (logic/analog mixed circuit) that is mainly driven at 5 V or less. At the outermost periphery of the semiconductor device 1, an I/O circuit 10 having an ESD protection function and a signal input/output function is arranged.
　半導体装置１には、Ｉ／Ｏ回路１０以外にも、種々の内部回路が集積化されている。本図に即して述べると、半導体装置１には、種々の内部回路として、ロジック回路ＬＯＧＩＣと、アナログ回路ＡＮＡＬＯＧと、インタフェイス回路Ｉ／Ｆと、不揮発性メモリＮＶＭと、揮発性メモリＳＲＡＭと、デジタル／アナログ変換器ＤＡＣと、アナログ／デジタル変換器ＡＤＣと、レギュレータＬＤＯが集積化されている。 In addition to the I/O circuit 10, various internal circuits are integrated in the semiconductor device 1. Referring to this diagram, the semiconductor device 1 includes various internal circuits such as a logic circuit LOGIC, an analog circuit ANALOG, an interface circuit I/F, a nonvolatile memory NVM, and a volatile memory SRAM. , a digital/analog converter DAC, an analog/digital converter ADC, and a regulator LDO are integrated.
　Ｉ／Ｏ回路１０は、半導体装置１の平面視において、上記の内部回路を取り囲むように半導体装置１の四辺に沿って配置してもよい。 The I/O circuit 10 may be arranged along the four sides of the semiconductor device 1 so as to surround the above-mentioned internal circuit in a plan view of the semiconductor device 1.
　半導体装置１としては、例えば、車載ネットワーク経由で指令を受けて各種の末端装置（ＬＥＤ［light　emitting　diode］ランプ、モータ又はスイッチなど）に搭載されたコントローラ（ＥＣＵ［electronic　control　unit］など）を制御する車載向けの統合通信ＩＣ［integrated　circuit］を挙げることができる。この場合、インタフェイス回路Ｉ／Ｆは、任意の車載ネットワーク（例えばＬＩＮ［local　interconnect　network］、ＣＸＰＩ［clock　extension　peripheral　interface］及びＣＡＮ［controller　area　network］）に準拠してもよい。 For example, the semiconductor device 1 controls a controller (such as an ECU [electronic control unit]) installed in various terminal devices (such as an LED [light emitting diode] lamp, a motor, or a switch) in response to a command via an in-vehicle network. One example is an integrated communication IC [integrated circuit] for in-vehicle use. In this case, the interface circuit I/F may be compliant with any in-vehicle network (for example, LIN [local interconnect network], CXPI [clock extension peripheral interface], and CAN [controller area network]).
＜Ｉ／Ｏ回路（第１比較例）＞
　図２は、Ｉ／Ｏ回路の第１比較例（＝後出の実施形態と対比される一般的な構成例）を示す図である。第１比較例のＩ／Ｏ回路１０は、Ｉ／Ｏセルライブラリ１００に含まれる複数種類の標準セルを任意に組み合わせることにより形成されている。Ｉ／Ｏセルライブラリ１００は、コンピュータで実行される回路設計プログラムから読み出されるものであり、回路設計用データベースの一種として理解することができる。 <I/O circuit (first comparative example)>
FIG. 2 is a diagram showing a first comparative example of an I/O circuit (=a general configuration example to be compared with the embodiment described later). The I/O circuit 10 of the first comparative example is formed by arbitrarily combining multiple types of standard cells included in the I/O cell library 100. The I/O cell library 100 is read from a circuit design program executed by a computer, and can be understood as a type of circuit design database.
　なお、上記複数種類の標準セルは、それぞれ、装置外部とのインタフェイス機能（ＥＳＤ保護機能及び信号入出力機能）を備えている。また、上記複数種類の標準セルは、いずれかの標準セルを別の標準セルに置換しても、その周囲に配置された標準セルに一切修正を加える必要がないように、それぞれの形状及びレイアウトが規格化されている。 Note that each of the plurality of types of standard cells described above is provided with an interface function (ESD protection function and signal input/output function) with the outside of the device. In addition, the multiple types of standard cells listed above have their own shapes and layouts so that even if one standard cell is replaced with another standard cell, there is no need to make any modifications to the standard cells placed around it. has been standardized.
　Ｉ／Ｏセルライブラリ１００を用いた半導体装置１（特にＩ／Ｏ回路１０）の回路設計方法について簡単に説明しておく。まず、Ｉ／Ｏセルライブラリ１００に含まれる複数種類の標準セルを選択及び配置して任意に組み合わせるステップを実施する。次に、任意に組み合わされた複数種類の標準セルとその他の回路ブロックとを接続するように電源線及び信号線などを敷設するステップを実施する。最後に、設計済み回路が所望の条件（電気的特性など）を満足しているか否かを検証するステップを実施する。 A circuit design method for the semiconductor device 1 (particularly the I/O circuit 10) using the I/O cell library 100 will be briefly described. First, a step of selecting and arranging a plurality of types of standard cells included in the I/O cell library 100 and combining them arbitrarily is carried out. Next, a step of laying power supply lines, signal lines, etc. to connect the arbitrarily combined plural types of standard cells and other circuit blocks is carried out. Finally, a step is performed to verify whether the designed circuit satisfies desired conditions (electrical characteristics, etc.).
　このようなＩ／Ｏセルライブラリ１００を用いて半導体装置１（特にＩ／Ｏ回路１０）の回路設計を行うことにより、ＥＳＤ耐性、ラッチアップ耐性及び電気的特性などを端子毎に設計する必要がなくなる。従って、回路設計者の負担を減らすとともに設計ミスを減らすことができる。 By designing the circuit of the semiconductor device 1 (particularly the I/O circuit 10) using such an I/O cell library 100, it is no longer necessary to design ESD resistance, latch-up resistance, electrical characteristics, etc. for each terminal. It disappears. Therefore, it is possible to reduce the burden on the circuit designer and reduce design errors.
　なお、本図に即して述べると、本比較例のＩ／Ｏ回路１０は、上記した複数種類の標準セルとしてＩ／Ｏセル１１０、ＶＣＣセル１２０及びＧＮＤセル１３０を組み合わせることにより形成されている。 Note that, referring to this figure, the I/O circuit 10 of this comparative example is formed by combining the I/O cell 110, the VCC cell 120, and the GND cell 130 as the plurality of types of standard cells described above. There is.
　Ｉ／Ｏセル１１０は、信号線Ｌ１に接続される信号端子Ｔ１の直近に配置される標準セルの一つである。本図に即して述べると、Ｉ／Ｏセル１１０は、トランジスタＰ１（例えばＰＭＯＳＦＥＴ［P-channel　type　MOS　field　effect　transistor］）と、トランジスタＮ１（例えばＮＭＯＳＦＥＴ［N-channel　type　MOSFET］）と、ダイオードＤ１及びＤ２と、を含む。 The I/O cell 110 is one of the standard cells arranged in the immediate vicinity of the signal terminal T1 connected to the signal line L1. Referring to this diagram, the I/O cell 110 includes a transistor P1 (for example, a PMOSFET [P-channel type MOS field effect transistor]), a transistor N1 (for example, an NMOSFET [N-channel type MOSFET]), and a diode. D1 and D2.
　トランジスタＰ１のソースとバックゲートは、いずれも電源線Ｌ２に接続されている。トランジスタＮ１のソースとバックゲートは、いずれも接地線Ｌ３に接続されている。トランジスタＰ１及びＮ１それぞれのドレインは、いずれも不図示の内部回路に接続されている。トランジスタＰ１及びＮ１それぞれのゲートは、いずれも信号線Ｌ１を介して信号端子Ｔ１に接続されている。このように接続されたトランジスタＰ１及びＮ１は、ＣＭＯＳインバータ（いわゆる入力バッファ）を形成する。なお、Ｉ／Ｏセル１１０には、入力バッファに代えて出力バッファ又は入出力バッファが形成されてもよい。 The source and back gate of the transistor P1 are both connected to the power supply line L2. The source and back gate of transistor N1 are both connected to ground line L3. The drains of transistors P1 and N1 are both connected to an internal circuit (not shown). The gates of transistors P1 and N1 are both connected to signal terminal T1 via signal line L1. Transistors P1 and N1 connected in this way form a CMOS inverter (so-called input buffer). Note that an output buffer or an input/output buffer may be formed in the I/O cell 110 instead of the input buffer.
　ダイオードＤ１のアノードとダイオードＤ２のカソードは、いずれも信号線Ｌ１に接続されている。ダイオードＤ１のカソードは、電源線Ｌ２に接続されている。ダイオードＤ２のアノードは、接地線Ｌ３に接続されている。このように接続されたダイオードＤ１及びＤ２は、それぞれ、信号端子Ｔ１と導通するゲートを備えた被保護素子（本図ではトランジスタＰ１及びＮ１）を保護するためのＥＳＤ保護素子として機能する。なお、ダイオードＤ１及びＤ２は、それぞれ、ゲート・ソース間がショートされたトランジスタのボディダイオードであってもよい。 The anode of the diode D1 and the cathode of the diode D2 are both connected to the signal line L1. The cathode of the diode D1 is connected to the power supply line L2. The anode of diode D2 is connected to ground line L3. The diodes D1 and D2 connected in this manner each function as an ESD protection element for protecting protected elements (transistors P1 and N1 in this figure) each having a gate electrically connected to the signal terminal T1. Note that the diodes D1 and D2 may each be a body diode of a transistor whose gate and source are shorted.
　ＶＣＣセル１２０は、電源線Ｌ２に接続される電源端子Ｔ２（＝電源電圧ＶＣＣの印加端）の直近に配置される標準セルの一つ（いわゆる電源保護セル）である。本図に即して述べると、ＶＣＣセル１２０は、トランジスタＮ２（例えばＮＭＯＳＦＥＴ）と、抵抗Ｒ２と、を含む。 The VCC cell 120 is one of the standard cells (so-called power protection cell) that is placed in the immediate vicinity of the power supply terminal T2 (=the end to which power supply voltage VCC is applied) connected to the power supply line L2. Referring to this figure, the VCC cell 120 includes a transistor N2 (eg, NMOSFET) and a resistor R2.
　トランジスタＮ２のドレインは、電源線Ｌ２に接続されている。トランジスタＮ２のゲートは、抵抗Ｒ２の第１端に接続されている。トランジスタＮ２のソース及びバックゲートと抵抗Ｒ２の第２端は、いずれも接地線Ｌ３に接続されている。なお、トランジスタＮ２のゲートをプルダウンするための抵抗Ｒ２は、省略され得る。このように接続されたトランジスタＮ２は、電源／接地間のＥＳＤ保護素子として機能する。 The drain of the transistor N2 is connected to the power supply line L2. The gate of transistor N2 is connected to the first end of resistor R2. The source and back gate of the transistor N2 and the second end of the resistor R2 are both connected to the ground line L3. Note that the resistor R2 for pulling down the gate of the transistor N2 may be omitted. Transistor N2 connected in this manner functions as an ESD protection element between power supply and ground.
　ＧＮＤセル１３０は、接地線Ｌ３に接続される接地端子Ｔ３（＝接地電圧ＧＮＤの印加端）の直近に配置される標準セルの一つ（いわゆるＧＮＤ保護セル）である。本図に即して述べると、ＧＮＤセル１３０は、トランジスタＮ３（例えばＮＭＯＳＦＥＴ）と、抵抗Ｒ３と、を含む。 The GND cell 130 is one of the standard cells (so-called GND protection cell) placed in the immediate vicinity of the ground terminal T3 (=the end to which the ground voltage GND is applied) connected to the ground line L3. Referring to this figure, the GND cell 130 includes a transistor N3 (eg, NMOSFET) and a resistor R3.
　トランジスタＮ３のドレインは、電源線Ｌ２に接続されている。トランジスタＮ３のゲートは、抵抗Ｒ３の第１端に接続されている。トランジスタＮ３のソース及びバックゲートと抵抗Ｒ３の第２端は、いずれも接地線Ｌ３に接続されている。なお、トランジスタＮ３のゲートをプルダウンするための抵抗Ｒ３は、省略され得る。このように接続されたトランジスタＮ３は、先出のトランジスタＮ２と同じく、電源／接地間のＥＳＤ保護素子として機能する。 The drain of the transistor N3 is connected to the power supply line L2. The gate of transistor N3 is connected to the first end of resistor R3. The source and back gate of the transistor N3 and the second end of the resistor R3 are both connected to the ground line L3. Note that the resistor R3 for pulling down the gate of the transistor N3 may be omitted. The transistor N3 connected in this manner functions as an ESD protection element between the power supply and ground, like the transistor N2 mentioned above.
　例えば、信号端子Ｔ１に印加されるＥＳＤパルスを接地端子Ｔ３に逃がしてＥＳＤ保護を掛ける場合を考える。この場合、図示の細い矢印で示したように、信号端子Ｔ１から信号線Ｌ１、ダイオードＤ１、電源線Ｌ２、トランジスタＮ２又はＮ３、及び、接地線Ｌ３を介して接地端子Ｔ３に至る電流経路に電流が流れ得る。 For example, consider a case where ESD protection is applied by letting the ESD pulse applied to the signal terminal T1 escape to the ground terminal T3. In this case, as shown by the thin arrow in the figure, a current flows through the current path from the signal terminal T1 to the ground terminal T3 via the signal line L1, the diode D1, the power line L2, the transistor N2 or N3, and the ground line L3. can flow.
　しかし、第１比較例のＩ／Ｏ回路１０では、信号端子Ｔ１と電源端子Ｔ２又は接地端子Ｔ３との距離が遠い場合、Ｉ／Ｏセル１１０からＶＣＣセル１２０及びＧＮＤセル１３０に至る電流経路の配線インピーダンスが大きくなる。その結果、Ｉ／Ｏセル１１０のＥＳＤ保護機能が成立しなくなるおそれがある。 However, in the I/O circuit 10 of the first comparative example, when the distance between the signal terminal T1 and the power supply terminal T2 or the ground terminal T3 is long, the current path from the I/O cell 110 to the VCC cell 120 and the GND cell 130 is Wiring impedance increases. As a result, there is a possibility that the ESD protection function of the I/O cell 110 will not be achieved.
＜Ｉ／Ｏ回路（第２比較例）＞
　図３は、Ｉ／Ｏ回路の第２比較例を示す図である。第２比較例のＩ／Ｏ回路１０は、先出の第１比較例（図２）を基本としつつ、先出のＩ／Ｏセル１１０、ＶＣＣセル１２０、及び、ＧＮＤセル１３０に加えて、ＮＣ［non-connected］セル１４０をさらに含む。 <I/O circuit (second comparative example)>
FIG. 3 is a diagram showing a second comparative example of the I/O circuit. The I/O circuit 10 of the second comparative example is based on the previously mentioned first comparative example (FIG. 2), but in addition to the previously mentioned I/O cell 110, VCC cell 120, and GND cell 130, It further includes an NC [non-connected] cell 140.
　ＮＣセル１４０は、その名の通り、半導体装置１に設けられるいずれの端子にも直接繋がることのない標準セルの一つである。ＮＣセル１４０は、主に複数の標準セルの間を埋めるように配置される。本図に即して述べると、ＮＣセル１４０は、Ｉ／Ｏセル１１０の直近（具体的にはＩ／Ｏセル１１０とＶＣＣセル１２０との間）に配置されている。ＮＣセル１４０は、トランジスタＮ４（例えばＮＭＯＳＦＥＴ）と、抵抗Ｒ４と、を含む。 As its name suggests, the NC cell 140 is one of the standard cells that is not directly connected to any terminal provided on the semiconductor device 1. The NC cell 140 is arranged mainly to fill in the space between a plurality of standard cells. Referring to the figure, the NC cell 140 is placed in the immediate vicinity of the I/O cell 110 (specifically, between the I/O cell 110 and the VCC cell 120). NC cell 140 includes a transistor N4 (eg, NMOSFET) and a resistor R4.
　トランジスタＮ４のドレインは、電源線Ｌ２に接続されている。トランジスタＮ４のゲートは、抵抗Ｒ４の第１端に接続されている。トランジスタＮ４のソース及びバックゲートと抵抗Ｒ４の第２端は、いずれも接地線Ｌ３に接続されている。なお、トランジスタＮ４のゲートをプルダウンするための抵抗Ｒ４は、省略され得る。このように接続されたトランジスタＮ４は、先出のトランジスタＮ２及びＮ３と同様、電源／接地間のＥＳＤ保護素子として機能する。 The drain of the transistor N4 is connected to the power supply line L2. The gate of transistor N4 is connected to the first end of resistor R4. The source and back gate of the transistor N4 and the second end of the resistor R4 are both connected to the ground line L3. Note that the resistor R4 for pulling down the gate of the transistor N4 may be omitted. Transistor N4 connected in this manner functions as an ESD protection element between the power supply and ground, like the transistors N2 and N3 described above.
　このように、第２比較例のＩ／Ｏ回路１０では、Ｉ／Ｏセル１１０の直近（又は近傍）にＮＣセル１４０が配置されている。 In this way, in the I/O circuit 10 of the second comparative example, the NC cell 140 is arranged immediately (or in the vicinity) of the I/O cell 110.
　例えば、信号端子Ｔ１に印加されるＥＳＤパルスを接地端子Ｔ３に逃がしてＥＳＤ保護を掛ける場合を考える。この場合、図示の細い矢印で示したように、信号端子Ｔ１から信号線Ｌ１、ダイオードＤ１、電源線Ｌ２、トランジスタＮ４及び接地線Ｌ３を介して接地端子Ｔ３に至る電流経路に電流が流れ得る。 For example, consider a case where ESD protection is applied by letting the ESD pulse applied to the signal terminal T1 escape to the ground terminal T3. In this case, as indicated by the thin arrow in the figure, a current may flow in a current path from the signal terminal T1 to the ground terminal T3 via the signal line L1, the diode D1, the power line L2, the transistor N4, and the ground line L3.
　従って、第２比較例のＩ／Ｏ回路１０であれば、信号端子Ｔ１と電源端子Ｔ２又は接地端子Ｔ３との距離が遠くても、配線インピーダンスの影響を小さく抑えることができる。その結果、Ｉ／Ｏセル１１０のＥＳＤ保護機能に支障を来し難くなる。 Therefore, with the I/O circuit 10 of the second comparative example, even if the distance between the signal terminal T1 and the power supply terminal T2 or the ground terminal T3 is long, the influence of wiring impedance can be suppressed to a small level. As a result, the ESD protection function of the I/O cell 110 is less likely to be impaired.
　ただし、端子間の距離は機種毎に異なるので、ＮＣセル１４０が配置される場所も機種毎に異なる。そのため、ＥＳＤパルスを逃がすための電流経路に多少の配線インピーダンスが付随することは避けられない。そのため、配線インピーダンスを考慮した保護素子サイズの設計及びセル配置が必要となる。 However, since the distance between the terminals differs depending on the model, the location where the NC cell 140 is arranged also differs depending on the model. Therefore, it is inevitable that some wiring impedance is attached to the current path for escaping the ESD pulse. Therefore, it is necessary to design the protection element size and arrange the cells in consideration of the wiring impedance.
　また、ＮＣセル１４０をＩ／Ｏセル１１０の直近（又は近傍）に配置することができない場合には、上記した電流経路の配線インピーダンスが増大し得る。その結果、Ｉ／Ｏセル１１０のＥＳＤ保護機能が成立しなくなるおそれがある。 Furthermore, if the NC cell 140 cannot be placed immediately (or in the vicinity) of the I/O cell 110, the wiring impedance of the above-described current path may increase. As a result, there is a possibility that the ESD protection function of the I/O cell 110 will not be achieved.
　また、半導体装置１の回路設計者がＮＣセル１４０を配置し忘れるおそれもある。 Additionally, there is a risk that the circuit designer of the semiconductor device 1 may forget to place the NC cell 140.
　図４は、第２比較例におけるＩ／Ｏ回路１０の平面レイアウトを示す図である。第２比較例におけるＩ／Ｏ回路１０では、Ｉ／Ｏセル１１０とＮＣセル１４０がそれぞれ独立した標準セルとして個別に配置される。本図に即して述べると、Ｉ／Ｏセル１１０とＮＣセル１４０は、半導体装置１の平面視において、紙面左右方向に並べて配置されている。 FIG. 4 is a diagram showing a planar layout of the I/O circuit 10 in the second comparative example. In the I/O circuit 10 in the second comparative example, the I/O cell 110 and the NC cell 140 are individually arranged as independent standard cells. Referring to the figure, the I/O cell 110 and the NC cell 140 are arranged side by side in the left-right direction in the drawing when the semiconductor device 1 is viewed from above.
　図５は、第２比較例におけるＩ／Ｏ回路１０の縦断面（＝図４のＸ１－Ｘ２断面）を示す図である。先にも述べたように、Ｉ／Ｏセル１１０とＮＣセル１４０は、それぞれ独立した標準セルである。 FIG. 5 is a diagram showing a vertical cross section (=X1-X2 cross section in FIG. 4) of the I/O circuit 10 in the second comparative example. As mentioned above, the I/O cell 110 and the NC cell 140 are each independent standard cells.
　そのため、Ｉ／Ｏセル１１０に含まれるダイオードＤ２（例えばゲート・ソース間がショートされたＮＭＯＳＦＥＴのボディダイオード）と、ＮＣセル１４０に含まれるトランジスタＮ４は、それぞれ、電位的に分離された個別のＰ型ウェル（ＰＷ）に形成される。すなわち、ダイオードＤ２（＝ゲート・ソース間がショートされたＮＭＯＳＦＥＴのボディダイオード）とトランジスタＮ４それぞれのバックゲートは、互いに分離されている。 Therefore, the diode D2 (for example, the body diode of an NMOSFET whose gate and source are shorted) included in the I/O cell 110 and the transistor N4 included in the NC cell 140 are each potential-separated individual PMOSFETs. It is formed in a type well (PW). That is, the diode D2 (=the body diode of the NMOSFET whose gate and source are shorted) and the back gates of the transistors N4 are separated from each other.
　従って、ダイオードＤ２とトランジスタＮ４との間を隔てる素子間距離が長くなり、Ｉ／Ｏ回路１０（延いては半導体装置１）の小面積化が阻害され得る。 Therefore, the distance between the elements separating the diode D2 and the transistor N4 becomes long, which may hinder the reduction in area of the I/O circuit 10 (and by extension, the semiconductor device 1).
　そこで、以下では、ＥＳＤ耐圧向上と小面積化を両立することのできる新規な実施形態を提案する。 Therefore, below, we will propose a new embodiment that can both improve the ESD withstand voltage and reduce the area.
＜Ｉ／Ｏ回路（実施形態）＞
　図６はＩ／Ｏ回路の新規な実施形態を示す図である。本実施形態のＩ／Ｏ回路１０は、Ｉ／Ｏセルライブラリ１００に含まれる複数種類の標準セルを組み合わせることにより形成されている。特に、本実施形態のＩ／Ｏ回路１０は、複数種類の標準セルとして、少なくともＩ／Ｏセル１５０を含む。なお、本図では明示されていないが、Ｉ／Ｏ回路１０では、先出のＶＣＣセル１２０及びＧＮＤセル１３０などが組み合わされていてもよい。 <I/O circuit (embodiment)>
FIG. 6 is a diagram illustrating a new embodiment of an I/O circuit. The I/O circuit 10 of this embodiment is formed by combining multiple types of standard cells included in the I/O cell library 100. In particular, the I/O circuit 10 of this embodiment includes at least an I/O cell 150 as a plurality of types of standard cells. Although not clearly shown in this figure, the I/O circuit 10 may include a combination of the previously mentioned VCC cell 120, GND cell 130, and the like.
　Ｉ／Ｏセル１５０は、第１素子形成領域１５１と、第２素子形成領域１５２と、第３素子形成領域１５３と、を含む。 The I/O cell 150 includes a first element formation region 151, a second element formation region 152, and a third element formation region 153.
　第１素子形成領域１５１は、信号線Ｌ１に接続される信号端子Ｔ１の直近（又は近傍）に配置されている。なお、第１素子形成領域１５１には、トランジスタＰ１１（例えばＰＭＯＳＦＥＴ）と、トランジスタＮ１１（例えばＮＭＯＳＦＥＴ）と、抵抗Ｒ１１が形成されている。 The first element formation region 151 is arranged immediately (or in the vicinity) of the signal terminal T1 connected to the signal line L1. Note that in the first element formation region 151, a transistor P11 (for example, PMOSFET), a transistor N11 (for example, NMOSFET), and a resistor R11 are formed.
　トランジスタＰ１１及びＮ１１それぞれのドレインは、いずれも信号線Ｌ１に接続されている。トランジスタＰ１１のソース、ゲート及びバックゲートは、いずれも電源線Ｌ２に接続されている。トランジスタＮ１１のゲートは、抵抗Ｒ１１の第１端に接続されている。トランジスタＮ１１のソース及びバックゲートと抵抗Ｒ１１の第２端は、いずれも接地線Ｌ３に接続されている。なお、トランジスタＮ１１のゲートをプルダウンするための抵抗Ｒ１１は、省略され得る。 The drains of transistors P11 and N11 are both connected to signal line L1. The source, gate, and back gate of the transistor P11 are all connected to the power supply line L2. The gate of transistor N11 is connected to the first end of resistor R11. The source and back gate of the transistor N11 and the second end of the resistor R11 are both connected to the ground line L3. Note that the resistor R11 for pulling down the gate of the transistor N11 may be omitted.
　このように、ゲート・ソース間がショートされたトランジスタＰ１１及びＮ１１は、それぞれ、信号線Ｌ１と電源線Ｌ２との間に接続される第１のＥＳＤ保護素子、及び、信号線Ｌ１と接地線Ｌ３との間に接続される第２のＥＳＤ保護素子として機能する。これら第１及び第２のＥＳＤ保護素子は、それぞれ、信号線Ｌ１に接続される被保護素子（本図では、後出のトランジスタＰ１２及びＮ１３）をＥＳＤパルスから保護する。なお、トランジスタＰ１１及びＮ１１は、それぞれ、第１比較例（図２）及び第２比較例（図３）に倣い、ダイオードに置き換えられてもよい。 In this way, the transistors P11 and N11 whose gates and sources are short-circuited are connected to the first ESD protection element connected between the signal line L1 and the power line L2, and the first ESD protection element connected between the signal line L1 and the ground line L3, respectively. It functions as a second ESD protection element connected between. These first and second ESD protection elements each protect protected elements (in this figure, transistors P12 and N13, which will be described later) connected to the signal line L1 from ESD pulses. Note that the transistors P11 and N11 may be replaced with diodes, respectively, as in the first comparative example (FIG. 2) and the second comparative example (FIG. 3).
　第２素子形成領域１５２は、第１素子形成領域１５１の直近（又は近傍）に配置されている。好ましくは、第２素子形成領域１５２が第１素子形成領域１５１に隣接して配置されるとよい。本図に即して述べると、第２素子形成領域１５２は、信号端子Ｔ１と第１素子形成領域１５１との間に配置されている。なお、第２素子形成領域１５２には、トランジスタＮ１２（例えばＮＭＯＳＦＥＴ）と、抵抗Ｒ１２が形成されている。 The second element formation region 152 is arranged immediately (or in the vicinity) of the first element formation region 151. Preferably, the second element formation region 152 is arranged adjacent to the first element formation region 151. Referring to this figure, the second element formation region 152 is arranged between the signal terminal T1 and the first element formation region 151. Note that a transistor N12 (for example, NMOSFET) and a resistor R12 are formed in the second element formation region 152.
　トランジスタＮ１２のドレインは、電源線Ｌ２に接続されている。トランジスタＮ１２のゲートは、抵抗Ｒ１２の第１端に接続されている。トランジスタＮ１２のソース及びバックゲートと抵抗Ｒ１２の第２端は、いずれも接地線Ｌ３に接続されている。なお、トランジスタＮ１２のゲートをプルダウンするための抵抗Ｒ１２は、省略され得る。 The drain of the transistor N12 is connected to the power supply line L2. The gate of transistor N12 is connected to the first end of resistor R12. The source and back gate of the transistor N12 and the second end of the resistor R12 are both connected to the ground line L3. Note that the resistor R12 for pulling down the gate of the transistor N12 may be omitted.
　このように、ゲート・ソース間がショートされたトランジスタＮ１２は、電源線Ｌ２と接地線Ｌ３との接続される第３のＥＳＤ保護素子として機能する。なお、トランジスタＮ１２は、ダイオードに置き換えられてもよい。 In this way, the transistor N12 whose gate and source are short-circuited functions as a third ESD protection element connected to the power supply line L2 and the ground line L3. Note that the transistor N12 may be replaced with a diode.
　第３素子形成領域１５３は、例えば、第１素子形成領域１５１及び第２素子形成領域１５２よりも半導体装置１の内部寄り（＝コア側）に配置されている。本図に即して述べると、半導体装置１の平面視において、信号端子Ｔ１に近い側から順に、第２素子形成領域１５２、第１素子形成領域１５１及び第３素子形成領域１５３が配置されている。なお、第３素子形成領域１５３には、トランジスタＰ１２（例えばＰＭＯＳＦＥＴ）と、トランジスタＮ１３（例えばＮＭＯＳＦＥＴ）が形成されている。 The third element formation region 153 is, for example, arranged closer to the inside (=core side) of the semiconductor device 1 than the first element formation region 151 and the second element formation region 152. Referring to this figure, in a plan view of the semiconductor device 1, the second element formation region 152, the first element formation region 151, and the third element formation region 153 are arranged in order from the side closer to the signal terminal T1. There is. Note that a transistor P12 (for example, PMOSFET) and a transistor N13 (for example, NMOSFET) are formed in the third element formation region 153.
　トランジスタＰ１２のソース及びバックゲートは、いずれも電源線Ｌ２に接続されている。トランジスタＮ１３のソース及びバックゲートは、いずれも接地線Ｌ３に接続されている。トランジスタＰ１２及びＮ１３それぞれのドレインは、いずれも不図示の内部回路に接続されている。トランジスタＰ１２及びＮ１３それぞれのゲートは、いずれも信号線Ｌ１を介して信号端子Ｔ１に接続されている。このように接続されたトランジスタＰ１２及びＮ１３は、ＣＭＯＳインバータ（いわゆる入力バッファ）を形成する。なお、第３素子形成領域１５３には、入力バッファに代えて出力バッファ又は入出力バッファが形成されてもよい。 The source and back gate of the transistor P12 are both connected to the power supply line L2. The source and back gate of transistor N13 are both connected to ground line L3. The drains of transistors P12 and N13 are both connected to an internal circuit (not shown). The gates of transistors P12 and N13 are both connected to signal terminal T1 via signal line L1. Transistors P12 and N13 connected in this way form a CMOS inverter (so-called input buffer). Note that an output buffer or an input/output buffer may be formed in the third element formation region 153 instead of the input buffer.
　例えば、信号端子Ｔ１に印加されるＥＳＤパルスを接地端子Ｔ３に逃がしてＥＳＤ保護を掛ける場合を考える。この場合、図示の細い矢印で示したように、信号端子Ｔ１から信号線Ｌ１、トランジスタＰ１１、電源線Ｌ２、トランジスタＮ１２及び接地線Ｌ３を介して接地端子Ｔ３に至る電流経路に電流が流れ得る。 For example, consider a case where ESD protection is applied by letting the ESD pulse applied to the signal terminal T1 escape to the ground terminal T3. In this case, as indicated by the thin arrow in the figure, a current may flow in a current path from the signal terminal T1 to the ground terminal T3 via the signal line L1, the transistor P11, the power supply line L2, the transistor N12, and the ground line L3.
　従って、本実施形態のＩ／Ｏ回路１０であれば、信号端子Ｔ１と電源端子Ｔ２又は接地端子Ｔ３との距離が遠くても、配線インピーダンスの影響を小さく抑えることができる。 Therefore, with the I/O circuit 10 of this embodiment, even if the distance between the signal terminal T1 and the power supply terminal T2 or the ground terminal T3 is long, the influence of wiring impedance can be suppressed.
　また、Ｉ／Ｏセル１５０は、第２比較例（図３）のＩ／Ｏセル１１０及びＮＣセル１４０を一つの標準セルに集約したものとして理解され得る。従って、配線インピーダンスを考慮した保護素子サイズの設計及びセル配置が不要となる。また、半導体装置１の回路設計者がＮＣセル１４０を配置し忘れてＥＳＤ保護機能が不成立となる心配もなくなる。 Further, the I/O cell 150 can be understood as a combination of the I/O cell 110 and the NC cell 140 of the second comparative example (FIG. 3) into one standard cell. Therefore, it is not necessary to design the protection element size and arrange the cells in consideration of the wiring impedance. Furthermore, there is no need to worry about the ESD protection function failing due to the circuit designer of the semiconductor device 1 forgetting to place the NC cell 140.
　図７は、本実施形態におけるＩ／Ｏ回路１０の平面レイアウトを示す図である。本図で示したように、トランジスタＰ１１、Ｎ１１及びＮ１２（それぞれ第１～第３のＥＳＤ保護素子に相当）は、それぞれ、単一のＩ／Ｏセル１５０を形成する構成要素の一つとして配置される。 FIG. 7 is a diagram showing a planar layout of the I/O circuit 10 in this embodiment. As shown in this figure, transistors P11, N11, and N12 (corresponding to the first to third ESD protection elements) are each arranged as one of the components forming a single I/O cell 150. be done.
　特に、先出の第２比較例（図４）と対比すると、トランジスタＮ１１（＝第２のＥＳＤ保護素子）とトランジスタＮ１２（＝第３のＥＳＤ保護素子）とを隔てる素子分離領域が存在しないことが分かる。 In particular, in comparison with the second comparative example (FIG. 4) mentioned above, there is no element isolation region separating transistor N11 (=second ESD protection element) and transistor N12 (=third ESD protection element). I understand.
　図８は、本実施形態におけるＩ／Ｏ回路１０の縦断面（＝図７のＹ１－Ｙ２断面）を示す図である。先にも述べたように、Ｉ／Ｏセル１５０は、第２比較例（図３）のＩ／Ｏセル１１０及びＮＣセル１４０を一つの標準セルに集約したものとして理解され得る。 FIG. 8 is a diagram showing a vertical cross section (=Y1-Y2 cross section in FIG. 7) of the I/O circuit 10 in this embodiment. As mentioned above, the I/O cell 150 can be understood as a combination of the I/O cell 110 and the NC cell 140 of the second comparative example (FIG. 3) into one standard cell.
　そのため、トランジスタＮ１１（＝第２のＥＳＤ保護素子）とトランジスタＮ１２（＝第３のＥＳＤ保護素子）は、それぞれ、共通のＰ型ウェル（ＰＷ）に形成される。すなわち、トランジスタＮ１１及びＮ１２それぞれのバックゲートは、共通化されている。 Therefore, the transistor N11 (=second ESD protection element) and the transistor N12 (=third ESD protection element) are each formed in a common P-type well (PW). That is, the back gates of transistors N11 and N12 are shared.
　従って、トランジスタＮ１１とトランジスタＮ１２との間を隔てる素子間距離が短くなるので、Ｉ／Ｏ回路１０（延いては半導体装置１）の小面積化を実現することができる。 Therefore, since the inter-element distance separating the transistor N11 and the transistor N12 is shortened, the area of the I/O circuit 10 (and thus the semiconductor device 1) can be reduced.
　なお、Ｉ／Ｏセル１５０は、第１比較例（図２）及び第２比較例（図３）のＩ／Ｏセル１１０と比べて、トランジスタＮ１２（＝第３のＥＳＤ保護素子）を含む分だけ面積が大きくなる。ただし、このような面積の増大を考慮しても、Ｉ／Ｏセル１５０は、信号端子Ｔ１に接続されるパッドと同程度のサイズに収まる。従って、Ｉ／Ｏセル１５０は、上記パッドの直下領域に配置されるとよい。このようなレイアウトによれば、Ｉ／Ｏセル１５０の面積が増大してもインパクトは小さくなる。 Note that the I/O cell 150 is different from the I/O cell 110 of the first comparative example (FIG. 2) and the second comparative example (FIG. 3) in that it includes the transistor N12 (=third ESD protection element). area becomes larger. However, even in consideration of such an increase in area, the I/O cell 150 is still approximately the same size as the pad connected to the signal terminal T1. Therefore, the I/O cell 150 is preferably placed directly under the pad. According to such a layout, even if the area of the I/O cell 150 increases, the impact is small.
＜総括＞
　以下では、上記で説明した種々の実施形態について総括的に述べる。 <Summary>
Below, the various embodiments described above will be described in general.
　例えば、本明細書中に開示されているＩ／Ｏ回路は、セルライブラリに含まれる複数種類の標準セルを任意に組み合わせることにより形成されるものであって、前記複数種類の標準セルに含まれるＩ／Ｏセルは、信号線と電源線との間に接続される第１保護素子及び前記信号線と接地線との間に接続される第２保護素子が形成されるように構成された第１素子形成領域と、前記電源線と前記接地線との間に接続される第３保護素子が形成されるように構成された第２素子形成領域と、を含み、前記第２保護素子及び第３保護素子は、いずれも共通のウェルに形成されている構成（第１の構成）とされている。 For example, the I/O circuit disclosed in this specification is formed by arbitrarily combining multiple types of standard cells included in a cell library, and the I/O circuit included in the multiple types of standard cells is The I/O cell includes a first protection element connected between a signal line and a power line, and a second protection element connected between the signal line and a ground line. a second element formation area configured such that a third protection element connected between the power supply line and the ground line is formed; The three protection elements are all formed in a common well (first configuration).
　上記第１の構成によるＩ／Ｏ回路は、前記信号線に接続される被保護素子が形成されるように構成された第３素子形成領域をさらに含む構成（第２の構成）にしてもよい。 The I/O circuit according to the first configuration may have a configuration (second configuration) further including a third element formation region configured to form a protected element connected to the signal line. .
　上記第２の構成によるＩ／Ｏ回路において、前記被保護素子は、入力バッファ、出力バッファ又は入出力バッファを形成する構成（第３の構成）にしてもよい。 In the I/O circuit according to the second configuration, the protected element may be configured to form an input buffer, an output buffer, or an input/output buffer (third configuration).
　上記第１～第３いずれかの構成によるＩ／Ｏ回路において、前記第１保護素子は、Ｐチャネル型の第１トランジスタであり、前記第１トランジスタのソース、ゲート及びバックゲートがいずれも前記電源線に接続されており、前記第１トランジスタのドレインが前記信号線に接続されている構成（第４の構成）にしてもよい。 In the I/O circuit according to any one of the first to third configurations, the first protection element is a P-channel type first transistor, and the source, gate, and back gate of the first transistor are all connected to the power source. A configuration (fourth configuration) may be adopted in which the drain of the first transistor is connected to the signal line and the drain of the first transistor is connected to the signal line.
　上記第１～第４いずれかの構成によるＩ／Ｏ回路において、前記第２保護素子は、Ｎチャネル型の第２トランジスタであり、前記第２トランジスタのソース、ゲート及びバックゲートがいずれも直接的又は間接的に前記接地線に接続されており、前記第２トランジスタのドレインが前記信号線に接続されている構成（第５の構成）にしてもよい。 In the I/O circuit according to any one of the first to fourth configurations, the second protection element is an N-channel type second transistor, and the source, gate, and back gate of the second transistor are all directly connected to each other. Alternatively, it may be indirectly connected to the ground line, and the drain of the second transistor may be connected to the signal line (fifth configuration).
　上記第１～第５いずれかの構成によるＩ／Ｏ回路において、前記第３保護素子は、Ｎチャネル型の第３トランジスタであり、前記第３トランジスタのソース、ゲート及びバックゲートがいずれも直接的又は間接的に前記接地線に接続されており、前記第３トランジスタのドレインが前記電源線に接続されている構成（第６の構成）にしてもよい。 In the I/O circuit according to any one of the first to fifth configurations, the third protection element is an N-channel type third transistor, and the source, gate, and back gate of the third transistor are all directly connected to each other. Alternatively, the third transistor may be indirectly connected to the ground line, and the drain of the third transistor may be connected to the power supply line (sixth configuration).
　また、例えば、本明細書中に開示されている半導体装置は、上記第１～第６いずれかの構成によるＩ／Ｏ回路と、前記信号線に接続されるように構成された外部端子と、を備える構成（第７の構成）とされている。 Further, for example, the semiconductor device disclosed in this specification includes an I/O circuit having any one of the first to sixth configurations, an external terminal configured to be connected to the signal line, (seventh configuration).
　上記第７の構成による半導体装置において、前記Ｉ／Ｏセルは、前記外部端子に接続されるパッドの直下領域に配置される構成（第８の構成）にしてもよい。 In the semiconductor device according to the seventh configuration, the I/O cell may be arranged in a region immediately below a pad connected to the external terminal (eighth configuration).
　また、例えば、本明細書中に開示されているセルライブラリは、コンピュータで実行される回路設計プログラムから読み出されて半導体装置のＩ／Ｏ回路を形成するために任意に組み合わせることのできる複数種類の標準セルを含むものであって、前記複数種類の標準セルに含まれるＩ／Ｏセルは、信号線と電源線との間に接続される第１保護素子及び前記信号線と接地線との間に接続される第２保護素子が形成されるように構成された第１素子形成領域と、前記電源線と前記接地線との間に接続される第３保護素子が形成されるように構成された第２素子形成領域と、を含み、前記第２保護素子及び第３保護素子は、いずれも共通のウェルに形成されている構成（第９の構成）とされている。 Furthermore, for example, the cell library disclosed herein includes multiple types that can be read out from a circuit design program executed by a computer and arbitrarily combined to form an I/O circuit of a semiconductor device. The I/O cells included in the plurality of types of standard cells include a first protection element connected between a signal line and a power line and a first protection element connected between the signal line and a ground line. a first element formation region configured such that a second protection element connected therebetween is formed; and a third protection element connected between the power supply line and the ground line The second protective element and the third protective element are both formed in a common well (a ninth configuration).
　また、例えば、本明細書中に開示されている半導体装置の回路設計方法は、上記第９のセルライブラリを用いるものであって、前記セルライブラリに含まれる前記複数種類の標準セルを選択及び配置して任意に組み合わせるステップと、任意に組み合わされた前記複数種類の標準セルとその他の回路ブロックとを接続するように前記電源線、前記接地線及び前記信号線を敷設するステップと、を備える構成（第１０の構成）とされている。 Further, for example, the method for designing a circuit for a semiconductor device disclosed in this specification uses the ninth cell library, and includes selecting and arranging the plurality of types of standard cells included in the cell library. and a step of laying the power supply line, the ground line, and the signal line so as to connect the arbitrarily combined plurality of types of standard cells and other circuit blocks. (10th configuration).
＜その他の変形例＞
　なお、本明細書中に開示されている種々の技術的特徴は、上記実施形態のほか、その技術的創作の主旨を逸脱しない範囲で種々の変更を加えることが可能である。すなわち、上記実施形態は、全ての点で例示であって制限的なものではないと考えられるべきであり、本開示の技術的範囲は、特許請求の範囲により規定されるものであって、特許請求の範囲と均等の意味及び範囲内に属する全ての変更が含まれると理解されるべきである。 <Other variations>
Note that the various technical features disclosed in this specification can be modified in addition to the above-described embodiments without departing from the gist of the technical creation. In other words, the above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present disclosure is defined by the claims, and the technical scope of the present disclosure is defined by the claims. It should be understood that all changes that come within the meaning and range of equivalence of the claims are included.
　　　１　　半導体装置
　　　１０　　Ｉ／Ｏ回路
　　　１００　　セルライブラリ
　　　１１０　　Ｉ／Ｏセル
　　　１２０　　ＶＣＣセル
　　　１３０　　ＧＮＤセル
　　　１４０　　ＮＣセル
　　　１５０　　Ｉ／Ｏセル
　　　１５１　　第１素子形成領域
　　　１５２　　第２素子形成領域
　　　１５３　　第３素子形成領域
　　　ＡＤＣ　　アナログ／デジタル変換器
　　　ＡＮＡＬＯＧ　　アナログ回路
　　　Ｄ１、Ｄ２　　ダイオード
　　　ＤＡＣ　　デジタル／アナログ変換器
　　　Ｉ／Ｆ　　インタフェイス回路
　　　Ｌ１　　信号線
　　　Ｌ２　　電源線
　　　Ｌ３　　接地線
　　　ＬＤＯ　　レギュレータ
　　　ＬＯＧＩＣ　　ロジック回路
　　　Ｎ１～Ｎ４、Ｎ１１～Ｎ１３　　トランジスタ（ＮＭＯＳＦＥＴ）
　　　ＮＶＭ　　不揮発性メモリ
　　　Ｐ１、Ｐ１１、Ｐ１２　　トランジスタ（ＰＭＯＳＦＥＴ）
　　　Ｒ２～Ｒ４、Ｒ１１、Ｒ１２　　抵抗
　　　ＳＲＡＭ　　揮発性メモリ
　　　Ｔ１　　信号端子
　　　Ｔ２　　電源端子
　　　Ｔ３　　接地端子 1 Semiconductor device 10 I/O circuit 100 Cell library 110 I/O cell 120 VCC cell 130 GND cell 140 NC cell 150 I/O cell 151 First element formation area 152 Second element formation area 153 Third element formation area ADC Analog /Digital converter ANALOG Analog circuit D1, D2 Diode DAC Digital/analog converter I/F Interface circuit L1 Signal line L2 Power line L3 Ground line LDO Regulator LOGIC Logic circuit N1 to N4, N11 to N13 Transistor (NMOSFET)
NVM Non-volatile memory P1, P11, P12 Transistor (PMOSFET)
R2~R4, R11, R12 Resistor SRAM Volatile memory T1 Signal terminal T2 Power supply terminal T3 Ground terminal

Claims (10)

  1. 　セルライブラリに含まれる複数種類の標準セルを任意に組み合わせることにより形成されたＩ／Ｏ回路であって、
    　前記複数種類の標準セルに含まれるＩ／Ｏセルは、
    　信号線と電源線との間に接続される第１保護素子及び前記信号線と接地線との間に接続される第２保護素子が形成されるように構成された第１素子形成領域と、
    　前記電源線と前記接地線との間に接続される第３保護素子が形成されるように構成された第２素子形成領域と、
    　を含み、
    　前記第２保護素子及び前記第３保護素子は、いずれも共通のウェルに形成されている、Ｉ／Ｏ回路。     An I/O circuit formed by arbitrarily combining multiple types of standard cells included in a cell library,
    The I/O cells included in the plurality of types of standard cells are:
    a first element formation region configured to form a first protection element connected between the signal line and the power line and a second protection element connected between the signal line and the ground line;
    a second element formation region configured to form a third protection element connected between the power supply line and the ground line;
    including;
    The second protection element and the third protection element are both formed in a common well.
  2. 　前記信号線に接続される被保護素子が形成されるように構成された第３素子形成領域をさらに含む、請求項１に記載のＩ／Ｏ回路。 The I/O circuit according to claim 1, further comprising a third element formation region configured such that a protected element connected to the signal line is formed.
  3. 　前記被保護素子は、入力バッファ、出力バッファ又は入出力バッファを形成する、請求項２に記載のＩ／Ｏ回路。 The I/O circuit according to claim 2, wherein the protected element forms an input buffer, an output buffer, or an input/output buffer.
  4. 　前記第１保護素子は、Ｐチャネル型の第１トランジスタであり、前記第１トランジスタのソース、ゲート及びバックゲートがいずれも前記電源線に接続されており、前記第１トランジスタのドレインが前記信号線に接続されている、請求項１～３のいずれか一項に記載のＩ／Ｏ回路。 The first protection element is a P-channel type first transistor, the source, gate, and back gate of the first transistor are all connected to the power supply line, and the drain of the first transistor is connected to the signal line. The I/O circuit according to any one of claims 1 to 3, which is connected to the I/O circuit.
  5. 　前記第２保護素子は、Ｎチャネル型の第２トランジスタであり、前記第２トランジスタのソース、ゲート及びバックゲートがいずれも直接的又は間接的に前記接地線に接続されており、前記第２トランジスタのドレインが前記信号線に接続されている、請求項１～４のいずれか一項に記載のＩ／Ｏ回路。 The second protection element is an N-channel type second transistor, and the source, gate, and back gate of the second transistor are all directly or indirectly connected to the ground line, and the second transistor 5. The I/O circuit according to claim 1, wherein a drain of the I/O circuit is connected to the signal line.
  6. 　前記第３保護素子は、Ｎチャネル型の第３トランジスタであり、前記第３トランジスタのソース、ゲート及びバックゲートがいずれも直接的又は間接的に前記接地線に接続されており、前記第３トランジスタのドレインが前記電源線に接続されている、請求項１～５のいずれか一項に記載のＩ／Ｏ回路。 The third protection element is an N-channel type third transistor, and the source, gate, and back gate of the third transistor are all directly or indirectly connected to the ground line, and the third transistor The I/O circuit according to claim 1, wherein a drain of the I/O circuit is connected to the power supply line.
  7. 　請求項１～６のいずれか一項に記載のＩ／Ｏ回路と、
    　前記信号線に接続されるように構成された外部端子と、
    　を備える、半導体装置。     The I/O circuit according to any one of claims 1 to 6,
    an external terminal configured to be connected to the signal line;
    A semiconductor device comprising:
  8. 　前記Ｉ／Ｏセルは、前記外部端子に接続されるパッドの直下領域に配置される、請求項７に記載の半導体装置。 8. The semiconductor device according to claim 7, wherein the I/O cell is arranged in a region directly below a pad connected to the external terminal.
  9. 　コンピュータで実行される回路設計プログラムから読み出されて半導体装置のＩ／Ｏ回路を形成するために任意に組み合わせることのできる複数種類の標準セルを含むセルライブラリであって、
    　前記複数種類の標準セルに含まれるＩ／Ｏセルは、
    　信号線と電源線との間に接続される第１保護素子及び前記信号線と接地線との間に接続される第２保護素子が形成されるように構成された第１素子形成領域と、
    　前記電源線と前記接地線との間に接続される第３保護素子が形成されるように構成された第２素子形成領域と、
    　を含み、
    　前記第２保護素子及び前記第３保護素子は、いずれも共通のウェルに形成されている、セルライブラリ。     A cell library including a plurality of types of standard cells that can be read from a circuit design program executed by a computer and arbitrarily combined to form an I/O circuit of a semiconductor device,
    The I/O cells included in the plurality of types of standard cells are:
    a first element formation region configured to form a first protection element connected between the signal line and the power line and a second protection element connected between the signal line and the ground line;
    a second element formation region configured to form a third protection element connected between the power supply line and the ground line;
    including;
    The second protection element and the third protection element are both formed in a common well.
  10. 　請求項９のセルライブラリを用いた半導体装置の回路設計方法であって、
    　前記セルライブラリに含まれる前記複数種類の標準セルを選択及び配置して任意に組み合わせるステップと、
    　任意に組み合わされた前記複数種類の標準セルとその他の回路ブロックとを接続するように前記電源線、前記接地線及び前記信号線を敷設するステップと、
    　を備える、半導体装置の回路設計方法。     A circuit design method for a semiconductor device using the cell library according to claim 9,
    selecting and arranging the plurality of types of standard cells included in the cell library and combining them arbitrarily;
    laying the power supply line, the ground line, and the signal line so as to connect the plurality of types of standard cells arbitrarily combined with other circuit blocks;
    A circuit design method for a semiconductor device, comprising:
PCT/JP2023/028414 2022-09-14 2023-08-03 I/o circuit, semiconductor device, cell library, and method for designing circuit of semiconductor device WO2024057763A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251453A (en) * 1998-12-28 1999-09-17 Seiko Epson Corp Semiconductor integrate device
JP2002050698A (en) * 2000-08-02 2002-02-15 Nec Corp Semiconductor device
JP2009164195A (en) * 2007-12-28 2009-07-23 Panasonic Corp Semiconductor chip
JP2009206402A (en) * 2008-02-29 2009-09-10 Fujitsu Microelectronics Ltd Method for designing semiconductor device, and semiconductor device
JP2010080622A (en) * 2008-09-25 2010-04-08 Panasonic Corp Semiconductor integrated circuit
JP2022105405A (en) * 2021-01-04 2022-07-14 ローム株式会社 Protection circuit and semiconductor integrated circuit having protection circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251453A (en) * 1998-12-28 1999-09-17 Seiko Epson Corp Semiconductor integrate device
JP2002050698A (en) * 2000-08-02 2002-02-15 Nec Corp Semiconductor device
JP2009164195A (en) * 2007-12-28 2009-07-23 Panasonic Corp Semiconductor chip
JP2009206402A (en) * 2008-02-29 2009-09-10 Fujitsu Microelectronics Ltd Method for designing semiconductor device, and semiconductor device
JP2010080622A (en) * 2008-09-25 2010-04-08 Panasonic Corp Semiconductor integrated circuit
JP2022105405A (en) * 2021-01-04 2022-07-14 ローム株式会社 Protection circuit and semiconductor integrated circuit having protection circuit

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