CN217543321U

CN217543321U - Chip version identification circuit and chip

Info

Publication number: CN217543321U
Application number: CN202221058887.6U
Authority: CN
Inventors: 陈明瑜; 陈永烈; 茹金泉; 陈明娇
Original assignee: Zhuhai Hongxin Technology Co ltd
Current assignee: Zhuhai Hongxin Technology Co ltd
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2022-10-04
Anticipated expiration: 2032-04-29

Abstract

The utility model provides a chip version identification circuit and a chip, wherein the chip version identification circuit comprises a plurality of version number circuits outputting high level or low level; each version number circuit comprises a tieh unit for sending high level, a tiel unit for sending low level and an inverter, and the output end of the tieh unit or the output end of the tiel unit is electrically connected with the input end of the inverter. The chip applies the chip version identification circuit. The utility model discloses a chip version identification circuit can be convenient for discern the chip version.

Description

Chip version identification circuit and chip

Technical Field

The utility model relates to a chip circuit technical field, it is concrete to relate to a chip version identification circuit, still relates to the chip of this chip version identification circuit.

Background

At present, after one chip is subjected to stream slicing, along with the increasing requirements of practical application, the chip can be subjected to version change and upgrading, and in the practical application, due to the existence of new and old products, if the version of the chip cannot be known, great troubles can be caused to the use, the maintenance and the use of the practical application.

In order to identify chips of different versions, a special pattern is arranged on the outer surface of the chip for identification in the conventional method, but the mode of arranging the pattern is inconvenient in modification and affects the attractiveness because the chip is packaged once after being modified every time.

Therefore, new designs that identify new and old versions of a chip need to be considered.

Disclosure of Invention

A first object of the present invention is to provide a chip version identification circuit capable of easily identifying a chip version.

A second object of the present invention is to provide a chip with easy identification of the version of the chip.

In order to achieve the first object, the present invention provides a chip version identification circuit, which comprises a plurality of version number circuits outputting high level or low level; each version number circuit comprises a tieh unit for sending high level, a tiel unit for sending low level and an inverter, and the output end of the tieh unit or the output end of the tiel unit is electrically connected with the input end of the inverter.

It is thus clear that by the above-mentioned scheme, the utility model discloses a chip version identification circuit can select output high level or low level according to the version of difference through the version number circuit that sets up a plurality of output high levels or low level, makes up the level of the output of a plurality of version number circuits, forms chip version number to discern. Meanwhile, the tieh unit and the tiel unit are adopted, a high level or a low level can be output according to needs to select the tieh unit or the tiel unit to be connected with the phase inverter, and the tieh unit and the tiel unit can further play a role in electrostatic protection, so that the safety of the circuit is guaranteed. The inverter is provided to output the levels output by the tieh unit and the tiel unit through the inverter, so that the line can be easily replaced when the version number is replaced.

In a further scheme, the tieh unit comprises a first PMOS tube and a first NMOS tube, wherein a source electrode of the first PMOS tube is electrically connected with a power supply end, a grid electrode of the first PMOS tube is electrically connected with a grid electrode of the first NMOS tube, a drain electrode of the first PMOS tube is electrically connected with an output end of the tieh unit, a drain electrode of the first NMOS tube is electrically connected with a grid electrode of the first NMOS tube, and a source electrode of the first NMOS tube is grounded.

In a further scheme, the tie unit comprises a second PMOS tube and a second NMOS tube, a source electrode of the second PMOS tube is electrically connected with a power supply end, a grid electrode of the second PMOS tube is electrically connected with a grid electrode of the second NMOS tube, a drain electrode of the second PMOS tube is electrically connected with the grid electrode of the second PMOS tube, a drain electrode of the second NMOS tube is electrically connected with an output end of the tie unit, and a source electrode of the second NMOS tube is grounded.

Therefore, the tieh unit can output stable level by arranging the first PMOS tube and the first NMOS tube, and the tiel unit can output stable level by arranging the second PMOS tube and the second NMOS tube, so that the accuracy of the version number is ensured.

In a further aspect, the number of version number circuits is eight.

Therefore, the eight version number circuits are arranged, and the requirement for updating the version number of the chip can be met.

In order to achieve the second object, the chip provided by the present invention comprises a substrate, wherein a chip version identification circuit and an output pin are arranged on the substrate, the chip version identification circuit comprises a plurality of version number circuits outputting high level or low level, the number of the output pin is equal to the number of the version number circuits, and the output end of each version number circuit is electrically connected with an output pin; each version number circuit comprises a tieh unit for sending high level, a tiel unit for sending low level and an inverter, wherein the output end of the tieh unit or the output end of the tiel unit is electrically connected with the input end of the inverter through a metal lead, and the output end of the inverter is electrically connected with a corresponding output pin; the tieh unit, the tiel unit and the inverter are all located on the same circuit layer of the substrate.

It is thus clear that by the above-mentioned scheme, the utility model discloses a chip version identification circuit can select output high level or low level according to the version of difference through the version number circuit that sets up a plurality of output high levels or low level, makes up the level of the output of a plurality of version number circuits, forms chip version number to discern. By adopting the tieh unit and the tiel unit, a high level or a low level can be output according to requirements to select the tieh unit or the tiel unit to be connected with the inverter, and the tieh unit and the tiel unit can further play a role in electrostatic protection, so that the safety of the circuit is guaranteed. Moreover, the inverter is arranged, so that the levels output by the tieh unit and the tiel unit are output through the inverter, and the tieh unit, the tiel unit and the inverter are all positioned on the same circuit layer of the substrate, so that when the connection relation of the tieh unit, the tiel unit and the inverter is required to be replaced for version number replacement, only the lead of a metal layer needs to be replaced, inconvenience of multilayer modification is reduced, and line replacement is facilitated.

In a further scheme, a plurality of version number circuits are sequentially arranged on the substrate.

Therefore, the multiple version number circuits are sequentially arranged on the substrate, so that the output arrangement of the version numbers can be facilitated, and the circuits can be conveniently modified.

In a further aspect, the number of version number circuits is eight.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of the chip of the present invention.

Fig. 2 is a schematic block diagram of a chip version identification circuit according to an embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of the structure of the embodiment of the present invention in which the tieh unit is electrically connected to the phase inverter at the chip version identification circuit.

Fig. 4 is a schematic circuit diagram of a chip version identification circuit according to an embodiment of the present invention.

The present invention will be further explained with reference to the drawings and examples.

Detailed Description

As shown in fig. 1, in this embodiment, the chip includes a substrate 1, a chip version identification circuit 2 and an output pin 3 are disposed on the substrate 1, the chip version identification circuit 2 includes a plurality of version number circuits 21 outputting a high level or a low level, and the plurality of version number circuits 21 are sequentially arranged on the substrate 1. The number of the output pins 3 is equal to the number of the version number circuits 21, and the output end of each version number circuit 21 is correspondingly electrically connected with one output pin 3, in this embodiment, the number of the version number circuits 21 is eight.

Referring to fig. 2, each version number circuit 21 includes a tieh cell 211 transmitting a high level and a tiel cell 212 transmitting a low level, and an inverter 213, an output terminal of the tieh cell 211 or an output terminal of the tiel cell 212 is electrically connected to an input terminal of the inverter 213 through a metal wire 214, and an output terminal of the inverter 213 is electrically connected to a corresponding output pin 3. Because there are many devices in the chip and it is not easy to search for a single device, setting the tieh unit 211 and the tiel unit 212 at the same time can increase the layout occupied area of the version number circuit 21 for searching. In addition, in order to facilitate the switching of the metal wiring 214 when the tieh cell 211 and the tiel cell 212 are switched as the output cells, in the present embodiment, referring to fig. 3, the tieh cell 211, the tiel cell 212, and the inverter 213 are all located at the same circuit layer of the substrate 1. Since a plurality of output pins 3 may be connected to different metal layers in the substrate, if the inverter 213 is not provided as an intermediate device for connecting the tieh cell 211 and the tiel cell 212 to the output pins 3, when modifying the outputs of the tieh cell 211 and the tiel cell 212, it may be necessary to exaggerate the multilayer metal layer connection, which is cumbersome and inconvenient to operate, and therefore, the inverter 213 is provided and the inverter 213, the tieh cell 211, and the tiel cell 212 are provided on the same circuit layer of the substrate 1, which may reduce the operation of crossing the multilayer connection.

Referring to fig. 4, in the present embodiment, the tieh unit 211 includes a first PMOS transistor P1 and a first NMOS transistor N1, a source of the first PMOS transistor P1 is electrically connected to the power supply terminal VDD, a gate of the first PMOS transistor P1 is electrically connected to a gate of the first NMOS transistor N1, a drain of the first PMOS transistor P1 is electrically connected to an output terminal of the tieh unit 211, a drain of the first NMOS transistor N1 is electrically connected to the gate of the first NMOS transistor N1, the source of the first NMOS transistor N1 is grounded, and the output terminal of the tieh unit 211 is electrically connected to an input terminal of the inverter 213 through a metal lead 214. the tiel unit 212 comprises a second PMOS tube P2 and a second NMOS tube N2, wherein a source electrode of the second PMOS tube P2 is electrically connected with a power supply end VDD, a grid electrode of the second PMOS tube P2 is electrically connected with a grid electrode of the second NMOS tube N2, a drain electrode of the second PMOS tube P2 is electrically connected with the grid electrode of the second PMOS tube P2, a drain electrode of the second NMOS tube N2 is electrically connected with an output end of the tiel unit 212, a source electrode of the second NMOS tube N2 is grounded, and an output end of the tiel unit 212 is electrically connected with an input end of the phase inverter 213 through a metal lead 214.

In the present embodiment, in order to correspond to the high level or the low level output by the version number circuit 21, binary version numbers are used, for example, the version number of the version a is "00000000", the version number of the version B is "00000001", the high level corresponds to the number "1", and the low level corresponds to the number "0". Electrically connecting the tieh unit 211 or the tiel unit 212 in the corresponding version number circuit 21 with the input end of the inverter 213 according to the version number, so that the version number circuit 21 can output a corresponding high level or low level, for example, when the low level needs to be output, the tieh unit 211 in the version number circuit 21 is electrically connected with the input end of the inverter 213, and the tiel unit 212 is disconnected with the input end of the inverter 213; when a high level needs to be output, the tieh unit 211 in the version number circuit 21 is disconnected from the input of the inverter 213, and the tiel unit 212 is electrically connected to the input of the inverter 213. Modifying the operation of the metal wire 214 between the tieh cell 211 or the tiel cell 212 and the input of the inverter 213 is well known to those skilled in the art and will not be described herein. When the version number of the chip needs to be checked, the output levels of all the output pins 3 are read by an external reading device, so that the read levels are sequentially combined into the version number of the chip.

It should be noted that the above is only a preferred embodiment of the present invention, but the design concept of the present invention is not limited thereto, and all insubstantial modifications made by using the design concept of the present invention also fall within the protection scope of the present invention.

Claims

1. A chip version identification circuit, characterized by: the circuit comprises a plurality of version number circuits for outputting high level or low level;

each version number circuit comprises a tieh unit for sending high level, a tiel unit for sending low level and an inverter, and the output end of the tieh unit or the output end of the tiel unit is electrically connected with the input end of the inverter.

2. The chip version identification circuit of claim 1, wherein:

the tieh unit comprises a first PMOS tube and a first NMOS tube, wherein a source electrode of the first PMOS tube is electrically connected with a power supply end, a grid electrode of the first PMOS tube is electrically connected with a grid electrode of the first NMOS tube, a drain electrode of the first PMOS tube is electrically connected with an output end of the tieh unit, a drain electrode of the first NMOS tube is electrically connected with a grid electrode of the first NMOS tube, and a source electrode of the first NMOS tube is grounded.

3. The chip version identification circuit of claim 2, wherein:

the tie unit comprises a second PMOS tube and a second NMOS tube, wherein a source electrode of the second PMOS tube is electrically connected with the power supply end, a grid electrode of the second PMOS tube is electrically connected with a grid electrode of the second NMOS tube, a drain electrode of the second PMOS tube is electrically connected with the grid electrode of the second PMOS tube, a drain electrode of the second NMOS tube is electrically connected with an output end of the tie unit, and a source electrode of the second NMOS tube is grounded.

4. The chip version identification circuit according to any one of claims 1 to 3, wherein:

the number of version number circuits is eight.

5. A chip, characterized by: the circuit comprises a substrate, wherein a chip version identification circuit and output pins are arranged on the substrate, the chip version identification circuit comprises a plurality of version number circuits which output high levels or low levels, the number of the output pins is equal to that of the version number circuits, and the output end of each version number circuit is correspondingly and electrically connected with one output pin;

each version number circuit comprises a tieh unit for sending high level, a tiel unit for sending low level and an inverter, wherein the output end of the tieh unit or the output end of the tiel unit is electrically connected with the input end of the inverter through a metal lead, and the output end of the inverter is electrically connected with the corresponding output pin;

the tieh unit, the tiel unit and the inverter are all located on the same circuit layer of the substrate.

6. The chip of claim 5, wherein:

the tie unit comprises a first PMOS tube and a first NMOS tube, wherein a source electrode of the first PMOS tube is electrically connected with a power supply end, a grid electrode of the first PMOS tube is electrically connected with a grid electrode of the first NMOS tube, a drain electrode of the first PMOS tube is electrically connected with an output end of the tie unit, a drain electrode of the first NMOS tube is electrically connected with a grid electrode of the first NMOS tube, and a source electrode of the first NMOS tube is grounded.

7. The chip of claim 6, wherein:

the tie unit comprises a second PMOS tube and a second NMOS tube, wherein the source electrode of the second PMOS tube is electrically connected with the power supply end, the grid electrode of the second PMOS tube is electrically connected with the grid electrode of the second NMOS tube, the drain electrode of the second PMOS tube is electrically connected with the grid electrode of the second PMOS tube, the drain electrode of the second NMOS tube is electrically connected with the output end of the tie unit, and the source electrode of the second NMOS tube is grounded.

8. The chip according to any one of claims 5 to 7, wherein:

the version number circuits are sequentially arranged on the substrate.

9. The chip of any one of claims 5 to 7, wherein:

the number of version number circuits is eight.