CN106934122B - Method for accelerating generation of conductor graph connection relation in layout - Google Patents
Method for accelerating generation of conductor graph connection relation in layout Download PDFInfo
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Abstract
A method for accelerating the generation of the connection relation of conductor patterns in a layout comprises the following steps: (1) determining an initial tracking pattern; (2) tracking the patterns of other conductor layers which are the same as or directly connected with the initial tracking pattern, and adding the tracked patterns into a result queue; (3) tracking the via layer patterns connected with the initial tracking patterns, grouping the tracked via layer patterns, tracking the conductor layer patterns connected with each group of the via layer patterns, and adding the tracked conductor layer patterns into the result queue; (4) taking the conductor layer patterns in the result queue as initial tracking patterns in sequence, and executing the steps (2) and (3); (5) and collecting all the traced patterns of the conductor layer and the via layer to form a complete wire network. The invention can reduce the times of searching and connecting conductor layer patterns, reduce the times of checking whether the patterns are overlapped or not and improve the efficiency of wire mesh tracking aiming at multi-layer large-scale punching connection.
Description
Technical Field
The invention relates to the technical field of computer aided design, in particular to a method for accelerating the generation of a connection relation of conductor patterns in a layout.
Background
With the rapid development of modern signal processing technology and large-scale integrated circuit technology, the physical design complexity of very large-scale integrated circuits is higher and higher, the back-end physical design under the condition of ultra-deep submicron process is increasingly complex, and the design has to rely on the assistance of an Electronic Design Automation (EDA) tool, and the EDA relates to almost all aspects of the integrated circuit design flow.
When the physical verification of the large layout is carried out, the net graph tracking is carried out according to the graph and the vertical process information in the layout. With the increasing scale of the layout, the patterns in the layout are more and more complex, the number of the through holes and the metal layers is more and more, and the time cost spent on wire mesh tracking is more and more. When the EDA is used for physical verification of a large layout, the connection relationship of conductor patterns in the layout is usually required to be established quickly to form complete circuit routing. Wire mesh tracing (TraceNet) is a technology for automatically judging the connection relation of conductors according to two-dimensional graph information and process information in a layout to form a complete wire mesh graph. However, the performance of wire mesh tracing is seriously affected by more and more process layers, various shapes and huge through hole arrays.
Therefore, it is a problem to be solved urgently that a method for accelerating generation of connection relationship between conductor patterns in a layout is provided, which can reduce the number of times of searching for and connecting conductor layer patterns, reduce the number of times of checking whether patterns are overlapped, and improve the efficiency of wire mesh tracing for multi-level large-scale punching connection.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide a method for accelerating the generation of the connection relation of conductor patterns in a layout, which can reduce the times of searching and connecting the conductor layer patterns, reduce the times of checking whether the patterns are overlapped and improve the efficiency of wire network tracking aiming at multi-level large-scale punching connection.
In order to achieve the above object, the method for accelerating the generation of the connection relationship of the conductor patterns in the layout provided by the invention comprises the following steps:
(1) determining an initial tracking pattern; (2) tracking the patterns of other conductor layers which are the same as or directly connected with the initial tracking pattern, and adding the tracked patterns into a result queue; (3) tracking the via layer patterns connected with the initial tracking patterns, grouping the tracked via layer patterns, tracking the conductor layer patterns connected with each group of the via layer patterns, and adding the tracked conductor layer patterns into the result queue; (4) taking the conductor layer patterns in the result queue as initial tracking patterns in sequence, and executing the steps (2) and (3); (5) and collecting all the traced patterns of the conductor layer and the via layer to form a complete wire network.
Further, the step (1) of determining the initial trace pattern is to define an initial layer and point coordinates of the wire mesh trace according to the layout data and the corresponding process setting file, and determine the initial trace pattern.
Further, the grouping of the tracked via layer patterns in the step (3) is to group the via layer patterns according to the depth of the hierarchical structure in the layout.
Further, in the step (3), the tracking of the conductor layer patterns connected to each group of the via layer pattern groups is performed by using the outer frame of each group of the via layer pattern groups to track the conductor layer patterns connected to each group of the via layer pattern groups.
In the step (3), the tracking of the conductor layer patterns connected with each via layer pattern group further includes: and if the conductor layer pattern covering a certain group of the through hole layer pattern groups exists, replacing the certain group of the through hole layer pattern groups with the conductor layer pattern covering the certain group of the through hole layer pattern groups for tracking.
The invention provides a method for accelerating the generation of the connection relation of conductor patterns in a layout, which groups the patterns of a through hole layer and searches the patterns of the conductor layer which can be connected by using the grouped outer frame; meanwhile, the group of through hole layer graphs is conditionally ignored so as to reduce the times of searching and checking, accelerate the speed of net tracing and generate the netlist.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a wire mesh structure diagram with via connections in a layout according to the present invention;
FIG. 2 is a flow chart of a method for accelerated generation of a connection relationship of conductor patterns in a layout according to the present invention;
FIG. 3 is a block diagram of via layers in a layout according to the present invention;
FIG. 4 is a schematic diagram of a layout with via layers omitted according to the present invention;
FIG. 5 is a flowchart of an example net tracing for a layout according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a diagram of a wire mesh structure having via connection relationships in a layout according to the present invention, and in fig. 1, conductive layers C1 and C2 are connected through a via layer V.
The rules for net tracing of the present invention are explained in detail in order to facilitate an understanding of the present invention.
The rule for net tracing is defined as: for two conductor layers C1 and C2 connected with a via layer V, the initial tracking point is a graph C11 of a conductor layer C1, the outline border of the C11 is used for searching the graphs of the V layers possibly connected with the conductor layer, and for each graph of the searched V layers, whether the graph is really connected with the C11 is judged through the logical operation of the graphs, so that the graphs of all the V layers really connected with the C11 are obtained; then, for each graph of the obtained V layers, the same search technology is adopted to obtain the graph of the C2 layer connected with the graph, and all the traced graphs of the C1/V/C2 layers form a complete net.
Fig. 2 is a flowchart of a method for accelerating generation of connection relationships between conductor patterns in a layout according to the present invention, and the method for accelerating generation of connection relationships between conductor patterns in a layout according to the present invention will be described in detail with reference to fig. 2.
In step 201, preparing layout data and a corresponding process setting file;
in the step, the connection relation of each conductor layer in the large-scale layout is determined, and a complete circuit netlist structure is formed.
In step 202, defining the initial layer and the initial point coordinates of the net trace, and determining an initial trace graph;
in step 203, tracing the pattern of the other conductor layer which is the same layer as or directly connected with the initial tracing pattern, and adding the traced pattern into a result queue;
in step 204, via layer patterns connected with the initial trace pattern are traced, the traced via layer patterns are grouped, the conductor layer patterns connected with each via layer pattern group are continuously traced by using the outer frame of each via layer pattern group, and the traced conductor layer patterns are added into a result queue;
in the process definition, different conductor layer graphs are connected through punching, the number of the graphs of the through hole layer is large, and the graphs of the through hole layer are distributed according to the array of the layered structure; when a conductor layer pattern is checked to be connected with a plurality of through hole layer patterns, the conductor layer patterns connected with the through hole layer patterns are checked uniformly for the patterns of all the through hole layers.
In the step, the via layer graphs are grouped according to the graph array information of the via layer, a rectangular outer frame of each group of the via layer graph groups is taken, and other conductor layer graphs which are possibly connected with the group of the via layer graphs are searched according to the rectangular outer frame. If a conductor layer pattern completely contains the rectangular outline of the group of the via layer pattern groups, the via layer patterns in the group do not need to continuously check the connection relationship, and other patterns which are possibly connected with the group of the via layer pattern groups are directly tracked by using the conductor layer pattern.
The basis for accelerating net generation by performing a grouped search on the via layers is as follows: in the design of a large-scale layout, the layout has hierarchical structures with a plurality of depths, a high-level structure can refer to a plurality of low-level structures in an array mode, in each through hole layer array, the graphs are relatively concentrated, and the probability that all the graphs have the same conductor layer connection relation is also higher. The via layer graphs are grouped according to the array relation, each group of graphs are relatively concentrated, and searching and tracking are carried out according to the outer frame of each group of graphs, so that the speed of generating the wire net can be increased.
Further, the way of grouping the via layer patterns is as follows: firstly, roughly grouping according to the hierarchical depth of a via layer graph in a layout; then, accurately grouping all the graphs with the same depth according to the names of the layers; and finally, grouping according to whether all the graphs of the same layer are positioned in the same array structure.
Fig. 3 is a schematic diagram of grouping via layers in a layout according to the present invention, and in fig. 3, the via layer patterns are divided into four groups: graph groups Group1, Group2, Group3, and Group 4.
Further, in the process of respectively continuing to track the outer frames of each group of the through hole layer graphs, if a conductor layer graph covering a certain group of the through hole layer graph groups exists, the conductor layer graph is adopted to replace the group of the through hole layer graph groups for tracking. Some via layer pattern groups may be omitted by way of an alternative to tracking.
Specifically, when a group of via layer patterns are all located in the same array structure, and the outer frames of all the via layer patterns in the group are taken to remove the conductor layer C2 for searching, whether one conductor layer pattern covers the outer frame of the group of via layer patterns can be judged; if a graph C21 covering the outline of the group of the through hole layer graphs exists in the conductor layer C2, the graphs of all the groups of the through hole layer graphs having real connection relations can be obtained by directly tracking by taking the C21 as a starting point without continuously searching each through hole layer graph independently or judging whether other searched C2 layer graphs have real connection with the group of the through hole layer graphs. This is because the pattern having the true connection to the set of via layer patterns must have an overlapping relationship with C21.
Fig. 4 is a schematic diagram of a layout omitting a via layer according to the present invention, and in fig. 4, an outer frame of a via layer pattern group V is covered by a pattern C21 in a conductor layer C2, so that it is only necessary to trace the pattern C21.
In step 205, the conductor layer patterns in the result queue are sequentially used as the initial trace pattern, and steps 203 and 204 are performed;
in step 206, all the traced patterns of the conductive layer and the via layer are collected to form a complete wire mesh.
FIG. 5 is a flowchart of an example net tracing for a layout according to the present invention. In fig. 5, a conventional tracking process and a tracking process of the method of the present invention are shown, respectively, wherein the pattern group V is a via layer pattern group consisting of via layer patterns V1, V2, V3 and V4; graph C11 is the start trace graph, and graphs C12, C21, C22, and C23 are the traced graphs.
The conventional tracing process is as follows:
c11 search → C12 → detect C12;
c11 search → V1/V2/V3/V4 → detect V1/V2/V3/V4;
v1 search → C21 → detect C21;
v2 search → C21 → detect C21;
v3 search → C21 → detect C21;
v4 search → C21/C22 → detect C22;
c21 search → C22/C23 → detect C22/C23;
the tracking process of the invention is as follows:
c11 search → C12 → detect C12;
c11 search → V1/V2/V3/V4 → detect V1/V2/V3/V4;
v search → C21/C22 → detect C21/C22;
c21 search → C22/C23 → detect C22/C23.
Through comparison, the invention can reduce the searching and detecting times in the tracking process and reduce the time of wire network tracking, and the larger the layout is, the more the arrays of the through hole layers are, the more the acceleration effect is obvious.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (2)
1. A method for accelerating generation of connection relations of conductor patterns in a layout is characterized by comprising the following steps:
(1) determining an initial tracking pattern;
(2) tracking the patterns of other conductor layers which are the same as or directly connected with the initial tracking pattern, and adding the tracked patterns into a result queue;
(3) tracking the via layer patterns connected with the initial tracking patterns, grouping the tracked via layer patterns, tracking the conductor layer patterns connected with each group of the via layer patterns, and adding the tracked conductor layer patterns into the result queue;
(4) taking the conductor layer patterns in the result queue as initial tracking patterns in sequence, and executing the steps (2) and (3);
(5) collecting all the traced patterns of the conductor layer and the via layer to form a complete wire network;
wherein, the mode of grouping the via layer graphs in the step (3) is as follows: firstly, roughly grouping according to the hierarchical depth of a via layer graph in a layout; then, accurately grouping all the graphs with the same depth according to the names of the layers; finally, grouping is carried out according to whether all the graphs of the same layer are positioned in the same array structure;
and (3) when the conductor layer patterns connected with each group of the via layer patterns are tracked, adopting the following mode: taking a rectangular outer frame of each group of the via layer graph groups, searching other conductor layer graphs which are possibly connected with the group of the via layer graphs according to the rectangular outer frame, and directly tracking other graphs which are possibly connected with the group of the via layer graph groups by using the conductor layer graphs without continuously checking the connection relation if one conductor layer graph completely contains the rectangular outer frame of the group of the via layer graph groups; and in the process of respectively continuing to track the outer frames of each group of the through hole layer graphs, if a conductor layer graph covering a certain group of the through hole layer graph groups exists, the conductor layer graph is adopted to replace the group of the through hole layer graph groups for tracking.
2. The method for accelerating the generation of the connection relationship of the conductor patterns in the layout according to claim 1, wherein the step (1) of determining the initial trace pattern is to define the initial layer and point coordinates of the wire mesh trace according to the layout data and the corresponding process setting file, and determine the initial trace pattern.
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| CN111553124B (en) * | 2020-05-12 | 2022-06-17 | 北京华大九天科技股份有限公司 | Rapid tracking method for graphic connected region |
| CN112199918B (en) * | 2020-10-20 | 2021-09-21 | 芯和半导体科技(上海)有限公司 | Method for reconstructing physical connection relation of general EDA model layout |
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| CN105226012A (en) * | 2015-09-12 | 2016-01-06 | 上海华虹宏力半导体制造有限公司 | The extracting method of MOM capacitor |
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| CN105224708B (en) * | 2014-07-03 | 2019-01-18 | 台湾积体电路制造股份有限公司 | The determination method and apparatus at network in integrated circuit |
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| CN102663169A (en) * | 2012-03-21 | 2012-09-12 | 领佰思自动化科技(上海)有限公司 | Method and system for design rule checking of integrated circuit layout |
| CN105226012A (en) * | 2015-09-12 | 2016-01-06 | 上海华虹宏力半导体制造有限公司 | The extracting method of MOM capacitor |
| CN105740540A (en) * | 2016-01-29 | 2016-07-06 | 上海华虹宏力半导体制造有限公司 | Method for searching characteristic graphs of layouts in mask design |
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Address after: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee after: Beijing Huada Jiutian Technology Co.,Ltd. Address before: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee before: HUADA EMPYREAN SOFTWARE Co.,Ltd. |