CN106934141B - Acceleration method for calculating resistance based on long-edge cutting - Google Patents
Acceleration method for calculating resistance based on long-edge cutting Download PDFInfo
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Abstract
An acceleration method for calculating resistance based on long edge cutting comprises the following steps: cutting the wiring layout into a long-edge subgraph and a corner subgraph; acquiring template subgraphs, acquiring a port-based equivalent resistance network of the template subgraphs and applying the equivalent resistance network to each corner subgraph; combining the resistance network of the long-side subgraph and the equivalent resistance network of the corner subgraph into a resistance network of the wiring; the resistance of the wiring is calculated by the combined resistance network. According to the acceleration method for calculating the resistance based on the long-edge cutting, the long edge is cut by adopting a unique scanning line algorithm, a complex and large-scale layout is subjected to long-edge cutting, a small-scale and simple-shape graph is formed, the dimension of a solved matrix is reduced, and the time of a subdivision equation and an analytic equation is reduced; and a unique template-based acceleration technology is adopted, a template is extracted from the cut subgraph, equivalent transformation is carried out on a template resistance network, and a reduced total resistance network is combined, so that the speed of extracting the wiring resistance is improved.
Description
Technical Field
the invention relates to the technical field of EDA (electronic design automation) design, in particular to an acceleration method for calculating resistance based on long-edge cutting.
Background
In the field of EDA design, there are often some large-scale mesh wirings, and designers cannot quickly calculate the resistance between designated ports by means of personal techniques and experience. In order to achieve consistency of layout wiring signal delay, wiring resistance needs to be calculated accurately in a layout verification process, and accurate and rapid calculation of wiring resistance becomes more and more important in an iteration process of accelerating design.
the long-edge cutting algorithm in the prior art has certain limitation and cannot process parallel or series-parallel wiring; on the other hand, if the finite element method or the boundary element method is used to calculate the mesh interconnection resistance in the actual layout wiring, the calculation accuracy is poor and the calculation time is long.
Therefore, an acceleration method for calculating resistance based on long-edge cutting is provided, which can improve the calculation speed of the resistance of large-scale wiring without losing precision aiming at the geometric structure characteristics of the mesh wiring, and is a problem to be solved urgently.
disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide an acceleration method for calculating resistance based on long-edge cutting, which can improve the calculation speed of the resistance of a large-scale wiring without losing precision according to the geometric structure characteristics of the mesh wiring.
In order to achieve the purpose, the acceleration method for calculating the resistance based on the long-edge cutting comprises the following steps:
(1) Cutting the wiring layout into a long-edge subgraph and a corner subgraph; (2) acquiring template subgraphs, acquiring a port-based equivalent resistance network of the template subgraphs and applying the equivalent resistance network to each corner subgraph; (3) combining the resistance network of the long-side subgraph and the equivalent resistance network of the corner subgraph into a resistance network of the wiring; (4) the resistance of the wiring is calculated by the combined resistance network.
the step (1) further comprises: and cutting the wiring layout into a long-edge subgraph and a corner subgraph based on a scanning line algorithm.
The step (2) further comprises: and carrying out pattern recognition on each corner subgraph to obtain a template subgraph.
The step (2) further comprises: and carrying out finite element subdivision on the template subgraph to obtain a resistance network of the template subgraph.
The step (2) further comprises: and reducing the resistance network of the template subgraph into an equivalent resistance network based on a port.
the step (4) further comprises: and calculating the resistance of the long-side subgraph by using the square resistance, calculating the resistance of the corner subgraph by using a finite element method, and calculating the wiring resistance of the combined resistance network.
according to the acceleration method for calculating the resistance based on the long-edge cutting, the long edge is cut by adopting a unique scanning line algorithm, a complex and large-scale layout is subjected to long-edge cutting, a small-scale and simple-shape graph is formed, the dimension of a solved matrix is reduced, and the time of a subdivision equation and an analytic equation is reduced; and a unique template-based acceleration technology is adopted, a template is extracted from the cut subgraph, equivalent transformation is carried out on a template resistance network, and a reduced total resistance network is combined, so that the speed of extracting the wiring resistance is improved.
the invention has the beneficial effects that: according to the acceleration method for calculating the resistance based on the long-edge cutting, the long-edge cutting algorithm is used, so that the wiring scale needing to be calculated is reduced, the shape is relatively simple, and the calculation speed is improved; the use of template-based wire matching techniques further reduces the area that needs to be calculated, and also further increases the calculation speed. Under the condition of equivalent precision, the acceleration method for calculating the resistance based on the long-edge cutting has the advantage that the calculation speed is one order of magnitude faster than that of a pure finite element method.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of an acceleration method for calculating resistance based on long edge cutting according to the present invention;
FIG. 2 is a schematic diagram of a wiring layout to be calculated according to the present invention;
FIG. 3 is a schematic illustration of a cut long side of a wiring layout according to the present invention;
FIG. 4 is a schematic diagram of a corner sub-graph of a wiring layout according to the invention;
FIG. 5 is a schematic diagram of a resistive network port tag according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of an acceleration method for calculating resistance based on long-edge cutting according to the present invention, and the acceleration method for calculating resistance based on long-edge cutting according to the present invention will be described in detail with reference to fig. 1.
In step 101, cutting the wiring layout into a long-side subgraph and a corner subgraph;
In the step, based on a scan line algorithm, a large-scale two-dimensional wiring structure is cut into two types of wirings, namely 'long side' wiring and 'corner', and a plurality of sub-graphs and ports are generated in the cutting process.
in the process of cutting the layout, the large layout is divided into the small layouts, the size of the layout is reduced, and the speed of calculating the resistance of the layout by using the finite element method is improved conveniently.
In step 102, obtaining an equivalent resistance network of the corner subgraph by extracting a template subgraph of the corner subgraph;
In the step, firstly, carrying out pattern recognition on each corner subgraph to obtain a group of template subgraphs;
When pattern recognition is performed on each corner sub-graph, the following two items of information need to be compared between the corner sub-graphs:
1) whether the graphs of the corner subgraphs are consistent; 2) whether the relative positions of the ports of the corner subgraphs are consistent.
The specific process of comparison is as follows: 1. sequencing the corner subgraphs, and storing the corner subgraphs and the ports thereof which are arranged at the first position as template subgraphs into a template set;
2. sequentially comparing whether the relative positions of the graphs and the ports of the rest corner subgraphs and the template subgraphs in the template set are consistent or not;
3. If the two sub-image ports are consistent, recording the corresponding relation between the relative positions of the corner sub-image port and the template sub-image port;
4. And if the sub-images are not consistent, the corner sub-images and the ports of the corner sub-images are used as template sub-images to be stored in the template set.
in the process of comparing whether the relative positions of the graph and the port of the corner subgraph are consistent or not, a fixed position can be set, and the graph and the port of each corner subgraph are moved to the same fixed position and then compared.
Secondly, carrying out finite element subdivision on each template subgraph to obtain a resistance network of the template subgraph;
Then, the obtained template subgraph resistance network is reduced to an equivalent resistance network based on a port;
Finally, the port-based equivalent resistance network of the template subgraph described above is applied to each corner subgraph.
in step 103, combining the resistance network of the long-side subgraph and the equivalent resistance network of the corner subgraph into a resistance network of the wiring;
In the step, the matrix dimension of the combined resistance network is greatly reduced, so that the calculation speed of the wiring resistance is improved.
in step 104, the resistance of the wiring is calculated through the combined resistance network.
In the step, the resistance of the long-side subgraph is calculated by using the square resistance, the resistance of the corner subgraph is calculated by using a finite element method, and finally the resistance of the combined resistance network is calculated.
in this step, since the current density of the long side is uniform, the resistance of the long side subgraph is very accurate in terms of the aspect ratio, and the resistance of the long side subgraph = sheet resistance vs. The sheet resistance is typically user specified and pertains to process information.
The following describes in detail a specific procedure of the acceleration method for calculating resistance based on long-edge cutting according to the present invention with reference to specific examples.
1) opening a layout; fig. 2 is a schematic diagram of a wiring layout to be calculated according to the present invention.
2) traversing the layout to find out a long side, and cutting out a long side sub-graph and a corner sub-graph;
Fig. 3 is a schematic diagram of a cut long side of a wiring layout according to the present invention. As shown in fig. 3, during the cutting of the long edge, two non-boundary ports are generated on the long edge, and the non-boundary ports are connected to the long edge sub-graph and the corner sub-graph.
3) checking the body of the corner subgraph and extracting a template of the corner subgraph;
Before extraction, the corner subgraphs in the layout are numbered, and the ports of the corner subgraphs in the layout are marked with IDs. Fig. 4 is a schematic diagram of a corner subgraph of the wiring layout according to the invention, and as shown in fig. 4, the corner subgraph inspection forms with numbers Fig1, Fig2, Fig3 and Fig4 are subjected to pattern recognition.
the order of pattern recognition is Fig1, Fig2, Fig3, and Fig 4;
when the Fig1 is identified, if the template set does not have any information, the graph of the Fig1 and the port 6/3/7/11 are moved to a relatively fixed position (such as an origin) and are added into the template set as templates;
when Fig2 is identified, after the graph of Fig2 and the port 8/4/9/12 are moved to the relative fixed positions (the original points), whether a template which is consistent with the graph of Fig2 and the relative positions of the port 8/4/9/12 exists or not is searched in the template set;
if so, recording the corresponding relation between the template port id and the port id of the FIG 2; otherwise, adding the Fig2 as a template into the template set;
Pattern recognition was performed on Fig3 and Fig4 in the same manner as Fig 2.
After pattern recognition, the patterns and the relative positions of the ports of the FIG1, the FIG2, the FIG3 and the FIG4 are all consistent,
Fig1 is used as a template of Fig1, Fig2, Fig3 and Fig 4;
the corresponding relation between port ids of the Fig2 and the Fig1 is 3-4/6-8/7-9/11-12;
the corresponding relation between port ids of Fig3 and Fig1 is 3-13/6-16/7-17/11-21;
The correspondence between port ids for FIG4 and FIG1 is 3-14/6-18/7-19/11-22.
4) calculating an equivalent resistance network between ports of the corner subgraph template;
As shown in fig. 4, the equivalent resistance network between ports 3, 6, 7, 11 is calculated for Fig 1.
5) applying the equivalent resistance network of the corner subgraph template to the rest corner subgraphs;
As shown in fig. 4, the equivalent resistance network of Fig1 is applied to the corner sub-graphs Fig2, Fig3 and Fig 4.
For example, when FIG. 1 is extracted, the resistance network is:
R116/30.5 (meaning 0.5 resistance between Fig1 port 6/3)
R12 6/7 0.7
…
Through the correspondence between the port ids of Fig2 and Fig1, the resistance network of Fig2 is:
R218/40.5 (meaning 0.5 resistance between Fig2 port 8/4)
R22 8/9 0.7
…
6) And (4) forming a complete resistance network by the long-side subgraph and the corner subgraphs, and solving the resistance between wiring ports.
In the calculation process, the port of the whole resistor network is marked with ID, and FIG. 5 is a schematic diagram of the port mark of the resistor network according to the present invention. As shown in fig. 5, the port resistance between ports 5 to 20 is calculated.
According to the acceleration method for calculating the resistance based on the long-edge cutting, the long edge is cut by adopting a unique scanning line algorithm, a complex and large-scale layout is subjected to long-edge cutting, a small-scale and simple-shape graph is formed, the dimension of a solved matrix is reduced, and the time of a subdivision equation and an analytic equation is reduced; and a unique template-based acceleration technology is adopted, a template is extracted from the cut subgraph, equivalent transformation is carried out on a template resistance network, and a reduced total resistance network is combined, so that the speed of extracting the wiring resistance is improved.
those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. an acceleration method for calculating resistance based on long edge cutting is characterized by comprising the following steps:
(1) cutting the wiring layout into a long-edge subgraph and a corner subgraph;
(2) acquiring template subgraphs, acquiring a port-based equivalent resistance network of the template subgraphs and applying the equivalent resistance network to each corner subgraph;
(3) combining the resistance network of the long-side subgraph and the equivalent resistance network of the corner subgraph into a resistance network of the wiring;
(4) calculating the resistance of the wiring through the combined resistance network;
The step (2) further comprises: and performing pattern recognition on each corner sub-graph, and comparing whether the relative positions of the graph and the port between the corner sub-graphs are consistent or not to obtain a template sub-graph.
2. the acceleration method for calculating resistance based on long edge cutting according to claim 1, wherein the step (1) further comprises: and cutting the wiring layout into a long-edge subgraph and a corner subgraph based on a scanning line algorithm.
3. The acceleration method for calculating resistance based on long edge cutting as claimed in claim 1, wherein said step (2) further comprises: and carrying out finite element subdivision on the template subgraph to obtain a resistance network of the template subgraph.
4. The acceleration method for calculating resistance based on long edge cutting as claimed in claim 1, wherein said step (2) further comprises: and reducing the resistance network of the template subgraph into an equivalent resistance network based on a port.
5. The acceleration method for calculating resistance based on long edge cutting as claimed in claim 1, wherein said step (4) further comprises: and calculating the resistance of the long-side subgraph by using the square resistance, calculating the resistance of the corner subgraph by using a finite element method, and calculating the wiring resistance of the combined resistance network.
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| CN2016112522942 | 2016-12-30 | ||
| CN201611252294 | 2016-12-30 |
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| CN106934141A CN106934141A (en) | 2017-07-07 |
| CN106934141B true CN106934141B (en) | 2019-12-06 |
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| CN111079360B (en) * | 2019-12-30 | 2023-09-22 | 北京华大九天科技股份有限公司 | Extraction method of direct-connection metal resistor |
| CN112560386B (en) * | 2020-12-09 | 2022-05-24 | 南京华大九天科技有限公司 | Large-scale complex layout resistance extraction acceleration method |
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| US6032082A (en) * | 1996-03-01 | 2000-02-29 | Fujitsu Limited | Method and CAD system for calculating semiconductor circuit resistance |
| CN104217046A (en) * | 2013-06-03 | 2014-12-17 | 绩达特软件(北京）有限公司 | Wiring method and device |
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| US6032082A (en) * | 1996-03-01 | 2000-02-29 | Fujitsu Limited | Method and CAD system for calculating semiconductor circuit resistance |
| CN104217046A (en) * | 2013-06-03 | 2014-12-17 | 绩达特软件(北京）有限公司 | Wiring method and device |
| CN104731987A (en) * | 2013-12-18 | 2015-06-24 | 北京华大九天软件有限公司 | Parasitic resistance and capacitance estimating method of early layout |
| CN105808791A (en) * | 2014-12-29 | 2016-07-27 | 北京华大九天软件有限公司 | An acceleration method for resistance calculation mesh division |
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Address after: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee after: Beijing Huada Jiutian Technology Co.,Ltd. Address before: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee before: HUADA EMPYREAN SOFTWARE Co.,Ltd. |