CN117151003A - FPGA layout method and device based on clock domain division - Google Patents
FPGA layout method and device based on clock domain division Download PDFInfo
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Abstract
The application provides an FPGA layout method based on clock domain division, which comprises the following steps: obtaining a netlist of the FPGA; obtaining a layout block through a net of the netlist; dividing the layout blocks according to a time sequence diagram to obtain first clock domain layout blocks; dividing the first clock domain layout block according to modules to obtain a programmable logic cluster; carrying out coordinate judgment on the programmable logic cluster to obtain the first coordinate information; and determining the coordinate position of each layout block through the first coordinate information of the programmable logic cluster. In the initial layout of the FPGA, the method for dividing the layout block into a plurality of programmable logic clusters by adopting the clock domain dividing method is adopted, and then the technique of initial layout is carried out, so that the effect of the initial layout of the FPGA is improved, and the performance of the layout result is improved. The application also provides a device with corresponding advantages.
Description
Technical Field
The application belongs to the field of software design of programmable logic devices, and particularly relates to an FPGA layout method and device based on clock domain division.
Background
The purpose of the FPGA layout is to determine the physical locations of logic units such as programmable logic Clusters (CLBs), input/Output blocks (IOBs), memories (BRAMs), digital Signal Processing (DSPs) in the circuits on the FPGA chip. Layout is an important stage in the FPGA CAD flow, and the result directly influences the routing rate and performance of the circuit. With the increase of the capacity and complexity of the FPGA, a high-performance FPGA layout algorithm has become a research hotspot in the current CAD field. The performance of the FPGA layout algorithm is improved, and the method has very important effects on improving the level of the whole CAD tool and shortening the design period of an application circuit.
The currently mainstream FPGA layout algorithm comprises three phases: initial layout, global layout, and detailed layout. The initial layout stage allocates initial coordinate positions for all logic blocks of the layout by random or simulated annealing and other methods. The global layout stage minimizes the line length by solving the mathematical equation, and the layout result obtained after solving the equation has a large number of overlapped logic blocks, which is illegal. Therefore, the overlapped logic blocks need to be removed through legal movement, and legal layout results are generated. But this typically results in reduced layout quality, such as increased line length and delay. The detailed layout stage is further optimization of the result of the composite layout, thereby improving the performance of the circuit.
Disclosure of Invention
The application provides an FPGA layout method and device based on clock domain division, which aims to solve all or part of the problems in the prior art, improve the effect of the initial layout of the FPGA and improve the performance of the layout result. In order to achieve the above purpose, the technical scheme of the application is realized as follows:
an embodiment of the present application provides an FPGA layout method based on clock domain division, including:
obtaining a netlist of the FPGA; obtaining a layout block through a net of the netlist; dividing the layout blocks according to a time sequence diagram to obtain first clock domain layout blocks; dividing the first clock domain layout block according to modules to obtain a programmable logic cluster; carrying out coordinate judgment on the programmable logic cluster to obtain first coordinate information of the programmable logic cluster; and determining the coordinate position of each layout block through the first coordinate information of the programmable logic cluster.
Based on the above method, a layout block is obtained through a net of the netlist, the layout block is divided according to a timing diagram, and a first clock domain layout block is obtained, and the method further comprises:
the layout blocks at least comprise a first layout block and a second layout block; traversing the net of the netlist through a time sequence diagram to obtain a clock domain set; obtaining a first clock signal according to the clock domain set; one end of the netlist net is connected with the first layout block to obtain a second clock signal; the other end of the wire net is connected with the second layout block to obtain a third clock signal; if the first clock signal is greater than the second clock signal, the second clock signal is equal to the first clock signal; if the first clock signal is greater than the third clock signal, the third clock signal is equal to the first clock signal; the first layout block and the second layout block obtain a first clock domain layout block according to a first clock signal.
Based on the method, the coordinate judgment is carried out on the programmable logic cluster to obtain first coordinate information of the programmable logic cluster, and the method further comprises the steps of;
predefining a first coordinate location of the programmable cluster; selecting one from the N programmable block clusters as an initial programmable cluster; randomly selecting the coordinate position of the initial programmable cluster to obtain a second coordinate position; judging whether the length of the layout line is reduced after the initial programmable cluster selects the second coordinate position, if so, moving the coordinate position of the initial programmable cluster to the second coordinate position to obtain the first coordinate information of the initial programmable logic cluster, otherwise, turning to a step of selecting an undefined position from N programmable clusters as the initial programmable cluster.
Based on the above method, determining, by the first coordinate information of the programmable logic cluster, a coordinate position of each layout block, further includes:
the first coordinate information of the programmable logic cluster at least comprises N pieces of coordinate information of the layout blocks; sorting the N pieces of layout block coordinate information according to the abscissa size of the coordinate information to obtain a first list; and expanding according to the first list and the ordinate direction of the coordinate information to obtain the coordinate position of each layout block.
A second aspect of the embodiments of the present disclosure provides an FPGA layout device based on clock domain division, which is characterized by including:
the acquisition module is used for acquiring a netlist of the FPGA; a first processing module, configured to obtain a layout block through a net of the netlist; the first dividing module is used for dividing the layout blocks according to a time sequence diagram to obtain first clock domain layout blocks; the second division module is used for dividing the first clock domain layout block according to the modules to obtain a programmable logic cluster; the judging module is used for carrying out coordinate judgment on the programmable logic cluster to obtain first coordinate information of the programmable logic cluster; and the determining module is used for determining the coordinate position of the layout block through the first coordinate information of the programmable logic cluster.
A third aspect of an embodiment of the present disclosure provides an electronic device, including: a memory; and the processor is connected with the memory and is used for executing the computer executable instructions stored on the memory and realizing the FPGA layout method based on clock domain division provided by any of the first aspect or the second aspect.
A fourth aspect of the disclosed embodiments provides a computer storage medium comprising: the computer storage medium stores computer-executable instructions; after the computer executable instructions are executed, the FPGA layout method based on clock domain division provided by any of the first aspect or the second aspect can be realized.
Compared with the prior art, the application has the main beneficial effects that: in the initial layout of the FPGA, a clock domain dividing method is adopted to divide a layout block into a plurality of programmable logic clusters, and then an initial layout technology is carried out, so that the effect of the initial layout of the FPGA is improved, and the performance of a layout result is improved.
Drawings
FIG. 1 is a schematic flow chart of an FPGA layout method based on clock domain division;
FIG. 2 is a schematic flow chart of netlist division in an FPGA layout method based on clock domain division according to an embodiment of the present application;
FIG. 3 is a schematic flow chart of a method for analyzing a clock domain set where each net is located in an FPGA layout method based on clock domain division according to an embodiment of the present application;
fig. 4 is a flow chart of a method for dividing internal layout blocks of each clock domain in the FPGA layout method based on clock domain division according to the embodiment of the present application;
fig. 5 is a schematic diagram of a legal flow in an FPGA layout method based on clock domain division according to an embodiment of the present application;
FIG. 6 is a schematic flow chart of a legal processing method for each layout block in an FPGA layout method based on clock domain division according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an FPGA layout device based on clock domain division according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
Detailed Description
So that the manner in which the features and objects of the present application can be understood in more detail, a more particular description of the application, briefly summarized above, may be had by reference to the appended drawings, which are not necessarily limited to the embodiments described.
As shown in fig. 1, an embodiment of the present disclosure provides an FPGA layout method based on clock domain division, where the method includes:
s110: obtaining a netlist of the FPGA;
s120: obtaining a layout block through a net of the netlist;
s130: dividing the layout blocks according to a time sequence diagram to obtain first clock domain layout blocks;
s140: dividing the first clock domain layout block according to modules to obtain a programmable logic cluster;
s150: carrying out coordinate judgment on the programmable logic cluster to obtain first coordinate information of the programmable logic cluster;
s160: and determining the coordinate position of the layout block through the first coordinate information of the programmable logic cluster.
The netlist of the FPGA refers to a description mode for describing the connection condition of a digital circuit by using basic logic gates. Netlists typically convey information about circuit connections, such as instances of modules, nets, and related attributes. If more hardware information is required, hardware description languages, such as Verilog, VHDL, or other proprietary languages, are typically used for description, verification, and simulation. The hardware description of high abstraction level (such as register transfer level) can be converted into the circuit wiring netlist of low abstraction level (logic gate level) through logic synthesis, and this step can be accomplished by using automation technology, which also greatly reduces the complexity of the designer to handle very large scale integrated circuits. The hardware manufacturer may manufacture a specific application specific integrated circuit or other circuit using the netlist. Some relatively small circuits may also be implemented on field programmable gate arrays.
The time sequence diagram refers to the time sequence of the relevant signals of the control function of the circuit chip, and the response relationship among the signals. Accurate timing coordination between the different signals can achieve the desired control function. The clock signals in the timing diagram are divided into two types: with and without arrows. The arrow at the clock edge with up refers to the rising edge trigger. While rising edge triggering refers to triggering an action, such as sampling data, when the clock signal rises. In addition to rising edge triggering and falling edge triggering, there are high level triggering and low level triggering.
The module refers to a basic unit in the FPGA hardware language design. In digital circuits, complex circuits or circuits with specific functions are often packaged for use as a module. When a plurality of modules are combined with each other, a system can be formed, and complex problems are solved; the module may be invoked directly in use.
In some embodiments, the S110 may include:
firstly, translating Verilog codes in the FPGA through a compiler and a synthesis tool, and converting the Verilog codes into a netlist.
In some embodiments, the S120 may include:
the layout blocks connected with the starting points of the wire nets are first layout blocks; the layout blocks connected at the end of the net are the second layout blocks.
In some embodiments, the S130 may include:
the layout blocks at least comprise a first layout block and a second layout block; traversing the net of the netlist through a time sequence diagram to obtain a clock domain set; obtaining a first clock signal according to the clock domain set; one end of the netlist net is connected with the first layout block to obtain a second clock signal; the other end of the wire net is connected with the second layout block to obtain a third clock signal; if the first clock signal is greater than the second clock signal, the second clock signal is equal to the first clock signal; if the first clock signal is greater than the third clock signal, the third clock signal is equal to the first clock signal; the first layout block and the second layout block obtain a first clock domain layout block according to the second clock signal and the third clock signal.
In some embodiments of the present application, in some embodiments,
traversing on a time sequence diagram, and finding a set clock (n) of a clock domain where each net is located;
traversing each clock c of clock (n) for each net n;
finding a layout block s where the starting point of the net n is located; if the frequency of clock c is greater than the frequency of clock(s), then clock(s) =c;
a layout block d for each end point of the net n; if the frequency of clock c is greater than the frequency of clock (d), then clock (d) =c;
dividing all layout blocks in the netlist according to clock domains, so that each layout block is divided into corresponding clock domains;
within each clock domain, the layout blocks are partitioned by modules (modules) until the entire netlist is partitioned into about the parameters N programmable logic clusters (Cluster). By the method, the initial layout effect of the FPGA is improved, and the performance of a layout result is improved.
In some embodiments, the S140 may include:
within each clock domain, the layout blocks are partitioned in modules (modules) until the entire netlist is partitioned into about a parameter N programmable logic clusters.
In some embodiments, the S150 may include:
the N programmable logic clusters are distributed with initial random positions, then the positions are exchanged for a certain number of times at each temperature, new layout is accepted according to a certain rule, and finally the whole layout cost is stabilized, so that a relatively stable layout result is achieved. After the simulated annealing algorithm is finished, each programmable logic cluster is laid out to a coordinate position. But since each programmable logic cluster contains a number of layout blocks, the layout positions of the layout blocks of each programmable logic cluster adopt the layout positions of the programmable logic clusters. It is also necessary to assign a legal coordinate position to each layout block through the process of expansion and legalization.
Generating a crowded area for each programmable logic cluster; sequentially expanding a unit size range leftwards, rightwards, downwards and upwards respectively; if another crowded area is encountered in the process of expanding to 4 directions, merging the crowded area into the current crowded area; stopping the expansion of the current region if the expanded new region range can meet the layout block requirement of the current region; otherwise, the expansion is continued to be respectively carried out to the left, the right, the downward and the upward in sequence until the resources of the area meet the requirements.
In some embodiments, the S160 may include:
ordering all layout blocks in each region in the expanded region set S according to the order from small to large of the x coordinates; then find the center point p of the layout block in this area, divide the layout block in this area into two parts of left and right; then, according to the center point p of the layout block, finding a resource center point q in the area, and dividing the resources in the area into a left part and a right part; in the divided left and right partial areas, a linear interpolation method is adopted, and layout blocks in the left and right areas are inserted into proper coordinate positions according to the sequence of x coordinates; adding the new segmented region into the set S; expanding all layout blocks in the region according to the y direction; until all regions in set S have been processed; find a legal position for each layout block and move the layout block to a new position.
As shown in fig. 2, a schematic flow diagram of netlist division in an FPGA layout method based on clock domain division is provided in this embodiment;
in some embodiments of the present application, in some embodiments,
traversing on a time sequence diagram, and finding a set clock (n) of a clock domain where each net is located;
traversing each clock c of clock (n) for each net n;
finding a layout block s where the starting point of the net n is located; if the frequency of clock c is greater than the frequency of clock(s), then clock(s) =c;
a layout block d for each end point of the net n; if the frequency of clock c is greater than the frequency of clock (d), then clock (d) =c;
dividing all layout blocks in the netlist according to clock domains, so that each layout block is divided into corresponding clock domains;
within each clock domain, the layout blocks are partitioned by modules (modules) until the entire netlist is partitioned into about the parameters N programmable logic clusters (Cluster). By the method, the initial layout effect of the FPGA is improved, and the performance of a layout result is improved.
As shown in fig. 3, in this embodiment, a flow diagram of a method for analyzing a clock domain set where each net is located in an FPGA layout method based on clock domain division is provided;
in some embodiments of the present application, in some embodiments,
for each node s on the time sequence diagram level 0, finding a clock domain c where the node s is located, and executing the following procedure;
resetting the values of all nodes of the set visited to false, and setting visited [ s ] =true;
traversing each output edge (s, d) of node s, setting visited [ d ] =true;
for each level i from level 1 to N, N representing the maximum level N of the timing diagram, the following procedure is performed;
for each node v of level i, performing the following procedure; if the node v is the starting point of a certain network n, executing to add the node s into a network n time sequence path starting point set source [ n ], and if the node v is not the starting point of the certain network n, judging the value of the visible [ v ]; if visited [ v ] =true, traversing each output edge (v, d) of node v, setting visited [ d ] =true; if visible [ v ] = false, return to step for each node v of level i.
As shown in fig. 4, a flow chart of a method for dividing internal layout blocks of each clock domain of the FPGA layout method based on clock domain division is provided in this embodiment;
in some embodiments of the present application, in some embodiments,
calculating the number of Cluster which can be divided in the clock domain according to the formula Cluster (i) =N×B (i)/(Σi ε CB (i)), wherein N is a parameter representing the total number of Cluster which is divided in the whole netlist; b (i) represents the number of layout blocks belonging to the clock domain i; c represents the number of clock domains for the entire netlist;
dividing the layout block of the clock domain i according to modules (modules) if the Cluster (i) >1, and dividing the layout block of the clock domain i into M clusters if the layout block of the clock domain i contains M modules;
if Cluster (i) > M, for each module j of clock domain i, calculating the number of clusters (j) =cluster (i) ×B (j)/(Σj ε MB (j)), cluster (i) representing the number of clusters that can be partitioned by clock domain i, B (j) representing the number of layout blocks that module j contains, M representing the number of modules that clock domain i contains;
dividing the layout block of the module j according to the module (module) of the next stage if the module (j) >1, and dividing the layout block of the module j into K Cluster if the layout block of the module j contains K sub-modules;
counting that the total number of Cluster divided by the current clock domain i is larger than the number of Cluster (i), and stopping netlist division of the clock domain i; otherwise, continuing to divide modules of the next stage.
As shown in fig. 5, a schematic flow diagram of legalization in an FPGA layout method based on clock domain division is provided in this embodiment;
in some embodiments of the present application, in some embodiments,
the N Cluster initial random positions are distributed, then the positions are exchanged for a certain number of times at each temperature, new layout is accepted according to a certain rule, and finally the whole layout cost is stabilized, so that a relatively stable layout result is achieved. After the simulated annealing algorithm is finished, each Cluster is laid out to one coordinate position. However, since each Cluster includes a plurality of layout blocks, the layout position of the layout block of each Cluster is the layout position of the Cluster. Therefore, the expansion and legal treatment is needed, and a legal coordinate position is allocated to each layout block; although all Cluster have assigned coordinate locations, all layout blocks of each Cluster share one coordinate location, and many locations overlap. Therefore, the problem of overlapping of the positions of the layout blocks is solved by expanding the areas with crowded resources, and each layout block is allocated to an independent coordinate position through legal processing.
Generating a crowded area for each Cluster; sequentially expanding a unit size range leftwards, rightwards, downwards and upwards respectively; if another crowded area is encountered in the process of expanding to 4 directions, merging the crowded area into the current crowded area; stopping the expansion of the current region if the expanded new region range can meet the layout block requirement of the current region; otherwise, the expansion is continued to be respectively carried out to the left, the right, the downward and the upward in sequence until the resources of the area meet the requirements.
Ordering all layout blocks in each region in the expanded region set S according to the order from small to large of the x coordinates; then find the center point p of the layout block in this area, divide the layout block in this area into two parts of left and right; then, according to the center point p of the layout block, finding a resource center point q in the area, and dividing the resources in the area into a left part and a right part; in the divided left and right partial areas, a linear interpolation method is adopted, and layout blocks in the left and right areas are inserted into proper coordinate positions according to the sequence of x coordinates; adding the new segmented region into the set S; expanding all layout blocks in the region according to the y direction; until all regions in set S have been processed; find a legal position for each layout block and move the layout block to a new position.
As shown in fig. 6, a flow chart of a legal processing method for each layout block in an FPGA layout method based on clock domain division is provided in this embodiment;
in some embodiments of the present application, in some embodiments,
setting the initial value of the radius r to be 0, wherein the cost of legally moving the layout block is 1000000000, and the optimal legalization position of the layout block is (-1, -1); judging whether the position of the current layout block b is legal or not, and if not, setting a radius r+1; randomly selecting a position (nx, ny) within a circular range of a radius r by taking the position of the current layout block b as a circular point;
judging whether the layout block b moves to the position (nx, ny) or not is legal, if so, calculating the sum cost of the line length costs of the line network related to the layout block b after the layout block b moves to the position (nx, ny), otherwise, setting the limit+1; if min_cost > cost, then min_cost=cost, best_id= (nx, ny);
if it > =2r, if best_id +|= (-1, -1), then the position (nx, ny) is the legal position of the layout block b, otherwise, the position of the current layout block b is a dot again, and a position (nx, ny) is randomly selected within the circular range of radius r; if best_id= (-1, -1), then radius r+1 is set and iteration number itry=0.
As shown in fig. 7, a schematic structural diagram of an FPGA initial layout method based on clock domain division is provided in this embodiment.
An obtaining module 110, configured to obtain a netlist of the FPGA;
a first processing module 120, configured to obtain a layout block through a net of the netlist;
a first dividing module 130, configured to divide the layout blocks according to a timing diagram to obtain first clock domain layout blocks;
a second dividing module 140, configured to divide the first clock domain layout block according to a module to obtain a programmable logic cluster;
the judging module 150 is configured to perform coordinate judgment on the programmable logic cluster to obtain first coordinate information of the programmable logic cluster;
a determining module 160, configured to determine, according to the first coordinate information of the programmable logic cluster, a coordinate position of the layout block.
In some embodiments, the acquisition module 110, the first processing module 120, the first partitioning module 130, the second partitioning module 140, the determination module 150, and the determination module 160 may be program modules; the program modules may implement the operations of the various modules described above when executed by a processor.
In other embodiments, the acquiring module 110, the first processing module 120, the first dividing module 130, the second dividing module 140, the judging module 150, and the determining module 160 may be a soft-hard combination module; the soft and hard combined die block comprises but is not limited to: various programmable arrays; the programmable array includes, but is not limited to: a field programmable array and/or a complex programmable array.
In still other embodiments, the acquisition module 110, the first processing module 120, the first partitioning module 130, the second partitioning module 140, the determination module 150, and the determination module 160 may be pure hardware modules; the pure hardware modules wrap around but are not limited to: an application specific integrated circuit.
As shown in fig. 8, an embodiment of the present disclosure provides an electronic device, including:
a memory;
a processor, coupled to the memory, for enabling the implementation of the methods provided in any of the preceding embodiments, e.g., performing the methods as shown in any of fig. 1-6, by executing computer-executable instructions stored on the memory.
The electronic device may be a terminal device and/or a server in a service platform.
As shown in fig. 8, the electronic device may also include a network interface that may be used to interact with a peer device over a network.
Embodiments of the present disclosure provide a computer storage medium having stored thereon computer-executable instructions; the computer-executable instructions, when executed by a processor, enable the method provided by any of the foregoing embodiments, such as performing the method as shown in any of figures 1-6.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (7)
1. The FPGA layout method based on clock domain division is characterized by comprising the following steps:
obtaining a netlist of the FPGA;
obtaining a layout block through a net of the netlist;
dividing the layout blocks according to a time sequence diagram to obtain first clock domain layout blocks;
dividing the first clock domain layout block according to modules to obtain a programmable logic cluster;
carrying out coordinate judgment on the programmable logic cluster to obtain first coordinate information of the programmable logic cluster;
and determining the coordinate position of each layout block through the first coordinate information of the programmable logic cluster.
2. The FPGA layout method based on clock domain partitioning of claim 1, wherein a layout block is obtained by a net of the netlist, the layout block is partitioned according to a timing diagram to obtain a first clock domain layout block, further comprising:
the layout blocks at least comprise a first layout block and a second layout block;
traversing the net of the netlist through a time sequence diagram to obtain a clock domain set;
obtaining a first clock signal according to the clock domain set;
one end of the netlist net is connected with the first layout block to obtain a second clock signal; the other end of the wire net is connected with the second layout block to obtain a third clock signal;
if the first clock signal is greater than the second clock signal, the second clock signal is equal to the first clock signal;
if the first clock signal is greater than the third clock signal, the third clock signal is equal to the first clock signal;
the first layout block and the second layout block obtain a first clock domain layout block according to the second clock signal and the third clock signal.
3. The method for arranging an FPGA based on clock domain division according to claim 1, wherein the coordinate judgment is performed on the programmable logic cluster to obtain first coordinate information of the programmable logic cluster, and the method further comprises;
predefining a first coordinate location of the programmable cluster;
selecting one from the N programmable block clusters as an initial programmable cluster;
randomly selecting the coordinate position of the initial programmable cluster to obtain a second coordinate position;
judging whether the length of the layout line is reduced after the initial programmable cluster selects the second coordinate position, if so, moving the coordinate position of the initial programmable cluster to the second coordinate position to obtain the first coordinate information of the initial programmable logic cluster, otherwise, turning to a step of selecting an undefined position from N programmable clusters as the initial programmable cluster.
4. The FPGA layout method based on clock domain partitioning of claim 1, wherein determining the coordinate location of each of the layout blocks from the first coordinate information of the programmable logic cluster further comprises:
the first coordinate information of the programmable logic cluster at least comprises N pieces of coordinate information of the layout blocks;
sorting the N pieces of layout block coordinate information according to the abscissa size of the coordinate information to obtain a first list;
and expanding according to the first list and the ordinate direction of the coordinate information to obtain the coordinate position of each layout block.
5. An FPGA topology apparatus based on clock domain division, comprising:
the acquisition module is used for acquiring a netlist of the FPGA;
a first processing module, configured to obtain a layout block through a net of the netlist;
the first dividing module is used for dividing the layout blocks according to a time sequence diagram to obtain first clock domain layout blocks;
the second division module is used for dividing the first clock domain layout block according to the modules to obtain a programmable logic cluster;
the judging module is used for carrying out coordinate distribution on the programmable logic cluster to obtain first coordinate information of the programmable logic cluster;
and the determining module is used for determining the coordinate position of the layout block through the first coordinate information.
6. An electronic device, comprising:
a memory;
a processor, coupled to the memory, for executing computer-executable instructions stored on the memory and capable of implementing the clock domain division based FPGA layout method provided in any one of claims 1 to 4.
7. A computer storage medium having stored thereon computer executable instructions; the computer-executable instructions, when executed, enable the FPGA layout method based on clock domain partitioning provided in any one of claims 1 to 4.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311405423.7A CN117151003B (en) | 2023-10-27 | 2023-10-27 | FPGA layout method and device based on clock domain division |
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| CN202311405423.7A CN117151003B (en) | 2023-10-27 | 2023-10-27 | FPGA layout method and device based on clock domain division |
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| CN117151003A true CN117151003A (en) | 2023-12-01 |
| CN117151003B CN117151003B (en) | 2024-01-30 |
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