CN111539178B - Chip layout design method and system based on neural network and manufacturing method - Google Patents
Chip layout design method and system based on neural network and manufacturing method Download PDFInfo
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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Abstract
The invention discloses a chip layout design method and system based on a neural network and a manufacturing method, which belong to the technical field of digital integrated circuits, and comprise the following steps of S1: collecting RTL codes of the digital integrated circuit, and identifying to obtain a physical unit; s2: classifying physical units and reading in design rule data of a target layout; s3: setting the performance of the target layout to obtain the design parameters of the target layout, and setting a placement barrier layer and a wiring barrier layer; s4: training a neural network, pre-placing physical units according to the trained neural network, outputting position coordinates of each physical unit after pre-placing, actually placing, and adding special physical units; s5: setting a power supply and a grounding network, checking design rules and simulating to obtain a target layout meeting preset performance; the invention solves the problems that the existing digital integrated circuit layout design needs to manually put physical units and manually iterate, so that the labor cost is high, the design efficiency is low, and the success rate of the chip flow is affected.
Description
Technical Field
The invention belongs to the technical field of digital integrated circuits, and relates to a chip layout design method and system based on a neural network and a chip manufacturing method of an integrated circuit layout designed based on the method.
Background
With the advancement of technology, integrated circuit technology has entered the nanoera. The integrated circuit design method has wide involved range and complex content, wherein the layout design is the basic technology of the integrated circuit physical realization. The quality of the layout design directly affects the power consumption, performance and area of the integrated circuit. In the system chip design, an interface unit, a standard logic unit, an analog and mixed signal module, a memory and various IP modules are integrated. The physical implementation of all these modules is not separated from the basic layout design.
With the increase of the number of transistors integrated inside an integrated circuit and the gradual increase of the product iteration speed, in the integrated circuit technology, EDA tools become necessary basic means, a series of research results of integrated circuit layout design methods are embodied in the integrated circuit, the research results play a role in the design process, and the IP core multiplexing technology is also widely used. However, in the digital chip design production process, various physical units are often required to be manually placed, so that not only is a great deal of labor cost increased, but also a great deal of effort is required to be spent for continuous iterative placement in the manual placement process, the design efficiency of the digital chip is greatly reduced, and the success rate of the chip is greatly influenced by the experience of the placement personnel of the digital integrated circuit layout. And because the number of macro units is too large, the automatic placement function of the system cannot meet the design rule of the target layout and cannot reach the preset performance.
Therefore, the invention provides a chip layout design method and system based on a neural network and a chip manufacturing method aiming at the problems.
Disclosure of Invention
The invention aims at: the chip layout design method, the chip layout design system and the chip layout manufacturing method based on the neural network are provided, and the problems that the manpower cost is high, the design efficiency is low and the success rate of chip streaming is influenced because the existing digital integrated circuit layout design needs to be manually put into physical units and manually iterated are solved.
The technical scheme adopted by the invention is as follows:
a chip layout design method based on a neural network comprises the following steps:
s1: acquiring RTL codes of the digital integrated circuit, identifying and obtaining physical units represented by the RTL codes, and then acquiring physical layout effect related parameters corresponding to each physical unit;
s2: the physical units obtained through identification in the step S1 are classified, wherein the classification comprises a basic logic unit and a macro unit, and design rule data of a digital integrated circuit target layout are read in, and the design rule data comprise basic attributes of each layer of metal of the digital integrated circuit;
s3: setting the performance of the digital integrated circuit target layout to obtain the design parameters of the digital integrated circuit target layout, and setting a placement barrier layer and a wiring barrier layer according to the design parameters;
s4: training a neural network, pre-placing the physical units classified in the step S2 according to the trained neural network, outputting the position coordinates of each physical unit after pre-placing, performing actual placing, and adding special physical units comprising trap units;
s5: and (3) setting a power supply and a grounding network for the physical units put in the step (S4), and then checking and simulating design rules to obtain a target layout meeting preset performances.
Further, the basic attributes in the step S2 include a minimum width, a maximum width, a minimum pitch, and a maximum density.
Further, training the neural network in the step S4 includes:
s41: collecting size information, shape information, pin information and functional attributes of various common physical units and taking the size information, the shape information, the pin information and the functional attributes as an original data set of the neural network to be trained;
s42: selecting a digital integrated circuit layout with higher success rate of streaming, manufacturing a marking data set, marking the position priority of macro units in an original data set, placing macro units with more connecting pins between each other in the digital integrated circuit layout on the periphery of the digital integrated circuit layout according to the area size and the utilization rate of the digital integrated circuit layout, taking the relative position information of each physical unit of the digital integrated circuit layout with higher success rate of streaming as a target set, taking the relative position information of each physical unit of the digital integrated circuit layout and the original data set of the step S41 as a training set of a neural network to be trained, and taking one fifth of the training set as a test set;
s43: determining the number of input ports of the neural network to be trained according to the data size dimension of the training set, and constructing a corresponding neural network according to specific requirements;
s44: transmitting the training set data to the neural network to be trained, calculating an updated weight value, and testing by using a testing set when the output data set of the neural network is in accordance with the target data set after iterative training, and stopping training until the accuracy of the neural network reaches the target requirement, so that the trained neural network is obtained.
Further, the pre-placing the physical units classified in the step S2 according to the trained neural network in the step S4 includes:
the trained neural network is adopted to classify the macro units, the classification comprises a storage unit and an IP core, the macro units are placed preferentially according to the size, the metal layers and different functions, proper intervals are reserved among the macro units according to different requirements, and then basic logic units are placed to finish pre-placement.
Further, the simulating in the step S5 includes:
and simulating layout effects of the pre-placed digital integrated circuit layout through a simulation tool, wherein the layout effects comprise the placement sequence of I/O, the power consumption of the layout, voltage drops of physical units at different positions in the layout, the isolation degree of analog signals and digital signals, whether an internal data path is shortest, whether the module distance of a key time path is shortest, whether wiring can be passed around, whether the optimal utilization rate of the layout is reached, and whether the time sequence is converged.
A chip layout design system based on a neural network adopts the chip layout design method based on the neural network, which comprises the following steps:
and a data acquisition module: collecting RTL codes of the digital integrated circuit and converting the RTL codes into physical units corresponding to the RTL codes;
and a classification module: classifying the physical units converted by the data acquisition module, and reading in design rule data of a digital integrated circuit target layout;
layout generation module: training a neural network, pre-placing the classified physical units according to the trained neural network, intelligently generating a digital integrated circuit layout meeting the set performance, and actually placing the digital integrated circuit layout;
layout simulation module: setting a power supply and a grounding network for the physical units placed by the layout generation module, checking design rules and simulating to obtain a target layout meeting preset performances.
Further, the layout generation module comprises a neural network training sub-module and a redundant unit adding sub-module;
the neural network training submodule obtains a training set and a testing set according to the physical units obtained by the data acquisition module and the classification module, builds and trains the neural network according to the training set to obtain a trained neural network, and outputs the position coordinates of each physical unit after intelligent pre-placement of the physical units obtained by the classification module according to the trained neural network;
and the redundant unit adding sub-module is used for carrying out actual placement according to the position coordinates of each physical unit and adding special physical units comprising the trap units.
A chip manufacturing method based on a neural network adopts the target layout designed by the chip layout design method based on the neural network to manufacture a digital integrated circuit chip.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
the neural network structure is introduced, the intelligent degree of the digital integrated circuit layout design method is greatly enhanced, the workload of a digital integrated circuit layout design engineer is greatly reduced through intelligent placement of the digital integrated circuit layout, more sufficient time is provided for post simulation and verification of the digital integrated circuit layout in the later period, and the design efficiency of the digital integrated circuit and the flow sheet yield of the digital integrated circuit are improved.
Drawings
For a clearer description of the technical solutions of embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and should not be considered limiting in scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a flow chart of a method of chip layout design based on neural networks;
FIG. 2 is a connection block diagram of a neural network based chip layout design system;
FIG. 3 is a schematic diagram of a target layout of a digital integrated circuit in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of an operational model of a neural network constructed in accordance with an embodiment of the present invention;
fig. 5 is a training flowchart for training a neural network in accordance with a first embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention, i.e., the embodiments described are merely some, but not all, of the embodiments of the invention. The components of the embodiments of the present invention generally described herein and shown in the figures can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
It is noted that relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The features and capabilities of the present invention are described in further detail below in connection with examples.
Example 1
The preferred embodiment of the invention provides a chip layout design method based on a neural network, as shown in fig. 1, comprising the following steps:
s1: acquiring RTL codes of the digital integrated circuit, identifying and obtaining physical units represented by the RTL codes, and then acquiring physical layout effect related parameters corresponding to each physical unit;
s2: the method comprises the steps that a physical unit is identified in a classification step S1, the classification type comprises a basic logic unit and a macro unit, and design rule data of a digital integrated circuit target layout are read in, wherein the design rule data comprise basic attributes of each layer of metal of the digital integrated circuit, and the basic attributes comprise minimum width, maximum width, minimum spacing and maximum density;
s3: setting the performance of a digital integrated circuit target layout shown in fig. 3, wherein the digital integrated circuit target layout comprises an I/O end and an internal module Core, the I/O end comprises an input/output unit and a power supply ground unit, for the convenience of subsequent packaging, an I/O Pad is added at the pin of the I/O, the internal module Core comprises a basic Logic unit (Logic) and a Macro unit (Macro cell), the Macro unit comprises a memory module (SRAM) and an IP Core, the IP Core comprises a phase-locked loop (PLL), a digital-to-analog conversion module (DAC) and a digital signal processing module (DSP), the digital integrated circuit target layout in the figure has 4n ports, wherein ' pi ' represents an input port, ' po ' represents an output port, ' PVDD ' represents a power supply port, PGND ' represents a ground port, and four corners are provided with special corner I/O pads to form a power ring and a ground ring at the periphery of the digital integrated circuit layout, the power ring can evenly distribute current, reduce voltage drop and electromigration problems, and P1 coupler, P2 coupler and P3 and P4/O corner Pad are all corner I/O pads; obtaining design parameters of a digital integrated circuit target layout according to preset performances, and setting a placement barrier layer (placement blockage) and a wiring barrier layer (routing block) according to the design parameters;
s4: training a neural network, pre-placing the physical units classified in the step S2 according to the trained neural network, outputting the position coordinates of each physical unit after pre-placing, performing actual placing, and adding special physical units comprising Well units (Well Taps);
s41: collecting size information, shape information, pin information and functional attributes of various common physical units and taking the size information, the shape information, the pin information and the functional attributes as an original data set of the neural network to be trained;
s42: selecting a digital integrated circuit layout with higher success rate of streaming, manufacturing a marking data set, marking the position priority of macro units in an original data set, placing macro units with more connecting pins between each other in the digital integrated circuit layout on the periphery of the digital integrated circuit layout according to the area size and the utilization rate of the digital integrated circuit layout, taking the relative position information of each physical unit of the digital integrated circuit layout with higher success rate of streaming as a target set, taking the relative position information of each physical unit of the digital integrated circuit layout and the original data set of the step S41 as a training set of a neural network to be trained, and taking one fifth of the training set as a test set;
s43: the number of input ports of the neural network to be trained is determined according to the data size dimension of the training set, and a corresponding neural network is built according to specific requirements, an operation model schematic diagram of the built neural network in this embodiment is shown in fig. 4, and the operation model schematic diagram comprises three layers, namely an input layer X1, an input layer X2, a hidden layer L1, an hidden layer L2 and an output layer, wherein each circle in the figure represents a neuron, and comprises signal input summation, and the summed signals are processed through an activation function to obtain output, wherein the activation function comprises a sigmoid function, a Tanh function, a ReLU function and the like, and the operation of one neuron is as follows:
f 1 (e)＝f 1 (w (x1)1 x 1 +w (x2)1 x 2 ，
wherein f 1 (e) Representing the activation function, and calculating to obtain an activation function f according to the operation formula 2 (e)、f 3 (e)、f 4 (e)、f 5 (e)、f 6 (e)、f 7 (e)；
S44: training the neural network of fig. 4, wherein the training flow chart is shown in fig. 5, transmitting training set data into the neural network to be trained, calculating an updated weight value through a back propagation algorithm, outputting a target result Y, and when the output data set of the iterative training to the neural network is consistent with the target data set, namely when a plurality of groups of training data simultaneously reach the target result Y, defaulting the neural network to be trained, then testing by using a testing set until the accuracy rate of the neural network reaches the target requirement, stopping training, and obtaining the trained neural network;
s45: classifying macro units by adopting a trained neural network, wherein the classification comprises a storage unit and an IP core, the macro units are placed preferentially according to the size, the metal layers and different functions, proper intervals are reserved among the macro units according to different requirements, and then basic logic units are placed to finish pre-placement;
s46: outputting the position coordinates of all the physical units after the pre-placement, then carrying out actual placement, and adding special physical units comprising trap units;
s5: setting a power supply and a grounding network for the physical units put in the step S4, checking design rules and simulating to obtain a target layout meeting preset performance, wherein the simulation simulates the layout effect of the pre-put digital integrated circuit layout through a simulation tool, and the layout effect comprises
Placement order of I/O: the method comprises the steps of arranging a signal I/O, a power supply I/O and a ground I/O in sequence, wherein the signal I/O comprises a high-frequency signal I/O and a conventional electric signal I/O; the qualified I/O arrangement sequence keeps balance for power supply of the whole digital integrated circuit chip, and cannot cause blockage of internal connecting wires of the digital integrated circuit chip or increase of connecting wires of redundant paths;
layout power consumption size: the overall power consumption of the chip is guaranteed to be in the lowest state after the digital integrated circuit layout is pre-placed;
voltage drop of physical units at different positions inside the layout: the voltage at different positions on the power supply and the ground network in the digital integrated circuit chip is reduced or increased, the voltage drop is determined by the equivalent resistance between the power supply PAD and the calculated logic gate unit, the whole IR-drop of the chip is ensured to be minimum after the intelligent pre-placement of the digital integrated circuit layout, and the voltage drop cannot be lower than the working voltage of any physical unit inside the digital integrated circuit chip;
isolation of analog and digital signals: after the digital integrated circuit layout is pre-placed, the analog signal physical units and the digital signal physical units are intelligently placed according to a certain area range, so that the analog signals and the digital signals of the physical units are ensured not to interfere with each other to normally work;
whether the internal data path is shortest: after the digital integrated circuit layout is pre-placed, the shortest connection line between the physical units is ensured as much as possible at the place with a data path between the internal physical units, and the condition of wire winding blockage does not occur;
whether the wiring can be wound or not: after the digital integrated circuit layout is pre-placed, the placement density of the internal physical units is ensured to ensure that the external connection lines of each physical unit can be normally connected;
whether the optimal utilization rate of the layout is reached: after the digital integrated circuit layout is pre-placed, the distribution density of the internal macro units and the physical logic units is optimal, so that the utilization rate of chips in unit area is ensured, and the overall streaming cost is saved;
whether the timing converges: after the digital integrated circuit layout is pre-placed, the establishing time and the maintaining time of each macro unit and each physical unit in the digital integrated circuit chip are required to meet the target working frequency of the chip.
Example two
On the basis of the first embodiment, the present embodiment provides a chip layout design system based on a neural network, as shown in fig. 2, including:
and a data acquisition module: collecting RTL codes of the digital integrated circuit and converting the RTL codes into physical units corresponding to the RTL codes;
and a classification module: classifying the physical units converted by the data acquisition module, reading in design rule data of a digital integrated circuit target layout, and ensuring that the generated digital integrated circuit layout meets the requirements of a practical production process;
layout generation module: training a neural network, pre-placing the classified physical units according to the trained neural network, intelligently generating a digital integrated circuit layout meeting the set performance, and actually placing the digital integrated circuit layout;
layout simulation module: setting a power supply and a grounding network for the physical units placed by the layout generation module, checking design rules and simulating to obtain a target layout meeting preset performances.
Further, the layout generation module comprises a neural network training sub-module and a redundant unit adding sub-module;
the neural network training submodule obtains a training set and a testing set according to the physical units obtained by the data acquisition module and the classification module, builds and trains the neural network according to the training set to obtain a trained neural network, and outputs the position coordinates of each physical unit after intelligent pre-placement of the physical units obtained by the classification module according to the trained neural network;
the redundant unit adding sub-module is actually placed according to the position coordinates of each physical unit, and a special physical unit comprising a trap unit is added, so that the success rate of the streaming can be improved.
Example III
The embodiment provides a chip manufacturing method based on a neural network on the basis of the first embodiment, and a target layout designed by the chip layout design method based on the neural network of the first embodiment is adopted to manufacture a digital integrated circuit chip.
The invention introduces a neural network structure, greatly enhances the intelligent degree of the digital integrated circuit layout design method, greatly lightens the workload of digital integrated circuit layout design engineers through the intelligent placement of the digital integrated circuit layout, provides more sufficient time for the post-simulation and verification of the digital integrated circuit layout in the later period, and improves the design efficiency of the digital integrated circuit and the flow sheet yield of the digital integrated circuit.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and modifications within the spirit and principles of the invention will become apparent to those skilled in the art.
Claims (5)
1. The chip layout design method based on the neural network is characterized by comprising the following steps of:
s1: acquiring RTL codes of the digital integrated circuit, identifying and obtaining physical units represented by the RTL codes, and then acquiring physical layout effect related parameters corresponding to each physical unit;
s2: the physical units obtained through identification in the step S1 are classified, wherein the classification comprises a basic logic unit and a macro unit, and design rule data of a digital integrated circuit target layout are read in, and the design rule data comprise basic attributes of each layer of metal of the digital integrated circuit;
s3: setting the performance of the digital integrated circuit target layout to obtain the design parameters of the digital integrated circuit target layout, and setting a placement barrier layer and a wiring barrier layer according to the design parameters;
s4: training a neural network, pre-placing the physical units classified in the step S2 according to the trained neural network, outputting the position coordinates of each physical unit after pre-placing, performing actual placing, and adding special physical units comprising trap units;
s5: setting a power supply and a grounding network for the physical units put in the step S4, and then checking design rules and simulating to obtain a target layout meeting preset performances;
the training the neural network in step S4 includes:
s41: collecting size information, shape information, pin information and functional attributes of various common physical units and taking the size information, the shape information, the pin information and the functional attributes as an original data set of the neural network to be trained;
s42: selecting a digital integrated circuit layout with higher success rate of streaming, manufacturing a marking data set, marking the position priority of macro units in an original data set, placing macro units with more connecting pins between each other in the digital integrated circuit layout on the periphery of the digital integrated circuit layout according to the area size and the utilization rate of the digital integrated circuit layout, taking the relative position information of each physical unit of the digital integrated circuit layout with higher success rate of streaming as a target set, taking the relative position information of each physical unit of the digital integrated circuit layout and the original data set of the step S41 as a training set of a neural network to be trained, and taking one fifth of the training set as a test set;
s43: determining the number of input ports of the neural network to be trained according to the data size dimension of the training set, and constructing a corresponding neural network according to specific requirements;
s44: transmitting the training set data to a neural network to be trained, calculating an updated weight value, and testing by using a testing set when the output data set of the neural network is in accordance with a target data set after iterative training, and stopping training until the accuracy of the neural network reaches the target requirement, so as to obtain a trained neural network;
in the step S4, pre-placing the physical units classified in the step S2 according to the trained neural network includes:
classifying macro units by adopting a trained neural network, wherein the classification comprises a storage unit and an IP core, the macro units are placed preferentially according to the size, the metal layers and different functions, proper intervals are reserved among the macro units according to different requirements, and then basic logic units are placed to finish pre-placement;
the simulating in the step S5 includes:
and simulating layout effects of the pre-placed digital integrated circuit layout through a simulation tool, wherein the layout effects comprise the placement sequence of I/O, the power consumption of the layout, voltage drops of physical units at different positions in the layout, the isolation degree of analog signals and digital signals, whether an internal data path is shortest, whether the module distance of a key time path is shortest, whether wiring can be passed around, whether the optimal utilization rate of the layout is reached, and whether the time sequence is converged.
2. The neural network-based chip layout design method as claimed in claim 1, wherein: the basic attributes in the step S2 include a minimum width, a maximum width, a minimum pitch, and a maximum density.
3. A chip layout design system based on a neural network is characterized in that: the chip layout design system based on the neural network is a system based on the chip layout design method based on the neural network of any one of claims 1 and 2, and comprises:
and a data acquisition module: collecting RTL codes of the digital integrated circuit and converting the RTL codes into physical units corresponding to the RTL codes;
and a classification module: classifying the physical units converted by the data acquisition module, and reading in design rule data of a digital integrated circuit target layout;
layout generation module: training a neural network, pre-placing the classified physical units according to the trained neural network, intelligently generating a digital integrated circuit layout meeting the set performance, and actually placing the digital integrated circuit layout;
layout simulation module: setting a power supply and a grounding network for the physical units placed by the layout generation module, checking design rules and simulating to obtain a target layout meeting preset performances.
4. A neural network based chip layout design system according to claim 3, wherein: the layout generation module comprises a neural network training sub-module and a redundant unit adding sub-module;
the neural network training submodule obtains a training set and a testing set according to the physical units obtained by the data acquisition module and the classification module, builds and trains the neural network according to the training set to obtain a trained neural network, and outputs the position coordinates of each physical unit after intelligent pre-placement of the physical units obtained by the classification module according to the trained neural network;
and the redundant unit adding sub-module is used for carrying out actual placement according to the position coordinates of each physical unit and adding special physical units comprising the trap units.
5. A chip manufacturing method based on a neural network is characterized in that: the neural network-based chip manufacturing method adopts the target layout designed by the neural network-based chip layout design method of any one of claims 1 and 2 to manufacture a digital integrated circuit chip.
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