CN101783324B - CMOS (complementary metal-oxide-semiconductor) transistor and manufacturing method thereof - Google Patents

CMOS (complementary metal-oxide-semiconductor) transistor and manufacturing method thereof Download PDF

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CN101783324B
CN101783324B CN2009100459740A CN200910045974A CN101783324B CN 101783324 B CN101783324 B CN 101783324B CN 2009100459740 A CN2009100459740 A CN 2009100459740A CN 200910045974 A CN200910045974 A CN 200910045974A CN 101783324 B CN101783324 B CN 101783324B
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grid
type source
drain region
cmos
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CN101783324A (en
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肖德元
季明华
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention discloses a CMOS (complementary metal-oxide-semiconductor) transistor and a manufacturing method thereof. The manufacturing method of the CMOS transistor comprises the following steps of: providing a semiconductor substrate, wherein the semiconductor substrate comprises n type silicon and p type silicon adjacent to the n type silicon; etching the semiconductor substrate, defining a p type source/drain electrode region on the n type silicon and defining an n type source/drain electrode region on the p type silicon; sequentially forming a grid dielectric layer and a grid electrode on the semiconductor substrate, wherein the grid electrode and the grid dielectric layer cross the p type source/drain electrode region and the n type source/drain electrode region; forming a p type lightly doped drain electrode in the p type source/drain electrode region at both sides of the grid electrode and forming an n type lightly doped drain electrode in the n type source/drain electrode region; forming two side walls at both sides of the grid electrode; and forming a p type source/drain electrode in the p type source/drain electrode region at both sides of the grid electrode and the side walls and forming an n type source/drain electrode in the n type source/drain electrode region. The invention improves the utilization ratio of the chip area and reduces the production cost.

Description

CMOS transistor and preparation method thereof
Technical field
The present invention relates to technical field of semiconductors, relate in particular to CMOS transistor and preparation method thereof.
Background technology
CMOS (CMOS) transistor is the elementary cell in the modem logic circuit; Wherein comprise PMOS and NMOS; And each PMOS (NMOS) transistor all is positioned on the impure well, and all is made up of the passage (Channel) between p type (n type) utmost point/drain region and source area and drain region in the substrate of grid (Gate) both sides.After the manufacture craft of CMOS advances to micron order; Because the passage between the source/drain regions shortens thereupon, so can produce short-channel effect (ShortChannel Effect) and hot carrier's effect (Hot Carrier Effect) and and then cause element to operate.Therefore; Can adopt lightly doped drain (Lightly Doped Drain in the source/drain design of the CMOS of micron order and following manufacture craft; LDD) structure, that is the part formation degree of depth in abutting connection with source/drain regions is more shallow below grid structure, and the dopant profile doped regions identical with source/drain regions; Reducing the electric field of channel region, and and then avoid the generation of short-channel effect and hot carrier's effect.
The existing transistorized technology of CMOS such as Fig. 1 to Fig. 5 of forming; With reference to figure 1; Semiconductor substrate 100 at first is provided; Comprise n type dopant well 102, p type dopant well 104 and isolation structure 106 in the said Semiconductor substrate 100, wherein be positioned at n type dopant well 102 tops and isolation structure 106 adjacent areas are PMOS active area 108, being positioned at p type dopant well 104 tops and isolation structure 106 adjacent areas is NMOS active area 110.Then on PMOS active area 108 and NMOS active area 110, form gate dielectric layer 112, on the gate dielectric layer 112 of PMOS active area 108 and NMOS active area 110, form grid 114a, 114b again; On Semiconductor substrate 100, form silicon nitride layer 116 with chemical vapour deposition technique.
With reference to figure 2,, form skew clearance wall 116a in grid 114a, 114b both sides with dry etching method etch silicon nitride layer 116.
With reference to figure 3; Next on NMOS active area 110, form first photoresist layer 118; Be mask with grid 114a and photoresist layer 118 again, in the Semiconductor substrate 100 of PMOS active area 108, inject p type ion, in the n type impure well 102 of grid 114a both sides, form p type lightly doped drain 120.
Please with reference to Fig. 4, on PMOS active area 108, forming second photoresist layer 122, is that mask injects n type ion with grid 114b and photoresist layer 122 again, in the p type impure well 104 of grid 114b both sides, forms n type low-doped drain 124.
Please with reference to Fig. 5, in the sidewall formation side wall 126 of grid 114a, 114b, to form grid structure 127a, 127b; Then on NMOS active area 110, forming the 3rd photoresist layer (not shown), is that mask injects p type ion with grid structure 127a and the 3rd photoresist layer again, in the n type impure well 102 of grid structure 128a both sides, forms p type source/drain regions 128a; On PMOS active area 108, forming the 4th photoresist layer (not shown), is that mask injects n type ion with grid structure 127b and the 4th photoresist layer again, in the p type impure well 104 of grid structure 128b both sides, forms n type source/drain regions 128b.
With reference to figure 6, Fig. 6 is the vertical view of Fig. 5, and the nmos pass transistor 140 in the existing CMOS transistor is linearly arranged with PMOS transistor 130 and formed the cmos device structure of elongate in shape, and its structure is single, underaction in design; And along with the integrated level of semiconductor device is increasingly high, the leeway that its volume diminishes thereupon is more and more littler, can't satisfy the technological development demand.
Summary of the invention
The problem that the present invention solves provides a kind of CMOS transistor and preparation method thereof, prevents that the transistorized structure of CMOS is single, and volume can't continue to diminish.
For addressing the above problem, the present invention provides a kind of CMOS transistorized manufacture method, comprising: Semiconductor substrate is provided, and said Semiconductor substrate comprises n type silicon, the p type silicon adjacent with n type silicon; The etching semiconductor substrate defines p type source/drain region in n type silicon, in p type silicon, define n type source/drain region; On Semiconductor substrate, form gate dielectric layer and grid successively, said grid and gate dielectric layer are across p type source/drain region and n type source/drain region; In the p of grid both sides type source/drain region, form p type lightly doped drain, in n type source/drain region, form n type lightly doped drain; Form side wall in the grid both sides; In the p type source/drain region of grid and side wall both sides, form p type source/drain electrode, in n type source/drain region, form n type source/drain electrode.
Optional, said grid material is polysilicon, metal or metal silicide.The width of said grid is 10nm～100nm.
Optional, the ion that formation p type lightly doped drain is injected is the boron ion.Said boron ion concentration is 10 18Cm -3～10 19Cm -3, dosage is 10 13Cm -2～10 15Cm -2, energy is 500eV～2000eV.
Optional, the ion that formation n type lightly doped drain is injected is phosphonium ion or arsenic ion.Said phosphonium ion or arsenic ion concentration are 10 18Cm -3～10 19Cm -3, dosage is 10 13Cm -2～10 15Cm -2, energy is 10KeV～100KeV.
Optional, forming the p type ion that the source/drain electrode is injected is the boron ion.Said boron ion concentration is 10 19Cm -3～10 21Cm -3, dosage is 10 15Cm -2～10 16Cm -2, energy is 1KeV～5KeV.
Optional, forming the n type ion that the source/drain electrode is injected is phosphonium ion or arsenic ion.Said phosphonium ion or arsenic ion concentration are 10 19Cm -3～10 21Cm -3, dosage is 10 15Cm -2～10 16Cm -2, energy is 50KeV～200KeV.
The present invention also provides a kind of CMOS transistor, comprising: Semiconductor substrate, said Semiconductor substrate comprise n type silicon, the p type silicon adjacent with n type silicon; Be arranged in the p type source/drain region of n type silicon, be positioned at the n type source/drain region of p type silicon; Be positioned on the Semiconductor substrate and across the gate dielectric layer of p type source/drain region and n type source/drain region; Be positioned at the grid on the gate dielectric layer; Be positioned at the p type lightly doped drain and the p type source/drain electrode of the p type source/drain region of grid both sides; Be positioned at the n type lightly doped drain and the n type source/drain electrode of the n type source/drain region of grid both sides; Be positioned at the side wall of grid both sides.
Compared with prior art; The present invention has the following advantages: PMOS transistor AND gate nmos pass transistor common grid, and the transistorized volume energy of CMOS is further reduced, satisfy the ever-increasing trend of semiconductor device integrated level; Improve the utilance of chip area, make layout more flexible.
In addition,, shortened the production cycle, reduced production cost because PMOS transistor AND gate nmos pass transistor common grid has reduced photoetching process and etching technics step.
Description of drawings
Fig. 1 to Fig. 5 is that existing technology forms the transistorized sketch map of CMOS;
Fig. 6 is the vertical view of Fig. 5;
Fig. 7 is that the present invention forms the transistorized embodiment flow chart of CMOS;
Fig. 8 to Figure 13 is that the present invention forms the transistorized embodiment sketch map of CMOS;
Figure 13 a is the profile of Figure 13 along the A-A direction;
Figure 13 b is the profile of Figure 13 along the B-B direction.
Embodiment
Fig. 7 is that the present invention forms the transistorized embodiment flow chart of CMOS.As shown in Figure 7, execution in step S1 provides Semiconductor substrate, and said Semiconductor substrate comprises n type silicon, the p type silicon adjacent with n type silicon; Execution in step S2, the etching semiconductor substrate defines p type source/drain region in n type silicon, in p type silicon, define n type source/drain region; Execution in step S3 forms gate dielectric layer and grid successively on Semiconductor substrate, said grid and gate dielectric layer are across p type source/drain region and n type source/drain region; Execution in step S4 forms p type lightly doped drain in the p of grid both sides type source/drain region, in n type source/drain region, form n type lightly doped drain; Execution in step S5 forms side wall in the grid both sides; Execution in step S6 forms p type source/drain electrode in the p type source/drain region of grid and side wall both sides, in n type source/drain region, form n type source/drain electrode.
The CMOS transistor that forms based on above-mentioned execution mode comprises: Semiconductor substrate, said Semiconductor substrate comprise n type silicon, the p type silicon adjacent with n type silicon; Be arranged in the p type source/drain region of n type silicon, be positioned at the n type source/drain region of p type silicon; Be positioned on the Semiconductor substrate and across the gate dielectric layer of p type source/drain region and n type source/drain region; Be positioned at the grid on the gate dielectric layer; Be positioned at the p type lightly doped drain and the p type source/drain electrode of the p type source/drain region of grid both sides; Be positioned at the n type lightly doped drain and the n type source/drain electrode of the n type source/drain region of grid both sides; Be positioned at the side wall of grid both sides.
PMOS transistor AND gate nmos pass transistor common grid of the present invention further reduces the transistorized volume energy of CMOS, satisfies the ever-increasing trend of semiconductor device integrated level, improves the utilance of chip area, makes layout more flexible.In addition,, shortened the production cycle, reduced production cost because PMOS transistor AND gate nmos pass transistor common grid has reduced photoetching process and etching technics step.
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
As shown in Figure 8; Semiconductor substrate 200 is provided; Said Semiconductor substrate 200 can be silicon or silicon-on-insulator (SO1), the preferred silicon-on-insulator of present embodiment, and it comprises silicon base 201, is positioned at the oxide layer 202 on the silicon base 201 and is positioned at the top layer silicon 203 on the oxide layer 202.On top layer silicon 203, apply first photoresist layer (not shown), adopt photoetching process, on first photoresist layer, define NMOS active area 208; With first photoresist layer is mask, and doped p type ion in the top layer silicon 203 of NMOS active area 208 forms p type silicon 204.After ashing method and wet etching method are removed first photoresist layer, on top layer silicon 203, apply second photoresist layer (not shown), after exposure imaging technology, on second photoresist layer, define PMOS active area 210; With second photoresist layer is mask, in the top layer silicon 203 of PMOS active area 210, injects n type ion, forms n type silicon 206.
In the present embodiment, the doped p type ion is boron ion or indium ion, and wherein the concentration of boron ion or indium ion is 10 17Cm -3～10 18Cm -3, dosage is 10 12Cm -2～10 14Cm -2, energy is 100KeV～200KeV.The Doped n-type ion is phosphonium ion or arsenic ion, and its concentration is 10 17Cm -3～10 18Cm -3, dosage is 10 12Cm -2～10 14Cm -2, energy is 100KeV～300KeV.
As shown in Figure 9, after ashing method and wet etching method are removed second photoresist layer, on top layer silicon, form the 3rd photoresist layer (not shown), adopt photoetching process, define lightly doped drain figure and source/drain electrode figure; With the 3rd photoresist layer is mask, and the etching top layer silicon forms p type source/drain region 206a to exposing oxide layer 202 at PMOS active area 210, forms n type source/drain region 204a at NOMS active area 208.
Shown in figure 10, ashing method and wet etching method are removed the 3rd photoresist layer; On oxide layer 202, p type source/drain region 206a and n type source/drain region 204a, form gate dielectric layer 212; The material of gate dielectric layer 212 can be silica, silica-silicon-nitride and silicon oxide etc., and the method for said formation gate dielectric layer 212 is thermal oxidation method or chemical vapour deposition technique or physical vaporous deposition etc.
Continuation on grid interlayer 212, form the grid 214 across p type source/drain region 206a and n type source/drain region 204a, and grid 214 is positioned at the mid portion of p type source/drain region 206a and n type source/drain region 204a with reference to Figure 10; The material of said grid 214 can be polysilicon, metal or metal silicide.With the material is that polysilicon is an example; Concrete formation technology is following: on gate dielectric layer 212, forming polysilicon layer with chemical vapour deposition (CVD) or plasma enhanced chemical vapor deposition method; Spin coating patterning photoresist layer (not shown) on polysilicon layer defines gate patterns again, is mask with the patterning photoresist layer; Etch polysilicon layer and gate dielectric layer 212 form grid 214 to exposing the top layer silicon of oxide layer 202 with p type source/drain region 206a and n type source/drain region 204a.
Another embodiment; After forming grid 214; Can also use chemical vapour deposition technique or plasma enhanced chemical vapor deposition method or physical vaporous deposition on oxide layer 202 and grid 214, to form thickness is the silicon nitride layer of 100 dusts～150 dusts, in order to form follow-up skew clearance wall; With the etch-back technics etch silicon nitride layer of dry etching method, form the skew clearance wall in grid 214 both sides, the effect of said skew clearance wall is the short-channel effect that prevents that source electrode from causing with drain electrode generation short circuit.
Shown in figure 11, in n type source/drain region 204a formation n type lightly doped drain 216b.Concrete technology is following: form the 4th photoresist layer (not shown) at PMOS active area 210; With the 4th photoresist layer and grid 214 is mask; In the n of NMOS active area 208 type source/drain region 204a, inject n type ion, in the n type source/drain region 204a of grid 214 both sides, form n type lightly doped drain 216b.
In the present embodiment, the ion that formation n type lightly doped drain 216b is injected is phosphonium ion or arsenic ion.Said phosphonium ion or arsenic ion concentration are 10 18Cm -3～10 19Cm -3, dosage is 10 13Cm -2～10 15Cm -2, energy is 10KeV～100KeV.
Continuation is with reference to Figure 11, remove the 4th photoresist layer of PMOS active area 210 with ashing method after, in p type source/drain region 206a forms p type lightly doped drain 216a.Concrete technology is following: form the 5th photoresist layer (not shown) in NMOS active area 208; With the 5th photoresist layer and grid 214 is mask, in the p of PMOS active area 210 type source/drain region 206a, injects p type ion, in the p type source/drain region 206a of grid 214 both sides, forms p type lightly doped drain 216a.
In the present embodiment, the ion that formation p type lightly doped drain 216a is injected is the boron ion.Said boron ion concentration is 10 18Cm -3～10 19Cm -3, dosage is 10 13Cm -2～10 15Cm -2, energy is 500eV～2000eV.
Next, remove the 5th photoresist layer of NMOS active area 208 with ashing method.
Shown in figure 12, form side wall 218 in grid 214 both sides.Concrete technology is following: on whole Semiconductor substrate, form mask layer (not shown) with chemical vapour deposition technique, be used to form follow-up side wall, the material of said mask layer can be silica, silica-silicon nitride or silica-silicon-nitride and silicon oxide etc.; With the etch-back technics etch mask layer of dry etching method, form side wall 218, in order to protection grid 214.
Shown in Figure 13, Figure 13 a, Figure 13 b, in n type source/drain region 204a formation n type source/drain electrode 220b.Concrete technology is following: then on PMOS active area 210, form the 6th photoresist layer (not shown); Be mask with the 6th photoresist layer, grid 214 and side wall 218 again; In the n of NMOS active area 208 type source/drain region 204a, inject n type ion, in the n type source/drain region 204a of grid 214 both sides, form n type source/drain electrode 220b.
In the present embodiment, forming the n type ion that the source/drain electrode 220b is injected is phosphonium ion or arsenic ion.Said phosphonium ion or arsenic ion concentration are 10 19Cm -3～10 21Cm -3, dosage is 10 15Cm -2～10 16Cm -2, energy is 50KeV～200KeV.
Continue behind the 6th photoresist layer with ashing method removal PMOS active area 210, to form p type lightly doped drain 220a at p type lightly doped drain and p type source/drain region 206a with reference to like Figure 13, Figure 13 a, Figure 13 b.Concrete technology is following: on NMOS active area 208, form the 7th photoresist layer (not shown); With the 7th photoresist layer, grid 214 and side wall 218 is mask; In the p of PMOS active area 210 type lightly doped drain and p type source/drain region 206a, inject p type ion, formation p type source/drain electrode 220a in the p type lightly doped drain of grid 214 both sides and p type source/drain region 206a.
In the present embodiment, forming the p type ion that the source/drain electrode 220a is injected is the boron ion.Said boron ion concentration is 10 19Cm -3～10 21Cm -3, dosage is 10 15Cm -2～10 16Cm -2, energy is 1KeV～5KeV.
CMOS transistor based on the foregoing description formation; Comprise: Semiconductor substrate 200; Said Semiconductor substrate 200 comprises silicon base 201, is positioned at the oxide layer 202 on the silicon base 201 and is positioned at n type lightly doped drain and n type source/drain region 204a and p type lightly doped drain and the p type source/drain region 206a on the oxide layer 202, and said n type lightly doped drain and n type source/drain region 204a and p type lightly doped drain and p type source/drain region 206a are adjacent; Gate dielectric layer 212 is positioned on oxide layer 202 and n type lightly doped drain and n type source/drain region 204a and p type lightly doped drain and the p type source/drain region 206a; Grid 214 is positioned on the gate dielectric layer 212 and across n type lightly doped drain and n type source/drain region 204a and p type lightly doped drain and p type source/drain region 206a; N type lightly doped drain 216b is positioned at the n type lightly doped drain and the n type source/drain region 204a of grid 214 both sides; P type lightly doped drain 216a is positioned at the p type lightly doped drain and the p type source/drain region 206a of grid 214 both sides; Side wall 218 is positioned at grid 214 both sides; The skew clearance wall 216a both sides of PMOS active area 208, and be positioned at NMOS active area 210 grid 214b both sides; N type source/drain electrode 220b is positioned at the n type lightly doped drain and the n type source/drain region 204a of grid 214 and side wall 218 both sides; P type source/drain electrode 220a is positioned at the p type lightly doped drain and the p type source/drain region 206a of grid 214 and side wall 218 both sides.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.

Claims (12)

1. the transistorized manufacture method of CMOS is characterized in that, comprising:
Semiconductor substrate is provided, and said Semiconductor substrate comprises n type silicon, the p type silicon adjacent with n type silicon;
The etching semiconductor substrate defines p type source/drain region in n type silicon, in p type silicon, define n type source/drain region;
On Semiconductor substrate, form gate dielectric layer and grid successively, said grid and gate dielectric layer are across p type source/drain region and n type source/drain region;
Form the skew clearance wall in the grid both sides;
In the p of grid both sides type source/drain region, form p type lightly doped drain, in n type source/drain region, form n type lightly doped drain;
Form side wall in the grid both sides;
In the p type source/drain region of grid and side wall both sides, form p type source/drain electrode, in n type source/drain region, form n type source/drain electrode.
2. according to the transistorized manufacture method of the said CMOS of claim 1, it is characterized in that said grid material is polysilicon, metal or metal silicide.
3. according to the transistorized manufacture method of the said CMOS of claim 2, it is characterized in that the width of said grid is 10nm～100nm.
4. according to the transistorized manufacture method of the said CMOS of claim 1, it is characterized in that the ion that formation p type lightly doped drain is injected is the boron ion.
5. according to the transistorized manufacture method of the said CMOS of claim 4, it is characterized in that said boron ion concentration is 10 18Cm -3～10 19Cm -3, dosage is 10 13Cm -2～10 15Cm -2, energy is 500eV～2000eV.
6. according to the transistorized manufacture method of the said CMOS of claim 1, it is characterized in that the ion that formation n type lightly doped drain is injected is phosphonium ion or arsenic ion.
7. according to the transistorized manufacture method of the said CMOS of claim 6, it is characterized in that said phosphonium ion or arsenic ion concentration are 10 18Cm -3～10 19Cm -3, dosage is 10 13Cm -2～10 15Cm -2, energy is 10KeV～100KeV.
8. according to the transistorized manufacture method of the said CMOS of claim 1, it is characterized in that forming the p type ion that the source/drain electrode is injected is the boron ion.
9. the transistorized manufacture method of said according to Claim 8 CMOS is characterized in that said boron ion concentration is 10 19Cm -3～10 21Cm -3, dosage is 10 15Cm -2～10 16Cm -2, energy is 1KeV～5KeV.
10. according to the transistorized manufacture method of the said CMOS of claim 1, it is characterized in that forming the n type ion that the source/drain electrode is injected is phosphonium ion or arsenic ion.
11., it is characterized in that said phosphonium ion or arsenic ion concentration are 10 according to the transistorized manufacture method of the said CMOS of claim 10 19Cm -3～10 21Cm -3, dosage is 10 15Cm -2～10 16Cm -2, energy is 50KeV～200KeV.
12. a CMOS transistor is characterized in that, comprising: Semiconductor substrate, said Semiconductor substrate comprise n type silicon, the p type silicon adjacent with n type silicon; Be arranged in the p type source/drain region of n type silicon, be positioned at the n type source/drain region of p type silicon; Be positioned on the Semiconductor substrate and across the gate dielectric layer of p type source/drain region and n type source/drain region; Be positioned at the grid on the gate dielectric layer; Be positioned at the p type lightly doped drain and the p type source/drain electrode of the p type source/drain region of grid both sides; Be positioned at the n type lightly doped drain and the n type source/drain electrode of the n type source/drain region of grid both sides; Be positioned at the skew clearance wall of grid both sides; Be positioned at the side wall on the grid both sides skew clearance wall.
CN2009100459740A 2009-01-19 2009-01-19 CMOS (complementary metal-oxide-semiconductor) transistor and manufacturing method thereof Expired - Fee Related CN101783324B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1893093A (en) * 2005-07-08 2007-01-10 精工爱普生株式会社 Semiconductor device and manufacturing method thereof
CN101030602A (en) * 2007-04-06 2007-09-05 上海集成电路研发中心有限公司 MOS transistor for decreasing short channel and its production

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1893093A (en) * 2005-07-08 2007-01-10 精工爱普生株式会社 Semiconductor device and manufacturing method thereof
CN101030602A (en) * 2007-04-06 2007-09-05 上海集成电路研发中心有限公司 MOS transistor for decreasing short channel and its production

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