CN101783322B - CMOS (complementary metal-oxide-semiconductor) transistor and manufacturing method thereof - Google Patents
CMOS (complementary metal-oxide-semiconductor) transistor and manufacturing method thereof Download PDFInfo
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- CN101783322B CN101783322B CN2009100459666A CN200910045966A CN101783322B CN 101783322 B CN101783322 B CN 101783322B CN 2009100459666 A CN2009100459666 A CN 2009100459666A CN 200910045966 A CN200910045966 A CN 200910045966A CN 101783322 B CN101783322 B CN 101783322B
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Abstract
The invention discloses a CMOS (complementary metal-oxide-semiconductor) transistor and a manufacturing method thereof. The CMOS transistor comprises a semiconductor substrate, a silicon-containing layer positioned on a top layer silicon, a grid dielectric layer, a grid electrode positioned on the gird dielectric layer, a p type lightly doped drain electrode positioned in the silicon-containing layer at both sides of the grid electrode, an n type lightly doped drain electrode positioned in the top layer silicon at both sides of the grid electrode, side walls positioned at both sides of the grid electrode, side walls positioned at both sides of the silicon-containing layer and part of the top layer silicon, a p type source/drain electrode positioned in the silicon-containing layer at both sides of the grid electrode and the side walls and an n type source/drain electrode in the top layer silicon at both sides of the grid electrode and the side walls, wherein the semiconductor substrate contains a silicon substrate, an oxidation layer positioned on the silicon substrate and the top layer silicon positioned on the oxidation layer, the electric conduction type of the silicon-containing layer is opposite to that of the top layer silicon, and the grid dielectric layer is positioned in the center of the top layer silicon and the silicon-containing layer and encircles the top layer silicon and the silicon-containing layer. The invention improves the utilization ratio of the chip area and reduces the production cost.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to CMOS transistor and preparation method thereof.
Background technology
CMOS (CMOS) transistor is the elementary cell in the modem logic circuit; Wherein comprise PMOS and NMOS; And each PMOS (NMOS) transistor all is positioned on the impure well, and all is made up of the passage (Channel) between p type (n type) utmost point/drain region and source area and drain region in the substrate of grid (Gate) both sides.After the manufacture craft of CMOS advances to micron order; Because the passage between the source/drain regions shortens thereupon, so can produce short-channel effect (ShortChannel Effect) and hot carrier's effect (Hot Carrier Effect) and and then cause element to operate.Therefore; Can adopt lightly doped drain (Lightly Doped Drain in the source/drain design of the CMOS of micron order and following manufacture craft; LDD) structure, that is the part formation degree of depth in abutting connection with source/drain regions is more shallow below grid structure, and the dopant profile doped regions identical with source/drain regions; Reducing the electric field of channel region, and and then avoid the generation of short-channel effect and hot carrier's effect.
The existing transistorized technology of CMOS such as Fig. 1 to Fig. 5 of forming; With reference to figure 1; Semiconductor substrate 100 at first is provided; Comprise n type dopant well 102, p type dopant well 104 and isolation structure 106 in the said Semiconductor substrate 100, wherein be positioned at n type dopant well 102 tops and isolation structure 106 adjacent areas are PMOS active area 108, being positioned at p type dopant well 104 tops and isolation structure 106 adjacent areas is NMOS active area 110.Then on PMOS active area 108 and NMOS active area 110, form gate dielectric layer 112, on the gate dielectric layer 112 of PMOS active area 108 and NMOS active area 110, form grid 114a, 114b again; On Semiconductor substrate 100, form silicon nitride layer 116 with chemical vapour deposition technique.
With reference to figure 2,, form skew clearance wall 116a in grid 114a, 114b both sides with dry etching method etch silicon nitride layer 116.
With reference to figure 3; Next on NMOS active area 110, form first photoresist layer 118; Be mask with grid 114a and photoresist layer 118 again, in the Semiconductor substrate 100 of PMOS active area 108, inject p type ion, in the n type impure well 102 of grid 114a both sides, form p type lightly doped drain 120.
Please with reference to Fig. 4, on PMOS active area 108, forming second photoresist layer 122, is that mask injects n type ion with grid 114b and photoresist layer 122 again, in the p type impure well 104 of grid 114b both sides, forms n type low-doped drain 124.
Please with reference to Fig. 5, in the sidewall formation side wall 126 of grid 114a, 114b, to form grid structure 127a, 127b; Then on NMOS active area 110, forming the 3rd photoresist layer (not shown), is that mask injects p type ion with grid structure 127a and the 3rd photoresist layer again, in the n type impure well 102 of grid structure 128a both sides, forms p type source/drain regions 128a; On PMOS active area 108, forming the 4th photoresist layer (not shown), is that mask injects n type ion with grid structure 127b and the 4th photoresist layer again, in the p type impure well 104 of grid structure 128b both sides, forms n type source/drain regions 128b.
With reference to figure 6, Fig. 6 is the vertical view of Fig. 5, and the nmos pass transistor 140 in the existing cmos device is linearly arranged with PMOS transistor 130 and formed the cmos device structure of elongate in shape, and its structure is single, underaction in design; And along with the integrated level of semiconductor device is increasingly high, the leeway that its volume diminishes thereupon is more and more littler, can't satisfy the technological development demand.
Summary of the invention
The problem that the present invention solves provides a kind of CMOS transistor and preparation method thereof, prevents that the transistorized structure of CMOS is single, and volume can't continue to diminish.
For addressing the above problem, the present invention provides a kind of CMOS transistorized manufacture method, comprising: Semiconductor substrate is provided, and said semiconductor substrate contains silicon base, is positioned at the oxide layer on the silicon base and is positioned at the top layer silicon on the oxide layer; On top layer silicon, form silicon-containing layer with its conductivity type opposite; Etching silicon-containing layer and top layer silicon, definition n type source/drain region; The etching oxidation layer forms the gate patterns district, and below the n in gate patterns district type source/drain region, forms through hole, the suprabasil partial oxidation layer of a residual silicon in the through hole; Form gate dielectric layer and grid successively around top layer silicon and silicon-containing layer in the gate patterns district; Etching silicon-containing layer and part top layer silicon, definition p type source/drain region; In the top layer silicon of n type source/drain region, grid both sides, form n type lightly doped drain, in the silicon-containing layer of p type source/drain region, grid both sides, form p type lightly doped drain; In the grid both sides, silicon-containing layer and silicon layer both sides, part top form side wall; In the top layer silicon of grid and n type source/drain region, side wall both sides, form n type source/drain electrode, in the silicon-containing layer of grid and p type source/drain region, side wall both sides, form p type source/drain electrode.
Optional, said silicon-containing layer material is a germanium silicon.The method that forms silicon-containing layer is an epitaxial growth method.The thickness of said silicon-containing layer is 10nm～100nm.
Optional, the ion that formation p type lightly doped drain is injected is the boron ion.Said boron ion concentration is 10
18Cm
-3～10
19Cm
-3, dosage is 10
13Cm
-2～10
15Cm
-2, energy is 500eV～2000eV.
Optional, the ion that formation n type lightly doped drain is injected is phosphonium ion or arsenic ion.Said phosphonium ion or arsenic ion concentration are 10
18Cm
-3～10
19Cm
-3, dosage 10
13Cm
-2～10
15Cm
-2, energy 100KeV～200KeV.
Optional, forming the p type ion that the source/drain electrode is injected is the boron ion.Said boron ion concentration is 10
19Cm
-3～10
21Cm
-3, dosage is 10
15Cm
-2～10
16Cm
-2, energy is 1KeV～5KeV.
Optional, forming the n type ion that the source/drain electrode is injected is phosphonium ion or arsenic ion.Said phosphonium ion or arsenic ion concentration are 10
19Cm
-3～10
21Cm
-3, dosage is 10
15Cm
-2～10
16Cm
-2, energy is 50KeV～200KeV.
The present invention also provides a kind of CMOS transistor, comprising: Semiconductor substrate, said semiconductor substrate contain silicon base, are positioned at the oxide layer on the silicon base and are positioned at the top layer silicon on the oxide layer; Be positioned at the silicon-containing layer on the top layer silicon, its conduction type is opposite with the top silicon layer; Be positioned at top layer silicon and silicon-containing layer central authorities and around the gate dielectric layer of top layer silicon and silicon-containing layer; Be positioned at the grid on the gate dielectric layer; Be positioned at the p type lightly doped drain of grid both sides silicon-containing layer; Be positioned at the n type lightly doped drain of grid both sides top layer silicon; Be positioned at the side wall of grid both sides; Be positioned at the side wall of silicon-containing layer and part top layer silicon both sides; Be positioned at the p type source/drain electrode of grid and side wall both sides silicon-containing layer; Be positioned at the n type source/drain electrode of grid and side wall both sides top layer silicon.
Compared with prior art; The present invention has the following advantages: PMOS transistor AND gate nmos pass transistor becomes stacked structure; And common grid further reduces the transistorized volume energy of CMOS, satisfies the ever-increasing trend of semiconductor device integrated level; Improve the utilance of chip area, make layout more flexible.
In addition,, shortened the production cycle, reduced production cost because PMOS transistor AND gate nmos pass transistor common grid has reduced photoetching process and etching technics step.
Description of drawings
Fig. 1 to Fig. 5 is that existing technology forms the transistorized sketch map of CMOS;
Fig. 6 is the vertical view of Fig. 5;
Fig. 7 is that the present invention forms the transistorized embodiment flow chart of CMOS;
Fig. 8 to Figure 16 is that the present invention forms the transistorized embodiment sketch map of CMOS;
Figure 10 A is the stereogram of Figure 10;
Figure 11 A is the stereogram of Figure 11;
Figure 12 A is the stereogram of Figure 12.
Embodiment
Fig. 7 is that the present invention forms the transistorized embodiment flow chart of CMOS.As shown in Figure 7, execution in step S1 provides Semiconductor substrate, and said semiconductor substrate contains silicon base, is positioned at the oxide layer on the silicon base and is positioned at the top layer silicon on the oxide layer; Execution in step S2 forms the silicon-containing layer with its conductivity type opposite on top layer silicon; Execution in step S3, etching silicon-containing layer and top layer silicon, definition n type source/drain region; Execution in step S4, the etching oxidation layer forms the gate patterns district, and below the n in gate patterns district type source/drain region, forms through hole, the suprabasil partial oxidation layer of a residual silicon in the through hole; Execution in step S5 forms gate dielectric layer and grid around top layer silicon and silicon-containing layer successively in the gate patterns district; Execution in step S6, etching silicon-containing layer and part top layer silicon, definition p type source/drain region; Execution in step S7 forms n type lightly doped drain in the top layer silicon of n type source/drain region, grid both sides, in the silicon-containing layer of p type source/drain region, grid both sides, form p type lightly doped drain; Execution in step S8 is in the grid both sides, silicon-containing layer and silicon layer both sides, part top form side wall; Execution in step S9 forms n type source/drain electrode in the top layer silicon of grid and n type source/drain region, side wall both sides, in the silicon-containing layer of grid and p type source/drain region, side wall both sides, form p type source/drain electrode.
The CMOS transistor that forms based on above-mentioned execution mode comprises: Semiconductor substrate, said semiconductor substrate contain silicon base, are positioned at the oxide layer on the silicon base and are positioned at the top layer silicon on the oxide layer; Be positioned at the silicon-containing layer on the top layer silicon, its conduction type is opposite with the top silicon layer; Be positioned at top layer silicon and silicon-containing layer central authorities and around the gate dielectric layer of top layer silicon and silicon-containing layer; Be positioned at the grid on the gate dielectric layer; Be positioned at the p type lightly doped drain of grid both sides silicon-containing layer; Be positioned at the n type lightly doped drain of grid both sides top layer silicon; Be positioned at the side wall of grid both sides; Be positioned at the side wall of silicon-containing layer and part top layer silicon both sides; Be positioned at the p type source/drain electrode of grid and side wall both sides silicon-containing layer; Be positioned at the n type source/drain electrode of grid and side wall both sides top layer silicon.
PMOS transistor AND gate nmos pass transistor of the present invention becomes stacked structure, and common grid, and the transistorized volume energy of CMOS is further reduced, and satisfies the ever-increasing trend of semiconductor device integrated level, improves the utilance of chip area, makes layout more flexible.In addition,, shortened the production cycle, reduced production cost because PMOS transistor AND gate nmos pass transistor common grid has reduced photoetching process and etching technics step.
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
As shown in Figure 8, Semiconductor substrate 200 is provided, said Semiconductor substrate 200 is silicon-on-insulator (SOI), it comprises silicon base 201, is positioned at the oxide layer 202 on the silicon base 201 and is positioned at the top layer silicon 203 on the oxide layer 202; Doped with boron ion or indium ion in top layer silicon 203, the conduction type that makes top layer silicon 203 is the P type.
Continuation forms silicon-containing layer 204 with reference to figure 8 with chemical vapour deposition technique on top layer silicon 203, the material of said silicon-containing layer 204 is a germanium silicon, and thickness is 10nnm～100nm.
With reference to figure 9, etching silicon-containing layer 204 and top layer silicon 203, definition n type source/drain region.Concrete technology is following: on silicon-containing layer 204, form first photoresist layer (not shown) with spin-coating method, adopt photoetching process, photomask n type source/whole figure of drain electrode is transferred on first photoresist layer; Through developing process, the source/whole figure drains on first photoresist layer, to form the n type; With first photoresist layer is mask, to exposing oxide layer 202, forms n type source/drain region along the whole pattern etching silicon-containing layer of source/drain electrode 204 and top layer silicon 203.
Then, adopt ashing method or wet etching method to remove first photoresist layer.
Shown in Figure 10 and Figure 10 A, etching oxidation layer 202 forms the gate patterns district, and in the gate patterns district, the oxide layer of source/below, drain region is worn for 202 quarters, forms through hole 206.Concrete technology is following: on oxide layer 202 and n type source/drain region, form second photoresist layer (not shown), photoresist layer is carried out exposure imaging technology, the definition gate patterns; With second photoresist layer is mask, along gate patterns etching oxidation layer 202, forms the gate patterns district with the wet etching method, because the corrosivity of etching solution can be removed the oxide layer 202 of source/below, drain region, forms through hole 206.
In the present embodiment, etching oxidation layer 202 stays partial oxidation layer 202 on silicon base 201, forms the gate patterns district.The effect of residual fraction oxide layer 202 is that silicon base 201 is oxidized when preventing that the subsequent thermal oxidizing process from forming gate dielectric layer on silicon base 201.
In the present embodiment, the solution that wet etching adopts is buffered oxide etch agent BOE, and wherein concentration is 40% NH
4The ratio of F and 49% HF is 7: 1～20: 1.
Shown in Figure 11 and Figure 11 A; Continuation is a mask with second photoresist layer; In the gate patterns district, form around the top layer silicon 203 of n type source/drain region and the gate dielectric layer 208 of silicon-containing layer with thermal oxidation method, promptly on through hole 206 top layer silicon 203, also be formed with gate dielectric layer 208.Then, ashing method and wet etching method are removed photoresist layer.
In the present embodiment, the material of gate dielectric layer 208 is silicon dioxide or other high K medium material, and thickness is 1.2nm～3nm.
With reference to Figure 12 and Figure 12 A, after ashing method and wet etching method are removed second photoresist layer, on gate dielectric layer 208, form grid 210, said grid 210 is positioned at n type source/drain region central authorities, around top layer silicon 203 and silicon-containing layer 204.The concrete technology that forms grid 210 is following: on oxide layer 202, silicon-containing layer 204 and gate dielectric layer 208, form metal level; The material of said metal level is a titanium nitride; Thickness is 10nm～200nm, and the method that forms metal level is chemical vapour deposition technique or atomic layer deposition method.Spin coating the 3rd photoresist layer on metal level; Adopt photoetching technique, on the 3rd photoresist layer, form gate patterns; With the 3rd photoresist layer is mask, to exposing silicon-containing layer 204 and oxide layer 202, forms grid 210 along the gate patterns etching sheet metal.
Then, ashing method and wet etching method are removed the 3rd photoresist layer.
Another embodiment; After forming grid 210; Can also use chemical vapour deposition technique or plasma enhanced chemical vapor deposition method or physical vaporous deposition on oxide layer 202, silicon-containing layer 204 and grid 214, to form thickness is the silicon nitride layer of 100 dusts～150 dusts, in order to form follow-up skew clearance wall; With the etch-back technics etch silicon nitride layer of dry etching method, form the skew clearance wall in grid 210 both sides, the effect of said skew clearance wall is the short-channel effect that prevents that source electrode from causing with drain electrode generation short circuit.
Shown in figure 13, etching silicon-containing layer 204 and part top layer silicon 203 form p type source/drain region.Concrete technology is following: on silicon-containing layer 204, top layer silicon 203, oxide layer 202 and grid 210, form the 4th photoresist layer (not shown) with spin-coating method, adopt exposure technology, photomask p type source/whole figure of drain electrode is transferred on the 4th photoresist layer; Through developing process, the source/whole figure drains on the 4th photoresist layer, to form the p type; With the 4th photoresist layer is mask, along whole pattern etching silicon-containing layer 204 of source/drain electrode and part top layer silicon 203, forms p type source/drain region.Wherein remaining top layer silicon 203 thickness inject the degree of depth of ion greater than follow-up source/drain electrode.
With reference to Figure 14, be mask with grid 210, in the top layer silicon 203 of n type source/drain region, inject n type ion, form the n type lightly doped drain 212 of nmos pass transistor.
In the present embodiment, the ion that formation n type lightly doped drain 212 is injected is phosphonium ion or arsenic ion.Said phosphonium ion or arsenic ion concentration are 10
18Cm
-3～10
19Cm
-3, dosage 10
13Cm
-2～10
15Cm
-2, energy is 100KeV～200KeV.
Continuation is mask with reference to Figure 14 with grid 210, in the silicon-containing layer 204 of p type source/drain region, injects p type ion, forms the transistorized p type of PMOS lightly doped drain 214.
In the present embodiment, the ion that formation p type lightly doped drain 214 is injected is the boron ion.Said boron ion concentration is 10
18Cm
-3～10
19Cm
-3, dosage is 10
13Cm
-2～10
15Cm
-2, energy is 500eV～2000eV.
Then, carry out annealing process, make n type ion even diffused in top layer silicon 203, p type ion even diffused in silicon-containing layer 204.
Another embodiment can be a mask with grid 210 earlier, in p type source/drain region silicon-containing layer 204, injects p type ion, forms the transistorized p type of PMOS lightly doped drain 214.Then, be mask with grid 210 again, in n type source/drain region top layer silicon 203, inject n type ion, form the n type lightly doped drain 212 of nmos pass transistor.
Shown in figure 15, the silicon-containing layer 204 after grid 210 and etching forms side wall 220 with part top layer silicon 203 both sides.Concrete technology is following: on whole Semiconductor substrate, form mask layer (not shown) with chemical vapour deposition technique, be used to form follow-up side wall, the material of said mask layer can be silica, silica-silicon nitride or silica-silicon-nitride and silicon oxide etc.; Etch-back technics etch mask layer with the dry etching method; Form side wall 220; In order to protection grid 210; The effect that forms side wall 220 in silicon-containing layer 204 and part top layer silicon 203 both sides be in follow-up source/when the drain region forms metal silicide contact layer, can be with n type source/drain electrode and p type source/drain electrode isolation.
Shown in figure 16, be mask with grid 210 with side wall 220, in n type source/drain region top layer silicon 203, inject n type ion, form the n type source/drain electrode 216 of nmos pass transistor.
In the present embodiment, forming the n type ion that the source/drain electrode 216 is injected is phosphonium ion or arsenic ion.Said phosphonium ion or arsenic ion concentration are 10
19Cm
-3～10
21Cm
-3, dosage is 10
15Cm
-2～10
16Cm
-2, energy is 50KeV～200KeV.
Continuation is mask with grid 210 with side wall 220 with reference to Figure 16, in p type source/drain region silicon-containing layer 204, injects p type ion, forms the transistorized p type of PMOS source/drain electrode 218.
In the present embodiment, forming the p type ion that the source/drain electrode 218 is injected is the boron ion.Said boron ion concentration is 10
19Cm
-3～10
21Cm
-3, dosage is 10
15Cm
-2～10
16Cm
-2, energy is 1KeV～5KeV.
Another embodiment can be mask with grid 210 with side wall 220 earlier, in p type source/drain region silicon-containing layer 204, injects p type ion, forms the transistorized p type of PMOS source/drain electrode 218.Then, be mask with grid 210 with side wall 220 again, in n type source/drain region top layer silicon 203, inject n type ion, form the n type source/drain electrode 216 of nmos pass transistor.
Based on the CMOS transistor that the foregoing description forms, comprising: Semiconductor substrate 200, said Semiconductor substrate 200 comprise silicon base 201, are positioned at the oxide layer 202 on the silicon base 201 and are positioned at the top layer silicon 203 on the oxide layer 202; Be positioned at the silicon-containing layer 204 on the top layer silicon 203,204 one-tenth n type source/drain region shapes of said top layer silicon 203 and silicon-containing layer, 204 one-tenth p type source/drain region shapes of part top layer silicon 203 and silicon-containing layer, and p type source/drain region is positioned on n type source/drain region; Gate dielectric layer 208 is positioned at top layer silicon 203 with silicon-containing layer 204 central authorities and around top layer silicon 203 and silicon-containing layer 204; Grid 210 is positioned on the gate dielectric layer 208; N type lightly doped drain 212 is positioned at the top layer silicon 203 of n type source/drain region, grid 210 both sides; P type lightly doped drain 214 is positioned at the silicon-containing layer 204 of p type source/drain region, grid 210 both sides; Side wall 220 is positioned at grid 210 both sides and silicon-containing layer 204 and part top layer silicon 203 both sides; N type source/drain electrode 216 is positioned at the top layer silicon 203 of grid 210 and n type source/drain region, side wall 220 both sides; P type source/drain electrode 218 is positioned at the silicon-containing layer 204 of grid 210 and p type source/drain region, side wall 220 both sides.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (13)
1. the transistorized manufacture method of CMOS is characterized in that, comprising:
Semiconductor substrate is provided, and said semiconductor substrate contains silicon base, is positioned at the oxide layer on the silicon base and is positioned at the top layer silicon on the oxide layer;
On top layer silicon, form silicon-containing layer with its conductivity type opposite;
Etching silicon-containing layer and top layer silicon, definition n type source/drain region;
The etching oxidation layer forms the gate patterns district, and below the n in gate patterns district type source/drain region, forms through hole, the suprabasil partial oxidation layer of a residual silicon in the through hole;
Form gate dielectric layer and grid successively around top layer silicon and silicon-containing layer in the gate patterns district;
Etching silicon-containing layer and part top layer silicon, definition p type source/drain region;
In the top layer silicon of n type source/drain region, grid both sides, form n type lightly doped drain, in the silicon-containing layer of p type source/drain region, grid both sides, form p type lightly doped drain;
In the grid both sides, silicon-containing layer and part top layer silicon both sides form side wall;
In the top layer silicon of grid and n type source/drain region, side wall both sides, form n type source/drain electrode, in the silicon-containing layer of grid and p type source/drain region, side wall both sides, form p type source/drain electrode.
2. according to the transistorized manufacture method of the said CMOS of claim 1, it is characterized in that said silicon-containing layer material is a germanium silicon.
3. according to the transistorized manufacture method of the said CMOS of claim 2, it is characterized in that the method that forms silicon-containing layer is an epitaxial growth method.
4. according to the transistorized manufacture method of the said CMOS of claim 3, it is characterized in that the thickness of said silicon-containing layer is 10nm～100nm.
5. according to the transistorized manufacture method of the said CMOS of claim 1, it is characterized in that the ion that formation p type lightly doped drain is injected is the boron ion.
6. according to the transistorized manufacture method of the said CMOS of claim 5, it is characterized in that said boron ion concentration is 10
18Cm
-3～10
19Cm
-3, dosage is 10
13Cm
-2～10
15Cm
-2, energy is 500eV～2000eV.
7. according to the transistorized manufacture method of the said CMOS of claim 1, it is characterized in that the ion that formation n type lightly doped drain is injected is phosphonium ion or arsenic ion.
8. according to the transistorized manufacture method of the said CMOS of claim 7, it is characterized in that said phosphonium ion or arsenic ion concentration are 10
18Cm
-3～10
19Cm
-3, dosage 10
13Cm
-2～10
15Cm
-2, energy is 100KeV～200KeV.
9. according to the transistorized manufacture method of the said CMOS of claim 1, it is characterized in that forming the p type ion that the source/drain electrode is injected is the boron ion.
10. according to the transistorized manufacture method of the said CMOS of claim 9, it is characterized in that said boron ion concentration is 10
19Cm
-3～10
21Cm
-3, dosage is 10
15Cm
-2～10
16Cm
-2, energy is 1KeV～5KeV.
11., it is characterized in that forming the n type ion that the source/drain electrode is injected is phosphonium ion or arsenic ion according to the transistorized manufacture method of the said CMOS of claim 1.
12., it is characterized in that said phosphonium ion or arsenic ion concentration are 10 according to the transistorized manufacture method of the said CMOS of claim 11
19Cm
-3～10
21Cm
-3, dosage is 10
15Cm
-2～10
16Cm
-2, energy is 50KeV～200KeV.
13. a CMOS transistor is characterized in that, comprising: Semiconductor substrate, said semiconductor substrate contain silicon base, are positioned at the oxide layer on the silicon base and are positioned at the top layer silicon on the oxide layer; Be positioned at the silicon-containing layer on the top layer silicon, its conduction type and top layer silicon are opposite; Be positioned at top layer silicon and silicon-containing layer central authorities and around the gate dielectric layer of top layer silicon and silicon-containing layer; Be positioned at the grid on the gate dielectric layer; Be positioned at the p type lightly doped drain of grid both sides silicon-containing layer; Be positioned at the n type lightly doped drain of grid both sides top layer silicon; Be positioned at the side wall of grid both sides, silicon-containing layer and part top layer silicon both sides; Be positioned at the p type source/drain electrode of grid and side wall both sides silicon-containing layer; Be positioned at the n type source/drain electrode of grid and side wall both sides top layer silicon.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| CN1906769A (en) * | 2004-01-22 | 2007-01-31 | 国际商业机器公司 | Vertical fin-fet mos devices |
| CN1969391A (en) * | 2004-06-12 | 2007-05-23 | 皇家飞利浦电子股份有限公司 | Semiconductor on insulator semiconductor device and method of manufacture |
-
2009
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| CN1906769A (en) * | 2004-01-22 | 2007-01-31 | 国际商业机器公司 | Vertical fin-fet mos devices |
| CN1969391A (en) * | 2004-06-12 | 2007-05-23 | 皇家飞利浦电子股份有限公司 | Semiconductor on insulator semiconductor device and method of manufacture |
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