CN101345195A - Method for manufacturing semiconductor element - Google Patents
Method for manufacturing semiconductor element Download PDFInfo
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- CN101345195A CN101345195A CNA2007101287460A CN200710128746A CN101345195A CN 101345195 A CN101345195 A CN 101345195A CN A2007101287460 A CNA2007101287460 A CN A2007101287460A CN 200710128746 A CN200710128746 A CN 200710128746A CN 101345195 A CN101345195 A CN 101345195A
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Abstract
The invention provides a manufacture method used for a semiconductor element, comprising the steps as follows: firstly, a substrate comprising a channel is provided; subsequently, by an isotropy mixing method, at least an impurity is mixed at the area in the substrate close to the side wall of the channel; subsequently, a grid dielectric layer is formed on the side wall of the channel and a grid electrode is formed in the channel; furthermore, the grid electrode is protruded from the surface of the substrate.
Description
Technical field
The present invention is relevant for a kind of manufacture method of semiconductor element, and particularly relevant for a kind of manufacture method of memory component.
Background technology
Mos field effect transistor (Metal-Oxide-Semiconductor FieldEffect Transistors, hereinafter to be referred as MOSFET) be considerable a kind of basic electronic component in integrated circuit technique, it is by three kinds of basic materials, and promptly compositions such as metal conductor layer, oxide skin(coating) and semiconductor layer are positioned at the suprabasil gridistor of semiconductor.In addition, comprised that also two are positioned at the gridistor both sides, and the electrical doped region opposite with the semiconductor-based end, source electrode and drain electrode be called.When making gridistor at present, metal conducting layer is many to be made of jointly polysilicon (Polysilicon) that mixes and metal, and this structure is called multi-crystal silicification metal (Polycide) again.Oxide skin(coating) many by the formed silica of thermal oxidation method as grid oxic horizon.In addition, the sidewall of grid many with silicon nitride as sept (spacer).
Though above-mentioned traditional MOSFET is widely used for a long time, yet, along with the raising that semiconductor technology requires integration, traditional metal oxide semiconductor field effect is answered the also reduction relatively of transistor (MOSFET) size and channel length (channel length) thereof.When being reduced to, the channel length of MOSFET element is lower than 100nm, just easy during its running because of source/drain and the interaction of raceway groove therebetween, and then influenced the control ability of grid to the On/Off state of its raceway groove, and further cause short-channel effect (short channel effects below can be called for short SCE).But, be necessary at MOSFET in element downsizing process, to seek the road of improvement for the control ability of its grid groove On/Off state in fact for development that makes the downsizing of MOSFET fit dimension and the demand that improves integrated level.Therefore, now developed the transistor that the on-plane surface grid structure, for example step gate (step gate) transistor, recess channel array transistor (Recess channel array transistor, RCAT) or the spherical notch channel array transistor (Sphere shaped recess channel array transistor, SSRCAT).
Figure 1A and Figure 1B disclose a known techniques and carry out ion implantation technology at step gate transistor, adjust the technology of raceway groove starting voltage.At first, please refer to Figure 1A, a substrate 102 is provided, and a raceway groove is carried out in substrate 102 inject 103, form a channel doping district 104.Then, please refer to Figure 1B, form hierarchic structure, in substrate 102, form a gate dielectric 106 and a gate electrode 108, and inject substrate 102 formation source area 120 and drain regions 122 in substrate 102 surfaces.Yet shown in Figure 1B, the alloy that raceway groove injects can't be uniformly distributed in channel region, that is raceway groove injects formed channel doping district 104 concerning whole raceway groove, the non-constant of the uniformity.
In addition, the raceway groove injection technology of recess channel array transistor or spherical notch channel array transistor is carried out an ion implantation technology form a groove in substrate after, forms the channel doping district in groove.Same, this kind adopts ion implantation technology to carry out the technology of channel doping, and the alloy that raceway groove injects also can't be uniformly distributed in the channel region of recess channel array transistor, has the not good problem of the uniformity.
Summary of the invention
According to the problems referred to above, purpose of the present invention can make alloy be distributed in the raceway groove of non-planar transistor equably, and the good homogeneous degree is arranged for a kind of manufacture method of on-plane surface gridistor is provided.
The invention provides a kind of manufacture method of semiconductor element, may further comprise the steps.At first, provide the substrate that comprises a groove.Then, with an anisotropic method, the zone of at least one impurity adjacent trenches sidewall in substrate that mixes.Form on the sidewall of a gate dielectric in groove.Follow-up, form a gate electrode in groove, and outstanding substrate surface.
The invention provides a kind of manufacture method of semiconductor element.At first, provide the substrate that comprises a groove, form a doped layer on the sidewall of groove, then, the barrier layer that formation one covers doped layer at least carries out a heating process, makes the diffusion of impurities in the doped layer go into the zone of adjacent trenches sidewall in the substrate.Follow-up, form a gate dielectric on the sidewall of groove, form a gate electrode in groove, and outstanding substrate surface.
The invention provides a kind of manufacture method of semiconductor element.At first, provide a substrate, comprise the outer suprabasil mask layer of a groove and groove, substrate is placed a reative cell, feed an impurity gas, and heating makes the diffusion of impurities in the impurity gas go into the zone of adjacent trenches sidewall in the substrate.Follow-up, form on the sidewall of a gate dielectric in groove, form a gate electrode in groove, and outstanding substrate surface.
Description of drawings
Figure 1A and Figure 1B disclose a known techniques and carry out the technology that ion implantation technology is adjusted the raceway groove starting voltage at step gate transistor;
Fig. 2 A～2I discloses the manufacture method of one embodiment of the invention on-plane surface gridistor;
Fig. 3 A～3F discloses the manufacture method of another embodiment of the present invention on-plane surface gridistor;
Fig. 4 A～4D discloses the present invention's manufacture method of another embodiment on-plane surface gridistor again.
The main element symbol description
102～substrate; 104～channel doping district;
103～raceway groove injects; 106～gate dielectric;
108～gate electrode; 120～source area;
122～drain region; 202～substrate;
204～groove; 206～doped layer;
208～mask layer; 210～barrier layer;
212～channel doping district; 214～gate dielectric film;
214a～gate dielectric; 216～gate electrode layer;
216a～gate electrode; 218～hard mask layer;
218a～hard mask layer; 220～source area;
222～drain region; 301～impurity gas;
302～substrate; 304～mask layer;
305～groove; 306～channel doping district;
308～gate dielectric film; 308a～gate dielectric;
310～gate electrode layer; 310a～gate electrode;
312～hard mask layer; 312a～hard mask layer
314～source area; 316～drain region;
402～substrate; 405～doleiform groove;
406～mask layer; 407～source area;
409～drain region; 410～gate dielectric film;
410a～gate dielectric; 412～gate electrode layer;
412a～gate electrode; 413～hard mask layer;
413a～hard mask layer.
Embodiment
Below go through the manufacturing and the use of the preferred embodiment of the present invention, yet according to notion of the present invention, it can comprise or apply to technical scope widely.It is noted that embodiment is only in order to disclose the ad hoc approach of manufacturing of the present invention and use, not in order to limit the present invention.
Fig. 2 A～2I discloses the manufacture method of one embodiment of the invention on-plane surface gridistor.At first, please refer to Fig. 2 A, a substrate 202 is provided, carry out photoetching and etch process and in substrate 202, form a groove 204.Then, with for example Low Pressure Chemical Vapor Deposition (low pressure chemical vapordeposition, below can be called for short LPCVD) or deposition one doped layer 206 of medium-sized air pressure chemical vapour deposition technique (sub-atmosphericchemical vapor deposition below can be called for short SACVD) compliance in substrate 202 and in the groove 204.In the transistor of one embodiment of the invention NMOS, doping P shape alloy, for example Pyrex (BSG) in the doped layer 206.In the transistor of one embodiment of the invention PMOS, doped layer 206 is doping N shape alloy, for example arsenic silex glass (ASG) or phosphorosilicate glass (PSG).
Then, please refer to Fig. 2 B, form a photoresist on doped layer 206 with for example method of spin coating, and insert in the groove 204.Then, the technology of removing with for example plasma photoetching glue removes groove 204 part photoresist outward, and the photoresist in the reservation groove 204, at this part photoresist in groove 204 is called mask layer 208, please note, mask layer 208 is not limited to above-mentioned photoresist, and it can also be formed by other material that can be made for mask, for example nitride or other macromolecular material.
Next, please refer to Fig. 2 C, is mask with the mask layer in the groove 204 208, carries out an etch process, removes the part doped layer 206 outside the groove 204, makes doped layer 206 only keep the part that is arranged in groove 204.In an embodiment of the present invention, and the hydrofluoric acid that above-mentioned etch process cushioned for immersion (Buffered oxide etch, BOE)., remove mask layer 208,, can use plasma photoetching glue removal method to remove it if mask layer 208 is a photoresist thereafter.
Follow-up, please refer to Fig. 2 D, deposit a barrier layer 210 in substrate 202 with for example plasma auxiliary chemical vapor deposition method (PECVD), and the doped layer in the covering groove 204 206, to limit to the diffusion of impurity in the doped layer 206 in the follow-up heating process.In an embodiment of the present invention, barrier layer 210 be the tetraethoxy silicomethane (tetra-ethyl-ortho-silicate, TEOS).Next, please refer to Fig. 2 E, carry out a heating process, make the diffusion of impurities in the doped layer 206 go into the zone (channel doping district 212 as shown in the figure) of adjacent trenches 204 sidewalls in the substrate 202.The temperature that note that heating needs to determine according to the demand of product and technology, and the top in channel doping district 212 is no more than the bottom that subsequent technique is formed at source area and drain region.In one embodiment of the present invention, the temperature of this step heating is substantially between 650 ℃～850 ℃.Be different from known techniques, the impurity of present embodiment can be distributed in the zone (that is the transistorized raceway groove of on-plane surface grid structure) of adjacent trenches 204 sidewalls in the substrate 202 uniformly.
Then, please refer to Fig. 2 F, remove doped layer 206 and barrier layer 210, when doped layer 206 be Pyrex (boron silicon glass, BSG), phosphorosilicate glass (phosphorus silicon glass, PSG) or arsenic silex glass (arsenic silicon glass, ASG), when barrier layer 210 is tetraethoxy silicomethane (TEOS), because it is all oxide, the method of soaking BOE be can use, doped layer 206 and barrier layer 210 removed simultaneously.Follow-up, please refer to Fig. 2 G, form one for example the gate dielectric film 214 of silica in groove 204 and in the substrate 202.Form a gate electrode layer 216 on gate dielectric film 214, and insert in the groove 204.Grind gate electrode layer 216 in the hope of planarization with for example chemical mechanical milling method.Form one for example the hard mask layer 218 of silicon nitride on gate electrode layer 216.The technology of this part is not described in detail at this for haveing the knack of known to this skill personage.
Then, please refer to Fig. 2 H,, form patterning hard mask layer 218a with gold-tinted photoetching and etch process definition hard mask layer 218.Thereafter, please refer to Fig. 2 I, with patterning hard mask layer 218a is mask, carry out an anisotropic etch process, patterned gate electrode layer 216 and gate dielectric film 214, make to constitute and be arranged at the gate dielectric 214a on the sidewall in the groove 204 and be arranged in the groove 204 and the gate electrode 216a on outstanding substrate 202 surfaces.Follow-up, carry out an ion implantation technology, in gate electrode 216a substrate on two sides 202, form an one source pole district 220 and a drain region 222 respectively.
In the present embodiment, the doping of the channel region of on-plane surface grid is diffused in the substrate 202 by the doped layer 206 that is formed on groove 204 sidewalls, and impurity can be distributed in the transistorized raceway groove uniformly, can more effectively suppress short-channel effect.In addition, because short-channel effect reduces, the transistor of this embodiment made of the present invention has less leakage current, can increase hold time (the retention time) of dynamic random processing memory (DRAM).
Fig. 3 A～3F discloses the manufacture method of another embodiment of the present invention on-plane surface gridistor.At first, please refer to Fig. 3 A, a substrate 302 is provided, in substrate 302, form the mask layer 304 of silicon nitride for example.With mask layer 304 is mask, carries out photoetching and etch process and form a groove 305 in substrate 302.Then, shown in Fig. 3 B, substrate 302 is placed a reative cell, feed an impurity gas 301, and heating makes the diffusion of impurities in the impurity gas 301 go into the zone (channel doping district 306 as shown in the figure) of adjacent trenches 305 sidewalls in the substrate 302.When semiconductor element is NMOS, impurity gas 301 comprises boron (BF for example
2), when semiconductor element is PMOS, impurity gas 301 comprises arsenic or phosphorus (PH for example
3Or AsH
3).Shown in Fig. 3 C, remove the mask layer 304 in the substrate 302.
Follow-up, please refer to Fig. 3 D, form one for example the gate dielectric film 308 of silica in groove 305 with substrate 302 on.Form a gate electrode layer 310 on gate dielectric film 308, and insert in the groove 305.Grind gate electrode layer 310 in the hope of planarization with for example chemical mechanical milling method.Form one for example the hard mask layer 312 of silicon nitride on gate electrode layer 310.In an embodiment of the present invention, above-mentioned make diffusion of impurities in the impurity gas go into the step of adjacent trenches 305 sidewall areas in the substrate 302 after, can in same reative cell, form gate dielectric film 308 by same environment (in-situ).In another embodiment of the present invention, above-mentioned make diffusion of impurities in the impurity gas go into the step of adjacent trenches 305 sidewall areas in the substrate 302 after, can in same reative cell, form gate dielectric film 308 and gate electrode layer 310 together by same environment (in-situ).
Then, please refer to Fig. 3 E, with gold-tinted photoetching and etch process patterning hard mask layer 312.Form patterning hard mask layer 312a thereafter.Next, please refer to Fig. 3 F, with patterning hard mask layer 312a is mask, carry out an anisotropic etch process, patterned gate electrode layer 310 and gate dielectric film 308, make to constitute and be arranged in the gate dielectric 308a on groove 305 sidewalls and be arranged at groove 305 and the gate electrode 310a on outstanding substrate 302 surfaces.Follow-up, carry out an ion implantation technology, in gate electrode 310a substrate on two sides 302, form an one source pole district 314 and a drain region 316 respectively.
The impurity of this embodiment can be distributed in the transistorized raceway groove of on-plane surface grid structure equally uniformly owing to mix for thermal diffusion, can more effectively suppress short-channel effect.
Groove of the present invention is not limited to above-mentioned cylindricality, and it can also be other shape, and method provided by the present invention can make alloy be uniformly distributed in the transistorized raceway groove of on-plane surface grid structure of other shape equally.For instance, please refer to Fig. 4 A, the groove that this embodiment is arranged in substrate 402 is that upper dimension is less, the doleiform groove 405 that lower dimension is bigger.Same adopted said method is a mask with the mask layer in the substrate 402 406, feeding impurity gas makes the impurity thing diffuse into the zone of contiguous doleiform groove 405 sidewalls in the substrate 402 with the thermal diffusion method, perhaps, by forming doped layer (not illustrating) on the sidewall of doleiform groove 405, and carry out a heating process, make the alloy in the doped layer diffuse into the zone that is close to doleiform groove 405 sidewalls in the substrate 402, form channel doping district 408.Follow-up, mask layer 406 is removed.
Then, shown in Fig. 4 B, form one for example the gate dielectric film 410 of silica in doleiform groove 405 with substrate 402 on.Form a gate electrode layer 412 in gate dielectric film 410, and insert in the doleiform groove 405.Grind gate electrode layer 412 with for example chemical mechanical milling method.Form one for example the hard mask layer 413 of silicon nitride on gate electrode layer 412.As Fig. 4 C shown in, with gold-tinted photoetching and etch process patterning hard mask layer 413, then, form patterning hard mask layer 413a thereafter.Next, please refer to Fig. 4 D, with patterning hard mask layer 413a is mask, carry out an anisotropic etch process, patterned gate electrode layer 412 and gate dielectric film 410, make to constitute and be arranged at the gate dielectric 410a on the sidewall in the doleiform groove 405 and be arranged in the doleiform groove 405 and the gate electrode 412a on outstanding substrate 402 surfaces.Follow-up, carry out an ion implantation technology, in gate electrode 412a substrate on two sides 402, form an one source pole district 407 and a drain region 409 respectively.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention, and when doing a little change and retouching.Therefore, protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (23)
1. the manufacture method of a semiconductor element comprises:
One substrate is provided, and it comprises a groove;
With first-class tropism's doping method, the zone of at least one impurity contiguous this trenched side-wall in this substrate that mixes;
Form on the sidewall of a gate dielectric in this groove; And
Form a gate electrode in this groove, and outstanding this substrate surface.
2. the manufacture method of semiconductor element as claimed in claim 1, wherein these tropism's doping methods heat this doped layer again for forming a doped layer on this trenched side-wall, and this diffusion of impurities in this doped layer is gone in this substrate.
3. the manufacture method of semiconductor element as claimed in claim 1, wherein these tropism's doping methods are for to place the environment that comprises an impurity gas with this substrate, and heating makes this diffusion of impurities in this impurity gas go into the zone of contiguous this trenched side-wall in this substrate.
4. the manufacture method of semiconductor element as claimed in claim 1 comprises that also a formation one source pole district and a drain region are in this substrate of these gate electrode both sides.
5. the manufacture method of semiconductor element as claimed in claim 1, wherein this anisotropic method this substrate of mixing makes this doping impurity in a channel region of this semiconductor element, constitutes a channel doping district.
6. the manufacture method of semiconductor element as claimed in claim 5, wherein the top in this channel doping district is lower than the bottom of this source area and this drain region.
7. the manufacture method of semiconductor element as claimed in claim 1, wherein this impurity is uniformly distributed in the zone of contiguous this trenched side-wall in this substrate.
8. the manufacture method of semiconductor element as claimed in claim 1, wherein this groove is that a upper dimension is less, the doleiform groove that lower dimension is bigger.
9. the manufacture method of a semiconductor element comprises:
One substrate is provided, and it comprises a groove;
Form a doped layer on the sidewall of this groove;
Form a barrier layer, it covers this doped layer at least;
Carry out a heating process, make the diffusion of impurities in this doped layer go into the zone of contiguous this trenched side-wall in this substrate;
Form a gate dielectric on the sidewall of this groove; And
Form a gate electrode in this groove, and outstanding this substrate surface.
10. the manufacture method of semiconductor element as claimed in claim 9, wherein when this semiconductor element be NMOS, this impurity of this doped layer comprises Pyrex.
11. the manufacture method of semiconductor element as claimed in claim 9, wherein working as this semiconductor element is PMOS, and this impurity of this doped layer comprises phosphorosilicate glass or arsenic silex glass.
12. the manufacture method of semiconductor element as claimed in claim 9, wherein the step of this formation one doped layer on the sidewall of this groove comprises:
The smooth property covered ground forms a mask layer on this doped layer, and inserts in this groove;
Remove outer this mask layer of part of this groove; And
With this mask layer is mask, carries out an etch process, removes outer this doped layer of part of this groove.
13. the manufacture method of semiconductor element as claimed in claim 12, wherein this mask layer is a photoresist.
14. the manufacture method of semiconductor element as claimed in claim 9, wherein this barrier layer comprises tetraethoxy silicomethane (TEOS).
15. the manufacture method of semiconductor element as claimed in claim 9, wherein this impurity is uniformly distributed in the zone of contiguous this trenched side-wall in this substrate.
16. the manufacture method of semiconductor element as claimed in claim 9, wherein this groove is that a upper dimension is less, the doleiform groove that lower dimension is bigger.
17. the manufacture method of a semiconductor element comprises:
One substrate is provided, and it comprises a groove and the outer suprabasil mask layer of this groove;
This substrate is placed a reative cell, feed an impurity gas, and heating makes the diffusion of impurities in this impurity gas go into the zone of contiguous this trenched side-wall in this substrate;
Form on the sidewall of a gate dielectric in this groove; And
Form a gate electrode in this groove, and outstanding this substrate surface.
18. the manufacture method of semiconductor element as claimed in claim 17 is wherein worked as this semiconductor element and comprised NMOS, this impurity gas comprises the gas of boron.
19. the manufacture method of semiconductor element as claimed in claim 18, wherein this impurity gas comprises BF
2
20. the manufacture method of semiconductor element as claimed in claim 17 is wherein worked as this semiconductor element and comprised PMOS, this impurity gas comprises the gas of arsenic or phosphorus.
21. the manufacture method of semiconductor element as claimed in claim 20, wherein this impurity gas comprises AsH
3Or PH
3
22. the manufacture method of semiconductor element as claimed in claim 17, wherein this diffusion of impurities in making this impurity gas is gone into the step in this substrate, be that original position forms a gate dielectric film and a gate electrode layer in this reative cell, and, constitute this gate dielectric and this gate electrode in this gate dielectric film of subsequent step patterning and this gate electrode layer.
23. the manufacture method of semiconductor element as claimed in claim 17, wherein this groove is that a upper dimension is less, the doleiform groove that lower dimension is bigger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101287460A CN101345195A (en) | 2007-07-12 | 2007-07-12 | Method for manufacturing semiconductor element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101287460A CN101345195A (en) | 2007-07-12 | 2007-07-12 | Method for manufacturing semiconductor element |
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|---|---|
| CN101345195A true CN101345195A (en) | 2009-01-14 |
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| CNA2007101287460A Pending CN101345195A (en) | 2007-07-12 | 2007-07-12 | Method for manufacturing semiconductor element |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184959A (en) * | 2011-04-25 | 2011-09-14 | 上海宏力半导体制造有限公司 | Power MOS (Metal-Oxide Semiconductor) tube and manufacturing method thereof |
| CN102738001A (en) * | 2011-03-30 | 2012-10-17 | 茂达电子股份有限公司 | Method for manufacturing power transistor with super interface |
| CN103855018A (en) * | 2012-12-04 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Method for adjusting BV and improving RDSON through ion implantation at bottoms of trenches |
| CN109390225A (en) * | 2017-08-04 | 2019-02-26 | 世界先进积体电路股份有限公司 | Semiconductor structure and its manufacturing method |
-
2007
- 2007-07-12 CN CNA2007101287460A patent/CN101345195A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738001A (en) * | 2011-03-30 | 2012-10-17 | 茂达电子股份有限公司 | Method for manufacturing power transistor with super interface |
| CN102184959A (en) * | 2011-04-25 | 2011-09-14 | 上海宏力半导体制造有限公司 | Power MOS (Metal-Oxide Semiconductor) tube and manufacturing method thereof |
| CN103855018A (en) * | 2012-12-04 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Method for adjusting BV and improving RDSON through ion implantation at bottoms of trenches |
| CN103855018B (en) * | 2012-12-04 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | Channel bottom carries out ion implanting and adjusts BV and the method for improving conducting resistance |
| CN109390225A (en) * | 2017-08-04 | 2019-02-26 | 世界先进积体电路股份有限公司 | Semiconductor structure and its manufacturing method |
| CN109390225B (en) * | 2017-08-04 | 2021-04-09 | 世界先进积体电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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Open date: 20090114 |