CN1206724C - Method for mfg. mask type ROM in high density planar unit mode - Google Patents
Method for mfg. mask type ROM in high density planar unit mode Download PDFInfo
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- CN1206724C CN1206724C CN02101553.8A CN02101553A CN1206724C CN 1206724 C CN1206724 C CN 1206724C CN 02101553 A CN02101553 A CN 02101553A CN 1206724 C CN1206724 C CN 1206724C
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- high density
- mask
- unit mode
- layer
- planar unit
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 150000002500 ions Chemical class 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 239000002019 doping agent Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000002513 implantation Methods 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000004576 sand Substances 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 150000001875 compounds Chemical class 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000000428 dust Substances 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The present invention relates to a method for manufacturing a mask type ROM in high density planar unit mode, which uses a step matched with CMOS programming and adds a light mask for etching isolation layers to manufacture the mask type ROM in high density planar unit mode. Firstly, a shallow trough isolating programming is implemented to form a plurality of shallow troughs at substrate, and an isolating layer is filled in the trough; secondly, the isolating layer is etched to be lower than the substrate surface with a set distance; thirdly, a compound crystal silicon layer of dopant ions is formed at the isolating layer; fourthly, a well area implantation and an anneal programming are implemented to make dopant ions diffuse to form a plurality of bit line areas, wherein a channel area is formed between any two bit line areas, then brake pole oxide layers and brake pole word lines are orderly formed, and parts of the channel areas are selected to use as coding areas; finally, ion distribution and implantation is performed to the coding areas.
Description
Technical field
The present invention is about a kind of mask-type ROM manufacture method, especially in regard to a kind of mask-type ROM manufacture method of high density planar unit mode type.
Background technology
Conventional method increases the density of memory cells of mask-type ROM by the mask-type ROM of making the planar unit mode type, as United States Patent (USP) the 5th, 688, No. 661 patents, yet it is the processing procedure complexity not only, and this kind mask-type ROM has the not good characteristic of surface profile.In addition, United States Patent (USP) the 6th, 034, No. 403 patents are then because processing procedure is special, can't with existing CMOS process-compatible so that can't utilize the standard processing procedure to form memory cell areas and periphery circuit region simultaneously.
Summary of the invention
In view of this, it is complicated and because of can't utilizing the standard processing procedure to form the problem of memory cell areas and periphery circuit region simultaneously with the CMOS process-compatible to the objective of the invention is to solve above-mentioned processing procedure.For achieving the above object, the present invention proposes a kind of mask-type ROM manufacture method of high density planar unit mode type, is to utilize the step of coupling CMOS processing procedure and increase the mask-type ROM of making the high density planar unit mode type together in order to the light shield of etch isolates layer.At first implement a shallow trench separation process to form a plurality of shallow trenchs in substrate, insert a separator then, secondly the etch isolates layer then forms the compound crystal silicon layer of a dopant ion to make it to be lower than both set a distances of substrate surface one in this insulation surface; Implement a wellblock implantation and annealing process then so that dopant ion diffuses to form many position radio zone, form a channel region between the wherein wantonly two bit line districts, form compole oxide layer and compole character line more in regular turn, the channel region of selecting part carries out implanting ions to those code areas at last with as the code area.
Description of drawings
Below, with the mask-type ROM manufacture method embodiment of accompanying drawings a kind of high density planar unit mode type of the present invention.
Fig. 1 is the mask-type ROM manufacture method flow chart of explanation a kind of high density planar unit mode type of the present invention.
Fig. 2 a is in the explanation embodiments of the invention, forms the step of shallow trench.
Fig. 2 b is in the explanation embodiments of the invention, forms the step of separator in shallow trench.
Fig. 2 c is in the explanation embodiments of the invention, the step of removing the part separator.
Fig. 2 d is in the explanation embodiments of the invention, removes the step of pad nitrogenize layer of sand.
Fig. 2 e is in the explanation embodiments of the invention, forms the step of the conductive layer of dopant ion.
In Fig. 2 f explanation embodiments of the invention, form the wellblock, source/drain region, and the step of buried type position radio zone.
Fig. 2 g is in the explanation embodiments of the invention, removes the step of pad oxide and formation gate pole oxidation layer.
Fig. 2 h is in the explanation embodiments of the invention, forms the step of gate character line.
Fig. 2 i is in the explanation embodiments of the invention, implements the ion implantation step of code area.
Symbol description
The 100--substrate; 130a, 130b--shallow trench;
140a, 140b--separator; The conductive layer of 160--dopant ion;
160a--bit line district; The 170--channel region;
The 180--gate pole oxidation layer; 190--gate character line;
The 170a--code area; 101--word storage unit district;
The 102--periphery circuit region; The 125--cushion layer structure;
The 110--pad oxide; 120--pad nitrogenize layer of sand;
103--P type wellblock; 104--N type wellblock.
Embodiment
Embodiment
See also Fig. 1 and reach Fig. 2 a to Fig. 2 i, it has illustrated a kind of mask-type ROM manufacture method of high density planar unit mode type, it comprises that fabrication steps causes 590, because above-mentioned processing procedure is a coupling CMOS processing procedure, therefore can form memory cell areas and periphery circuit region simultaneously by the standard processing procedure.
At first implementation step S10 shown in step S20, implements a shallow trench separation process to form a plurality of shallow trench 130a in substrate 100 then so that a substrate 100 to be provided.
The embodiment that wherein realizes above-mentioned steps at first provides a silicon base shown in Fig. 2 a, this silicon base has a memory cell areas 101 and a periphery circuit region 102.
Then, implement a shallow trench separation process, for example at first form a cushion layer structure 125 in the silicon base surface, it can select to be made up of the pad nitrogenize layer of sand 120 of the pad oxide 110 of thickness 80-200 dust and thickness 1000-2000 dust, implement a micro-photographing process then to transfer the shallow trench pattern to silicon base 100, for example be coated with one deck photoresist earlier, behind exposure imaging, cushion layer structure 125 is etched with exposes part silicon base surface, serve as the cover curtain with cushion layer structure 125 then, the etching silicon substrate is removed remaining photoresistance at last to form the shallow trench 130a and the 130b of degree of depth 2500-4500 dust respectively at memory cell areas 101 and periphery circuit region 102.
Secondly implementation step S30 is to insert a separator 140a in those shallow trenchs 130a and 130b.
The embodiment that wherein realizes above-mentioned steps is shown in Fig. 2 b, at first comprehensive formation one oxide layer is implemented a planarisation step then, for example uses the cmp processing procedure to remove unnecessary oxide layer, stay the isolating oxide layer 140a that fills up these shallow trenchs, 140b.
Secondly implementation step S40 makes this separator 140a be lower than both set a distance d of substrate surface one to remove the separator of part.
Wherein realize embodiment such as Fig. 2 c of above-mentioned steps, shown in Fig. 2 d, at first shown in Fig. 2 C, one oxide layer etching light shield of extra making, implement a micro-photographing process then to transfer pattern to silicon base 100, for example be coated with one deck photoresist earlier, after photodevelopment, stay the residue photoresist layer 150 that covers periphery circuit region 102, wherein this residue photoresist layer 150 with cushion layer structure 125 as etch mask, implement an etching step then, as to utilize oxide layer be 3: 1 above dry-etchings to the etching selectivity of nitrogenize layer of sand, carry out partially-etched to the oxide layer 140a in the shallow trench of memory cell areas 101, so that remaining oxide layer 140a is lower than both set a distance d of silicon base surface one in the shallow trench, for example be about 0.1um.
Then, see also Fig. 2 d, after the oxide layer etching step is finished, then implement to remove remaining photoresist layer 150 and select to carry out the step that wet etching is removed pad nitrogenize layer of sand 120 with phosphoric acid solution.
Implementation step S50 is to form the conductive layer 160 of the dopant ion of a thickness 1000-2000 dust in separator 140a surface then.
The embodiment that wherein realizes above-mentioned steps is shown in Fig. 2 e, the polysilicon layer of at first comprehensive deposition one N type dopant ion, then with etching selectivity greater than under 10 the condition, this polysilicon layer of etch-back is to form the polysilicon layer 160 of the dopant ion of planarization in oxide layer 140a surface, wherein above-mentioned dopant ion can be selected phosphonium ion.
Implementation step S60 then, it utilizes a wellblock implantation and annealing process so that the dopant ion diffusion of above-mentioned conductive layer 100 and form many buried type bit line district 160a forms a channel region 170 between the wherein wantonly two N type bit line districts.
The embodiment that wherein realizes above-mentioned steps is shown in Fig. 2 f, utilize twin-well or Mitsui implantation process and annealing process in the standard CMOS processing procedure, silicon base in memory cell areas 101 forms p type wells district 103, and in the silicon base formation p type wells district 103 and the N type wellblock 104 of periphery circuit region 102, wherein when implementing annealing process, dopant ion forms many N type bit line district 160a from the polysilicon layer sidewall diffusion, forms a channel region 170 between the wherein wantonly two N type bit line districts.
Implementation step 570 then, to form a gate pole oxidation layer 180 and a gate character line 190a who is across these bit lines district 160a and channel region 170 in regular turn.
The embodiment that wherein realizes above-mentioned steps is shown in Fig. 2 g and Fig. 2 h, see also Fig. 2 g, at first etching is removed pad oxide 110 to expose the silicon base surface, implement a step of thermal oxidation then to form a gate pole oxidation layer 180, wherein owing to dopant ion energy accelerating oxidation speed at polysilicon layer 160, therefore, at the thickness of the gate pole oxidation layer 180b on dopant ion polysilicon layer 160 surfaces, the gate pole oxidation layer 180a that generates greater than silicon base surface at memory cell areas and periphery circuit region.
Then see also Fig. 2 h, utilize the gate character line processing procedure in the standard CMOS processing procedure, be across the gate character line 190a of these bit lines district 160a and channel region 1706 respectively at the gate pole oxidation layer 180 surface formation one of memory cell areas 101, and in the gate pole oxidation layer 180a surface formation one gate character line 190b of periphery circuit region 102, implement source/drain ion implantation step then and form N type source/drain electrode (S/D) with p type wells district respectively at periphery circuit region, and in the N of periphery circuit region type wellblock formation P type source/drain electrode (S/D), said structure constitutes the CMOS transistor.
Implementation step 580 then, and the channel region of selecting earlier part is with as code area 170a, and implementation step S90 is to carry out implanting ions to those code areas 170a again.
The embodiment that wherein realizes above-mentioned steps at first makes the light shield of encoding together shown in Fig. 2 i, be coated with one deck photoresist then; Behind exposure imaging, form patterned light blockage layer 200 these patterned light blockage layer 200 and have an opening to expose the gate character line 190a surface of code area door 0a top.Serve as the cover curtain with this patterned light blockage layer 200 then, those code areas 170a is carried out boron or boron fluoride (B/BF
2) implanting ions, with the starting voltage (Vth) that improves code area 170a and then form a mask-type ROM that normally closes (normally off).
Because traditional high density planar unit mode type mask-type ROM manufacture method, the most complexity of its fabrication steps maybe need be utilized particular process sequence, the present invention is then under one simple oxidation layer etching light shield of extra increase, the step with the CMOS process-compatible can be used, and the mask-type ROM of high density planar unit mode types can be made simultaneously in memory cell areas 101; And make the CMOS transistor arrangement in periphery circuit region 102.
Though the present invention discloses as above with a preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention, and when doing a little change and retouching; Therefore protection scope of the present invention should be with appended being as the criterion that claim was defined.
Claims (9)
1. the mask-type ROM manufacture method of a high density planar unit mode type is characterized in that, comprises the following step:
One substrate is provided;
Implement a shallow trench separation process in this substrate, to form a plurality of shallow trenchs;
In these shallow trenchs, insert a separator;
This separator of removing part is so that this separator is lower than both set a distances of this substrate surface one;
Form the conductive layer of a dopant ion in this insulation surface;
Implement a wellblock implantation and annealing process so that this dopant ion diffuses to form many buried type bit line districts, form a channel region between the wherein wantonly two bit line districts;
Form a gate pole oxidation layer and a compole character line that is across these bit line districts and channel region in regular turn;
The channel region of selecting part is with as the code area; And
Implanting ions is carried out in those code areas.
2. the mask-type ROM manufacture method of high density planar unit mode type as claimed in claim 1 is characterized in that, wherein, this shallow trench separation process comprises:
Form a cushion layer structure in this substrate surface;
This cushion layer structure and substrate are implemented a micro-photographing process, to form a plurality of shallow trenchs.
3. the mask-type ROM manufacture method of high density planar unit mode type as claimed in claim 2 is characterized in that, wherein, this cushion layer structure is made up of a pad oxide and a pad nitrogenize layer of sand.
4. the mask-type ROM manufacture method of high density planar unit mode type as claimed in claim 3 is characterized in that, wherein, this separator is made up of oxide layer.
5. the mask-type ROM manufacture method of high density planar unit mode type as claimed in claim 4; It is characterized in that wherein, the step that forms this separator comprises:
Comprehensive formation one oxide layer;
Implement a planarisation step; To stay the isolating oxide layer that fills up these shallow trenchs.
6. the mask-type ROM manufacture method of high density planar unit mode type as claimed in claim 5 is characterized in that, wherein, the step of removing this separator of part comprises:
Make oxide layer etching light shield one;
Implement a micro-photographing process according to this road oxide layer etching light shield,, and make this isolating oxide layer be lower than both set a distances of this substrate surface one to remove this isolating oxide layer of part.
7. the mask-type ROM manufacture method of high density planar unit mode type as claimed in claim 6, it is characterized in that, wherein, this micro-photographing process comprises an etching step, and it is that 3: 1 dry-etching method is removed this isolating oxide layer of part with oxide layer to the etching selectivity of pad nitrogenize layer of sand.
8. the mask-type ROM manufacture method of high density planar unit mode type as claimed in claim 1 is characterized in that, wherein, this separator is less than about this substrate surface 0.1um greatly.
9. the mask-type ROM manufacture method of high density planar unit mode type as claimed in claim 1, it is characterized in that, wherein, this gate pole oxidation layer is to form with thermal oxidation method, causes the position to be higher than the part that stays in substrate surface at this gate oxide layer thickness of the conductive layer surface of this dopant ion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02101553.8A CN1206724C (en) | 2002-01-09 | 2002-01-09 | Method for mfg. mask type ROM in high density planar unit mode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02101553.8A CN1206724C (en) | 2002-01-09 | 2002-01-09 | Method for mfg. mask type ROM in high density planar unit mode |
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| CN1431705A CN1431705A (en) | 2003-07-23 |
| CN1206724C true CN1206724C (en) | 2005-06-15 |
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| CN102033971B (en) * | 2009-09-29 | 2012-12-26 | 中芯国际集成电路制造(上海)有限公司 | Design method of circuit patterns and rapid thermal annealing method of semiconductor device |
| CN102683290A (en) * | 2011-03-08 | 2012-09-19 | 无锡华润上华半导体有限公司 | ROM (read only memory) device and manufacturing method thereof |
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Effective date of registration: 20111121 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
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