CN102683290A - ROM (read only memory) device and manufacturing method thereof - Google Patents
ROM (read only memory) device and manufacturing method thereof Download PDFInfo
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- CN102683290A CN102683290A CN201110054243XA CN201110054243A CN102683290A CN 102683290 A CN102683290 A CN 102683290A CN 201110054243X A CN201110054243X A CN 201110054243XA CN 201110054243 A CN201110054243 A CN 201110054243A CN 102683290 A CN102683290 A CN 102683290A
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Abstract
The embodiment of the invention discloses an ROM (read only memory) device and a manufacturing method of the ROM device. The manufacturing method comprises the steps of: providing a substrate; forming a hard mask layer on the substrate; forming a buried layer pattern in the hard mask layer; forming a groove in the substrate by using the hard buried layer provided with a buried layer pattern as a mask; and forming a buried layer area in the substrate at the bottom of the groove by using the hard mask layer provided with the buried layer pattern as the mask. According to the manufacturing method provided by the invention, the groove is formed in the substrate, and ions are injected in the substrate at the bottom of the groove so as to form the buried layer area, so that the problem of electric leakage existing between a buried layer resistor and the buried layer can be released to a certain extent.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, relate to a kind of ROM device and manufacturing approach thereof.
Background technology
Programming ROM (read-only memory, Read-Only Memory), the MASKROM that is otherwise known as, its content can realize satisfying the ROM programming of user's needs then by user oneself customization through the mask process in the ic manufacturing process.FLATCELL ROM (plate ROM) makes simply because of it, and area is little extensively to be applied in the manufacturing of MASKROM with the integrated level height.
Referring to Fig. 1; The physical structure of flat cell has been shown among the figure; 10 represent buried dopant layer (as source/leakage of cell) among the figure, and 11 represent grid, the public identical source/leakage of the flat cell of each row; The public identical grid of each row's flat cell adopts the PN junction transoid to isolate between the flat cell.
The characteristic size (CD) of the ROM device of producing at present can reach 0.4 μ m, but the integrated level of As IC is increasingly high, the CD of all kinds of ROM devices miniaturization more.Along with reducing of buried dopant layer (comprise that the N type mixes and the P type mixes, be called for short BN and BP respectively) spacing, must make leakage current increase, even cause forming short circuit between the buried dopant layer, cause the ROM device to be scrapped.
In order to make the littler ROM device of CD, must solve the problem that leakage current increases.The existing method that can be used for reducing leakage current has (existing is that example is explained with N type buried dopant layer): 1, sacrifice BN resistance: the concentration of BN resistance and injection is inversely proportional to, and promptly implantation concentration is high more, and BN resistance is more little; But the raising of implantation concentration can cause ion horizontal proliferation aggravation, and ion horizontal proliferation aggravation just means that also the BN spacing reduces, thereby increases leakage current; Therefore; Through reducing the implantation concentration of BN, promptly increase BN resistance, make the ion horizontal proliferation reduce; Make the BN depletion region reduce, thereby reach the purpose that reduces leakage current.2, reduce the BN size: under the situation that BN size and BN spacing summation remain unchanged, through reducing the increase that the BN size can realize the BN spacing, thereby reach the purpose that reduces leakage current.
Though above-mentioned two kinds of methods can objectively reach the purpose that reduces leakage current; But all there is very big drawback,, sacrifices BN resistance and promptly mean increase BN resistance for first method; And the increase of BN resistance is unfavorable for the raising of the ROM device speed of service, and then influences performance of products.For second method, the BN size is very little in the existing technology, is difficult to further realize reducing of BN size again.Therefore, reducing leakage current through these two kinds of methods all is difficult to carry out.
Summary of the invention
In view of this, the present invention provides a kind of ROM device and manufacturing approach thereof, to reach the purpose that reduces leakage current.
For realizing above-mentioned purpose, the present invention provides following technical scheme:
A kind of ROM device making method comprises:
Substrate is provided, in said substrate, forms hard mask layer;
In said hard mask layer, form the buried regions pattern;
With the hard mask layer with buried regions pattern is that mask forms groove in said substrate;
With the hard mask layer with buried regions pattern is that mask forms the buried regions district in the substrate of said channel bottom.
Preferably, said is that mask forms the buried regions district in the substrate of said channel bottom with the hard mask layer with buried regions pattern, specifically comprises:
With said hard mask layer with buried regions pattern is that mask injects ion in the substrate of said channel bottom;
Remove said hard mask layer with buried regions pattern;
Quick thermal annealing process is carried out in said substrate.
Preferably, in said hard mask layer, form the buried regions pattern, specifically comprise:
On said hard mask layer, form photoresist layer with buried regions pattern;
With said photoresist layer with buried regions pattern is that mask forms the buried regions pattern in said hard mask layer;
Remove said photoresist layer with buried regions pattern.
Preferably, said method also comprises: in the substrate with buried regions district, form gate oxide.
Preferably, said hard mask layer is the SiN layer.
Preferably, the position in said buried regions district is corresponding with the groove position.
The present invention also provides a kind of ROM device, comprising:
Substrate;
Be positioned at said intrabasement groove;
Be positioned at the substrate of said channel bottom, the buried regions district corresponding with the groove position.
Preferably, said ROM device also comprises: be covered in the suprabasil gate oxide that comprises groove.
Preferably, said ROM device also comprises: be positioned in the said substrate, have a hard mask layer of buried regions pattern.
Preferably, said hard mask layer is the SiN layer.
Can find out from technique scheme; Method provided by the present invention is through forming hard mask layer in substrate; Then in said hard mask layer, form the buried regions pattern; Be that mask forms groove in said substrate with hard mask layer then, in the substrate of channel bottom, inject ion and can form the buried regions district with buried regions pattern.The present invention adopts hard mask layer to replace photoresist; Therefore can avoid that hard mask layer is reamed sidewall as photoresist layer in the ion implantation process; Thereby can accurately control the size of the size of formation buried regions in strict conformity with less buried regions process window; Relative to existing technologies, the buried regions size has obtained reducing, and can reduce leakage current effectively; Again owing in said substrate, formed groove; In the substrate of said channel bottom, inject ion and form the buried regions district; Can guarantee that the buried regions district has higher surface concentration, and can form suitable junction depth, thereby reach the purpose that reduces leakage current through the degree of depth and then the control of control groove.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the physical structure sketch map of the FLATCELL ROM device that the embodiment of the invention provided;
Fig. 2 is the flow chart of a kind of ROM device making method that the embodiment of the invention provided;
Fig. 3～Fig. 9 is the cross-sectional view in the ROM device making method that the embodiment of the invention provided;
Figure 10 is the sem photograph of ROM device profile structure in the prior art;
Figure 11 is the sem photograph of the ROM device profile structure that the embodiment of the invention provided.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
A lot of details have been set forth in the following description so that make much of the present invention; But the present invention can also adopt other to be different from alternate manner described here and implement; Those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed specific embodiment.
Secondly, the present invention combines sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is example, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Embodiment one
Said as the background technology part; Reduce all very difficult enforcement of leakage current through sacrificing BN resistance or reducing the BN size; The inventor discovers: for first kind of situation (sacrificing BN resistance), owing to should guarantee the speed of service of ROM device, therefore should not reduce leakage current through sacrificing BN resistance; But should put forth effort under the situation of not sacrificing BN resistance (promptly not reducing the concentration that BN injects), reach the purpose that reduces leakage current.Consider through sacrificing the reason that BN resistance reduces leakage current and be: reduce the concentration (promptly increasing BN resistance) that BN injects; Can reach the purpose that reduces the ion horizontal proliferation; And then reduction leakage current; Therefore, key of problem is to solve high concentration that BN injects and the ion horizontal proliferation contradiction between weakening, and then reduces leakage current.For second kind of situation (reducing the BN size); Be difficult in the prior art further realize that the reason that the BN size reduces is: reducing the BN size actual is the size that reduces the BN process window; And the size of BN process window has been less, on the basis of the BN of reduced size process window, forms BN owing to adopt photoresist to do mask in the prior art; And the sidewall of photoresist is prone to reamed by heavy dose of ion; And then can increase the size of BN, therefore, be difficult to realize the size of BN size in strict conformity with less BN process window.
Based on this, the present invention provides a kind of ROM device making method, and with reference to figure 2, said method comprises:
Step S1: substrate is provided, in said substrate, forms hard mask layer.
Particularly, at first in said substrate, adopt thermal oxidation technology growth pad oxide, adopt chemical vapour deposition (CVD) or physical gas-phase deposite method on said pad oxide, to form hard mask layer then.Pad oxide described in the present embodiment is a silicon dioxide, and said hard mask layer is the SiN layer.
Step S2: in said hard mask layer, form the buried regions pattern.
In the ROM device manufacturing processes, buried regions is used for making bit line and prepares for being connected source/leakage, and the size of buried regions pattern (being the size of BN or BP process window, is that example is explained below without exception with BN) will influence the size of final BN.In the present embodiment through photoetching process with the buried regions design transfer in said hard mask layer.
Step S3: with the hard mask layer with buried regions pattern is that mask forms groove in said substrate.
Can adopt etching technics in the practical implementation process, be mask with the hard mask layer with buried regions pattern, at first etches away said pad oxide, follows the etching substrate and in said substrate, form groove, and the degree of depth of said groove can be by the strict control of etch period.In the present embodiment owing to adopted hard mask layer as mask; Thereby in the process that forms groove and in the process in follow-up formation buried regions district; All can not reamed sidewall, therefore can accurately be controlled the size that groove dimensions and follow-up buried regions district size strictness reach said buried regions pattern as the photoresist mask.And method provided by the present invention relative to existing technologies, is that follow-up formation buried regions district prepares through in said substrate, forming groove, helps the control surface leakage current.
Step S4: with the hard mask layer with buried regions pattern is that mask forms the buried regions district in the substrate of said channel bottom.
Can adopt ion implantation technology, be that mask forms the buried regions district in the substrate of said channel bottom with said hard mask layer with buried regions pattern, and ion carries out annealing in process to said substrate after injecting and accomplishing.
Can find out from the foregoing description; The present invention is through forming hard mask layer in substrate; Then in said hard mask layer, forming the buried regions pattern, is that mask forms groove in said substrate with the hard mask layer with buried regions pattern then, and channel bottom injects ion can form the buried regions district.The present invention is owing to adopt hard mask layer to replace photoresist; Therefore can avoid being reamed sidewall, thereby can accurately control the size that the lateral dimension that forms buried regions meets less BN process window, relative to existing technologies; The BN size has obtained reducing, and can reduce leakage current effectively; Again owing in said substrate, formed groove; In the substrate of said channel bottom, inject ion and form the buried regions district; Can guarantee that the buried regions district has higher surface concentration, and can form suitable junction depth, be beneficial to the leakage current of control surface through control gash depth and then control.
Embodiment two
Below with one more specifically embodiment method provided by the present invention is described, method comprises the steps: described in the present embodiment
Step S1: substrate is provided, in said substrate, forms hard mask layer.
Substrate described in the present embodiment is a P type silicon substrate, and its diameter is 8 inches, and the crystal orientation is < 100 >, and resistivity is 15～20ohm.Said " in the substrate " is meant the zone that is made progress by substrate surface, and this zone does not belong to substrate itself; Said " in the substrate " is meant that this zone belongs to the part of substrate by the zone of substrate surface to the certain depth that extends below.
With reference to figure 3, at first in substrate 1, adopt thermal oxidation technology growth pad oxide 2 in the present embodiment, the hard mask layer that said pad oxide 2 is back formation plays buffering, reduces the effect of stress.Adopt chemical gaseous phase depositing process on said pad oxide 2, to form hard mask layer 3 then, said hard mask layer 3 plays the effect of mask in subsequent step.Pad oxide described in the present embodiment 2 is a silicon dioxide, and said hard mask layer 3 is the SiN layer.
Step S2: in said hard mask layer, form the buried regions pattern.
This step can comprise step S21～S23 again, and is specific as follows:
Step S21: on said hard mask layer, form photoresist layer with buried regions pattern.
With reference to figure 4 and Fig. 5, at first spin coating photoresist 4 on said hard mask layer 3 then utilizes corresponding mask that said photoresist is made public, and develops after the exposure, on said hard mask layer 3, forms the photoresist layer 4 with buried regions pattern 5.
Step S22: with said photoresist layer with buried regions pattern is that mask forms the buried regions pattern in said hard mask layer.
With reference to figure 6, be mask with said photoresist layer 4 with buried regions pattern 5, adopt etching technics in said hard mask layer 3, to form buried regions pattern 5, promptly in this step the buried regions pattern 5 in the photoresist layer 4 has been transferred in the hard mask layer 3.
Step S23: remove said photoresist layer 4 with buried regions pattern 5.
Step S3: with the hard mask layer 3 with buried regions pattern 5 is that mask forms groove in said substrate 1.
With reference to figure 7; Adopting etching technics in the present embodiment, is mask with the hard mask layer 3 with buried regions pattern, at first etches away said pad oxide 2; Follow etching substrate 1 and in said substrate 1, form groove 6, the degree of depth of said groove 6 can be by the strict control of etch period.Because with said hard mask layer 3 with buried regions pattern is that mask forms groove 6, therefore, the position of the corresponding buried regions pattern 5 in the position of groove 6.The general photoresist layer that adopts is as mask in the prior art; And need inject heavy dose of ion when forming buried regions; Therefore said photoresist layer sidewall is easy to reamed, and then makes the final buried regions district size that forms increase, and this also is the reason that the BN size can not further reduce in the prior art.And the present invention adopts hard mask layer 3 as mask; Said hard mask layer 3 has good masking action; Therefore when forming groove and follow-up carry out heavy dose of ion when injecting said hard mask layer 3 all can not reamed sidewall, and then can accurately control the size that groove dimensions and the strictness of BN size reach said buried regions pattern.
Step S4: with the hard mask layer 3 with buried regions pattern is that mask forms the buried regions district in the substrate of said groove 6 bottoms.
This step can comprise step S41～S43 again, and is specific as follows:
Step S41: with said hard mask layer with buried regions pattern is that mask injects ion in the substrate of said channel bottom.
The ion that injects in the embodiment of the invention is arsenic As, promptly in the substrate of said channel bottom, carries out N type ion doping, in the hope of forming the BN buried regions.
Step S42: remove said hard mask layer with buried regions pattern.
Step S43: quick thermal annealing process is carried out in said substrate.
Ion carries out annealing in process to said substrate after injecting and accomplishing.The general high temperature furnace that adopts is heated to 800 ℃～1000 ℃ to substrate in the traditional handicraft, and keeps 30 minutes.Under such temperature and time, heat-treat, will make the ion horizontal proliferation aggravate, and then increase the BN size.Adopt rapid thermal annealing (RTA) technology that substrate is handled in the embodiment of the invention, be about to substrate and put into feeding Ar or N
2Rapid thermal treatment machine (RTP) in.RTA has the advantages that to be rapidly heated with the transient continuous time; Therefore can and minimize between the ions diffusion three at reparation, the active ions of lattice defect and obtain optimization; Thereby help to solve the high concentration of BN injection and the contradiction between the ion horizontal proliferation, and then reach the purpose that reduces leakage current.
With reference to figure 8, in the embodiment of the invention said substrate 1 to be carried out in the substrate of said groove 6 bottoms, forming buried regions district 7 after the quick thermal annealing process, the position in said buried regions district 7 and the position of said groove 6 are corresponding fully.The surface in said buried regions district 7 is the bottom of groove 6, and 7 surfaces, buried regions district are lower than substrate 1 surface, and promptly said buried regions district 7 is positioned at substrate 1.
Step S5: in substrate, form gate oxide with buried regions district.
With reference to figure 9; Adopt the thermal oxidation technology gate oxide 8 of in the substrate with buried regions district 71, growing; Because the surface in said buried regions district 7 is lower than the surface of said substrate 1, therefore, behind growth gate oxide 8 in the said substrate 1; The expansion characteristics of said gate oxide 8 will be lower than substrate 1 surperficial groove 6 to 7 tops, buried regions district and fill and lead up; The gate oxide 8 that above buried regions district 7, forms like this will be different from the outstanding pattern (with reference to Figure 10) of elliptical shape in the traditional handicraft, and promptly formed gate oxide 8 surfaces are more smooth (with reference to Figure 11) in the present embodiment, and this also helps the control of tracking current.
Gate oxide described in the present embodiment 8 is a silicon dioxide, because pad oxide 2 also is a silicon dioxide, therefore when forming gate oxide 8, need not remove said pad oxide 2.
Compare that CD is the ROM device of 0.4 μ m in the prior art, can produce the ROM device of CD below 0.350 μ m, and then make the miniaturization more of ROM device through method provided by the present invention.
Can find out from the foregoing description; ROM device making method provided by the present invention; Through in substrate, forming hard mask layer, and in said hard mask layer, forming the buried regions pattern, is that mask forms groove in said substrate with the hard mask layer with buried regions pattern then; In the substrate of channel bottom, inject ion and form the buried regions district, and in said substrate, form gate oxide.And the method for making the ROM device in the traditional handicraft is: in substrate, form the photoresist layer with buried regions pattern; With said photoresist layer with buried regions pattern is that mask injects ion formation buried regions district in said substrate, and in said substrate, forms gate oxide.
By on can know, ROM device making method provided by the present invention, relative traditional handicraft, its improvements are: adopt hard mask layer to replace photoresist layer, can avoid being reamed sidewall by the ion of heavy dose, and then can accurately control the size of BN; In substrate, form groove; In the substrate of channel bottom, form the buried regions district; Replace in the traditional handicraft directly carrying out ion and inject and form the buried regions district, like this behind follow-up formation gate oxide, can avoid the gate oxide of top, buried regions district to form the outstanding pattern of elliptical shape because of expansion characteristics at substrate surface; And form suitable junction depth through control gash depth may command, and then be beneficial to the control leakage current; And the present invention adopts RTA technology that annealing in process is carried out in said substrate, has solved the high concentration of BN injection and the contradiction between the ion horizontal proliferation, and then has reached the purpose that reduces leakage current.
Embodiment three
The present invention also provides a kind of ROM device, comprising: substrate; Be positioned at said intrabasement groove; Be positioned at said channel bottom substrate, with corresponding buried regions district, groove position.Said ROM device also comprises: be positioned in the said substrate, have a hard mask layer of buried regions pattern.Hard mask layer described in the present embodiment is the SiN layer.
The present invention also provides another kind of ROM device, and the structure of said ROM device is the same with sketch map shown in Figure 9, comprising: substrate 1; Be positioned at the groove 6 of substrate 1; Be positioned at groove 6 bottoms substrate 1, with corresponding buried regions district, groove 6 positions 7.Said ROM device also comprises: be covered in the gate oxide 8 in the substrate 1 that comprises groove 6.Gate oxide described in the present embodiment 8 comprises the pad oxide 2 that is positioned in the said substrate 1, has the buried regions pattern, and said gate oxide 8 is silicon dioxide with pad oxide 2.
ROM device provided by the present invention can form according to above-mentioned ROM device making method.After this ROM device forms; The gate oxide that is positioned at buried regions district top will no longer be the outstanding pattern of traditional elliptical shape; But present more smooth surface; This just makes said buried regions district appear to Embedded structure, and therefore, ROM device provided by the present invention is also referred to as RECESSS FLATCELL ROM (embedded flat type ROM) device.
Each embodiment adopts the mode of going forward one by one to describe in this specification, and what each embodiment stressed all is and the difference of other embodiment that so description is fairly simple, relevant part is partly explained referring to method and got final product.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to these embodiment shown in this paper, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
Claims (10)
1. a ROM device making method is characterized in that, comprising:
Substrate is provided, in said substrate, forms hard mask layer;
In said hard mask layer, form the buried regions pattern;
With the hard mask layer with buried regions pattern is that mask forms groove in said substrate;
With the hard mask layer with buried regions pattern is that mask forms the buried regions district in the substrate of said channel bottom.
2. method according to claim 1 is characterized in that, is that mask forms the buried regions district in the substrate of said channel bottom with the hard mask layer with buried regions pattern, specifically comprises:
With said hard mask layer with buried regions pattern is that mask injects ion in the substrate of said channel bottom;
Remove said hard mask layer with buried regions pattern;
Quick thermal annealing process is carried out in said substrate.
3. method according to claim 1 is characterized in that, in said hard mask layer, forms the buried regions pattern, specifically comprises:
On said hard mask layer, form photoresist layer with buried regions pattern;
With said photoresist layer with buried regions pattern is that mask forms the buried regions pattern in said hard mask layer;
Remove said photoresist layer with buried regions pattern.
4. method according to claim 1 is characterized in that, also comprises: in the substrate with buried regions district, form gate oxide.
5. method according to claim 1 is characterized in that, said hard mask layer is the SiN layer.
6. according to each described method of claim 1～5, it is characterized in that the position in said buried regions district is corresponding with the groove position.
7. a ROM device is characterized in that, comprising:
Substrate;
Be positioned at said intrabasement groove;
Be positioned at the substrate of said channel bottom, the buried regions district corresponding with the groove position.
8. ROM device according to claim 7 is characterized in that, also comprises: be covered in the suprabasil gate oxide that comprises groove.
9. ROM device according to claim 7 is characterized in that, also comprises: be positioned in the said substrate, have a hard mask layer of buried regions pattern.
10. ROM device according to claim 9 is characterized in that, said hard mask layer is the SiN layer.
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| CN201110054243XA CN102683290A (en) | 2011-03-08 | 2011-03-08 | ROM (read only memory) device and manufacturing method thereof |
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| CN201110054243XA CN102683290A (en) | 2011-03-08 | 2011-03-08 | ROM (read only memory) device and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111952328A (en) * | 2020-09-25 | 2020-11-17 | 上海华力微电子有限公司 | Method for manufacturing CMOS image sensor |
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| GB2190241A (en) * | 1986-05-09 | 1987-11-11 | Seiko Epson Corp | Method of making an isolation region in semiconductor device |
| CN1182500A (en) * | 1995-04-21 | 1998-05-20 | 西门子公司 | Read-only storage cell arrangement and process for its production |
| US20020037627A1 (en) * | 2000-08-10 | 2002-03-28 | Liu Mark Y. | Extension of shallow trench isolation by ion implantation |
| CN1431705A (en) * | 2002-01-09 | 2003-07-23 | 中芯国际集成电路制造(上海)有限公司 | Method for mfg. mask type ROM in high density planar unit mode |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2190241A (en) * | 1986-05-09 | 1987-11-11 | Seiko Epson Corp | Method of making an isolation region in semiconductor device |
| CN1182500A (en) * | 1995-04-21 | 1998-05-20 | 西门子公司 | Read-only storage cell arrangement and process for its production |
| US20020037627A1 (en) * | 2000-08-10 | 2002-03-28 | Liu Mark Y. | Extension of shallow trench isolation by ion implantation |
| CN1431705A (en) * | 2002-01-09 | 2003-07-23 | 中芯国际集成电路制造(上海)有限公司 | Method for mfg. mask type ROM in high density planar unit mode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111952328A (en) * | 2020-09-25 | 2020-11-17 | 上海华力微电子有限公司 | Method for manufacturing CMOS image sensor |
| CN111952328B (en) * | 2020-09-25 | 2023-04-28 | 上海华力微电子有限公司 | Manufacturing method of CMOS image sensor |
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Application publication date: 20120919 |