CN102024717A - 一种半导体芯片的共晶方法及共晶结构 - Google Patents

一种半导体芯片的共晶方法及共晶结构 Download PDF

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Publication number
CN102024717A
CN102024717A CN2010102615816A CN201010261581A CN102024717A CN 102024717 A CN102024717 A CN 102024717A CN 2010102615816 A CN2010102615816 A CN 2010102615816A CN 201010261581 A CN201010261581 A CN 201010261581A CN 102024717 A CN102024717 A CN 102024717A
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eutectic
layer
semiconductor chip
pore structure
metal
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CN2010102615816A
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CN102024717B (zh
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刘英策
火东明
孙天宝
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BYD Semiconductor Co Ltd
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BYD Co Ltd
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Priority to CN2010102615816A priority Critical patent/CN102024717B/zh
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Priority to EP11819399.4A priority patent/EP2606509A4/en
Priority to PCT/CN2011/078491 priority patent/WO2012025024A1/en
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Abstract

一种半导体芯片的共晶方法，包括：以基板的一面为承载面形成第一共晶层和以半导体芯片的一面为承载面形成第二共晶层，所述第一共晶层或者第二共晶层为形成有孔结构的共晶层；对第一共晶层和第二共晶层进行共晶连接。本发明还涉及一种半导体芯片的共晶结构，包括半导体芯片、基板，以及位于半导体芯片和基板之间的共晶连接层，其中，所述共晶连接层由第一连接层和有孔结构的第二连接层共晶结合而成。本发明实施例提供的一种半导体芯片的共晶方法及共晶结构，有孔的共晶层和另一共晶层共晶，使二者之间形成更均匀结合力更强的共晶层，进而提高芯片和基板之间的结合力。

Description

一种半导体芯片的共晶方法及共晶结构
技术领域
本发明属于半导体器件制造工艺技术领域，具体涉及一种半导体芯片的共晶方法及共晶结构。
背景技术
当前，在国内众多的LED封装厂，芯片和基板的连接方式主要通过胶(包括银胶、硅胶、白胶)固晶的方式连接。即先把胶滴在基板上，然后把芯片放在基板上有胶的位置，通过胶的粘结作用把芯片固定在基板上。
然而，由于胶(无论是银胶、硅胶还是白胶)的热传导系数比较低，所以用此种方法把芯片固定在基板上，存在一个隐忧，即芯片内产生的热不能有效的传导出去，进而造成芯片可靠性的衰减；此隐忧在大功率芯片中尤其显著。
为了解决上述由于热传导效率差而导致的芯片可靠性衰减的问题，一般主要通过共晶的方法把芯片连接在基板上(此共晶材料具有高的热传导率)。即在芯片的背面和基板的正面镀上共晶材料，然后在一定的温度和压力下，使芯片上的共晶材料和基板上的共晶材料发生共晶反应，进而使芯片和基板结合在一起。图1是现有技术共晶工艺的制造方法流程图，其中1为基板，11为共晶材料，在基板1的正面镀上共晶材料11；2为芯片，21为共晶材料，在芯片2的背面镀上共晶材料21；然后在一定的温度(300度)和压力(50g)下，使芯片2上的共晶材料21和基板1上的共晶材料11发生共晶反应，形成一共晶层3，进而使芯片和基板结合在一起。
虽然共晶工艺能显著提高芯片的可靠性，然而，共晶工序也存在一个问题，即芯片和基板的结合力问题，通常，由共晶工艺把芯片固定在基板上，芯片和基板间的结合力比较差。如何提高共晶工艺的结合力，是当前面临的首要问题。
发明内容
本发明解决的技术问题是现有技术中现有共晶技术中存在的芯片和基板结合力差的问题。
为解决上述技术问题，本发明提供如下技术方案：
一种半导体芯片的共晶方法，包括：以基板的一面为承载面形成第一共晶层和以半导体芯片的一面为承载面形成第二共晶层，所述第一共晶层或者第二共晶层为形成有孔结构的共晶层；对第一共晶层和第二共晶层进行共晶连接。
本发明还涉及一种半导体芯片的共晶结构，包括半导体芯片、基板，以及位于半导体芯片和基板之间的共晶连接层，其中，所述共晶连接层由第一连接层和有孔结构的第二连接层共晶结合而成。
与现有技术相比本发明具有如下有益效果：本发明实施例提供的一种半导体芯片的共晶方法及共晶结构，有孔的共晶层和另一共晶层共晶，使二者之间形成更均匀结合力更强的共晶层，进而提高芯片和基板之间的结合力。
附图说明
图1是现有技术共晶工艺的制造方法流程图。
图2是本发明实施例中沉积粘结层和缓冲层示意图；
图3是本发明实施例中形成中空有孔结构的共晶层示意图；
图4是本发明实施例中基板上形成共晶层示意图；
图5是本发明实施例中基板和芯片进行共晶示意图；
图6是本发明第一实施例中在缓冲层上涂覆光刻胶示意图；
图7是本发明第一实施例中在缓冲层上沉积层叠体示意图；
图8是本发明第一实施例中剥离光刻胶示意图；
图9是本发明第一实施例中对层叠体腐蚀示意图；
图10是本发明第二实施例中在缓冲层上沉积层叠体示意图；
图11是本发明第二实施例中在层叠体上沉积保护层示意图；
图12是本发明第二实施例中在保护层上进行光刻示意图；
图13是本发明第二实施例中腐蚀保护层并剥离光刻胶示意图；
图14是本发明第二实施例中对层叠体腐蚀示意图；
图15是本发明第二实施例中去除保护层示意图。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
一种半导体芯片的共晶方法，包括：以基板的一面为承载面形成第一共晶层和以半导体芯片的一面为承载面形成第二共晶层，所述第一共晶层或者第二共晶层为形成有孔结构的共晶层；对第一共晶层和第二共晶层进行共晶连接。
与现有技术相比本发明具有如下有益效果：本发明实施例提供的一种半导体芯片的共晶方法，有孔的共晶层和另一共晶层共晶，使二者之间形成更均匀结合力更强的共晶层，进而提高芯片和基板之间的结合力。
本发明实施例以在芯片上形成的第二共晶层是有孔结构的共晶层为例，本发明半导体芯片优选发光二极管芯片。图2至图5是本发明实施例半导体芯片共晶的制造方法各步骤示意图；图2是本发明实施例中沉积粘结层和缓冲层示意图；先在芯片20背面沉积一层粘结层201，此粘结层201可以是Si、Ti、Cr中的一种或其中任意两种的组合，粘结层厚度0.02-0.2um，沉积方法可以是蒸镀，溅射，电镀，化学镀等。之后在此粘结层上面沉积一层缓冲层202，此缓冲层202可以是Au、Ag、Cu中的一种或其中任意两种的组合，粘结层厚度0.05-1um，沉积方法可以是蒸镀，溅射，电镀，化学镀等。图3是本发明实施例中形成中空有孔结构的共晶层示意图；缓冲层202之上做中空有孔结构的共晶层，中空有孔结构的共晶层是由低熔点金属和能与该低熔点金属共晶的缓冲层金属交叠形成，即由第一金属层203和第二金属或合金层204交叠形成，其中第一金属层203是Sn、Bi、Cd、Pb、Se等低熔点金属，第二金属或合金层204是Au、Ag、Cu中的一种或其中任意两种的组合；优选第一金属层203和第二金属或合金层204的循环次数介于3-10之间，这样形成的共晶层比较均匀；第一金属层203层的厚度0.1-2um，第二金属或合金层204层的厚度0.1-2um，沉积方法可以是蒸镀，溅射，电镀，化学镀等。图4是本发明实施例中基板上形成共晶层示意图；在基板10之上沉积第一共晶层101，此第一共晶层101由金属组成，成分同上述的第一金属层203，是Sn、Bi、Cd、Pb、Se等低熔点金属，沉积厚度0.1-2um，沉积方法可以是蒸镀，溅射，电镀，化学镀等。图5是本发明实施例中基板和芯片进行共晶示意图；利用低熔点共晶层203的流动性和共晶机，将半导体芯片具有共晶层的一面和基板具有共晶层的一面相对，把半导体芯片放置在基板之上进行压合，压合压力10-500g，压合温度250-500℃，压合时间0.5-100秒，从而完成了基板和芯片的共晶。本发明的共晶方法不但可以用在芯片和基板的连接上，也可用在倒装芯片中的芯片和衬底的连接上。
有孔结构的共晶层形成方法如下：在承载面上形成粘结层，在粘结层上形成有孔结构的层叠结构。该方法还包括：以所述孔结构的部分侧壁为起点往有孔结构的共晶层里面延伸去除部分层叠结构材料，形成中空结构。有孔结构的共晶层的形成方法可以有多种，以下以其中两种方法为例详述：
图6至图9是方法一的详细步骤；步骤包括：在粘结层201上形成缓冲层202；在部分缓冲层202上涂覆光刻胶210；形成层叠结构，层叠结构由至少包括第一金属层203和第二金属或合金层204交替层叠而成；剥离光刻胶210，形成有孔结构的共晶层；将腐蚀液放入孔结构中腐蚀部分层叠结构，形成中空结构。
图6是在缓冲层上涂覆光刻胶示意图；在粘结层201上形成缓冲层202；在部分缓冲层202上涂覆光刻胶210；要求光刻胶胶厚度大于6um，如图6中的210；光刻胶的形状为长条形，截面为矩形，光刻胶210可以是一个，也可以是多个，光刻胶210是多个即可以形成多个孔结构。在带有光刻胶的芯片上沉积层叠体，如图7是本发明第一实施例中在缓冲层上沉积层叠体示意图；叠型结构为第一金属层203和第二金属或合金层204交替层叠而成，优选第一金属层203和第二金属或合金层204的循环次数介于3-10之间，这样形成的共晶层比较均匀。然后是图8剥离光刻胶示意图，将光刻胶210剥离，形成有孔结构的共晶层。最后进行腐蚀层叠体，如图9所示，利用腐蚀液腐蚀层叠体，将腐蚀液放入孔结构中腐蚀部分层叠体，形成中空结构，腐蚀液要求选用能腐蚀第一金属层203的低熔点金属，而不能腐蚀缓冲层的溶液，优选盐酸、硫酸、硝酸、磷酸其中之一，或它们中任意二者或三者的组合。
图10至图15是方法二的详细步骤；步骤包括：在粘结层201上形成缓冲层202；在缓冲层202之上形成由至少包括第一金属层203和第二金属或合金层204交替层叠的层叠结构；在叠层结构上形成保护层220；在保护层上做光刻，腐蚀保护层形成保护层窗口；利用腐蚀液腐蚀孔结构的叠状共晶层，去除保护膜，形成中空的孔状叠层共晶层。
图10是在缓冲层上沉积层叠体示意图，在粘结层201上形成缓冲层202；在缓冲层202之上形成由至少包括第一金属层203和第二金属或合金层204交替层叠的层叠结构。图11是在层叠体上沉积保护层示意图，保护层220选用SiO2或SiN膜层。图12是在保护层上进行光刻示意图，在保护层220上涂覆光刻胶230，在中央部位留出矩形的开口，开口可以是一个，也可以是多个。图13是腐蚀保护层并剥离光刻胶示意图，利用腐蚀的方法，做出保护图案，即将图13中预留出的矩形开口处的保护层腐蚀掉，腐蚀液选用BOE溶液，BOE溶液是氟化铵和氢氟酸的混合液；然后剥离光刻胶。图14是对层叠体腐蚀示意图；利用腐蚀液的选择性腐蚀特性腐蚀有孔结构的层叠结构，形成中空有孔结构的层叠体；将腐蚀液放入孔结构中腐蚀部分层叠结构，腐蚀液选用对第一金属层203的低熔点金属有不同腐蚀速率的腐蚀溶液，而对缓冲层202和第二金属或合金层204没有腐蚀作用，优选王水溶液。图15是去除保护层示意图；利用BOE溶液去除保护膜，形成最终的中空有孔结构的层叠体。最后再进行共晶操作，这样可以使低熔点单层共晶层均匀扩散进入中空有孔结构的共晶层，使二者之间形成更均匀的共晶层，进而提高芯片和基板之间的结合力。
本发明还涉及一种半导体芯片的共晶结构，如图5的结构所示；包括半导体芯片20、基板10，以及位于半导体芯片和基板之间的共晶连接层，其中，共晶连接层由第一连接层和有孔结构的第二连接层共晶结合而成。有孔结构的第二连接层依次包括粘结层201、缓冲层202、层叠结构，孔结构位于层叠结构中。层叠结构是由低熔点金属和能与该低熔点金属共晶的缓冲层金属交叠形成，由第一金属层203和第二金属或合金层204交叠形成，其中第一金属层203是Sn、Bi、Cd、Pb、Se等低熔点金属，第二金属或合金层204是Au、Ag、Cu中的一种或其中任意两种的组合；优选第一金属层203和第二金属或合金层204的循环次数介于3-10之间，这样形成的共晶层比较均匀。有孔结构的第二连接层还包括中空结构，中空结构与孔结构连通。第一连接层是Sn、Bi、Cd、Pb、Se等低熔点金属。有些实施例中，第一连接层可以形成在半导体芯片上，有孔结构的第二连接层形成在基板上，然后再将两者进行共晶。另外一些实施例中，第一连接层可以形成在基板上，有孔结构的第二连接层形成在半导体芯片上，然后再将两者进行共晶。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (14)

1.一种半导体芯片的共晶方法，其特征在于，包括：以基板的一面为承载面形成第一共晶层和以半导体芯片的一面为承载面形成第二共晶层，所述第一共晶层或者第二共晶层为形成有孔结构的共晶层；对第一共晶层和第二共晶层进行共晶连接。
2.根据权利要求1所述的半导体芯片的共晶方法，其特征在于，所述有孔结构的共晶层形成方法如下：在承载面上形成粘结层，在粘结层上形成有孔结构的层叠结构。
3.根据权利要求2所述的半导体芯片的共晶方法，其特征在于，所述有孔结构的共晶层形成方法还包括：以所述有孔结构的层叠结构的部分侧壁为起点往所述有孔结构的共晶层里面延伸，去除部分层叠结构材料，形成中空结构。
4.根据权利要求3所述的半导体芯片共晶的制造方法，其特征在于，所述有孔结构的共晶层的形成方法进一步如下：在粘结层上形成缓冲层；在部分缓冲层上涂覆光刻胶；在剩余的缓冲层上形成层叠体，所述层叠体由至少包括第一金属层和第二金属或合金层交替层叠而成；剥离光刻胶，形成有孔结构的共晶层；将腐蚀液放入所述孔结构中腐蚀部分层叠结构，形成中空结构。
5.根据权利要求3所述的半导体芯片共晶的制造方法，其特征在于，所述有孔结构的共晶层的形成方法进一步如下：在粘结层上形成缓冲层；在所述缓冲层之上形成由至少包括第一金属层和第二金属或合金层交替层叠的层叠体；在所述叠层结构上形成保护层；在保护层上做光刻，腐蚀保护层形成保护层窗口；利用腐蚀液腐蚀孔结构的层叠体，去除保护膜，形成中空有孔结构的共晶层。
6.根据权利要求4或者5所述的半导体芯片的共晶方法，其特征在于，第一金属层的材料包括Sn、Bi、Cd、Pb或Se，第二金属或合金层的材料包括Au、Ag、Cu中的至少一种。
7.根据权利要求6所述的半导体芯片的共晶方法，其特征在于，与有孔结构的共晶层进行共晶的另一共晶层的材料包括Sn、Bi、Cd、Pb或Se。
8.根据权利要求4或5所述的半导体芯片的共晶方法，其特征在于，所述缓冲层的材料包括Au、Ag、Cu中的至少一种。
9.根据权利要求2-5任一项所述的半导体芯片的共晶方法，其特征在于，所述粘结层的材料包括Si、Ti、Cr中的至少一种。
10.根据权利要求1-5任一项所述的半导体芯片的共晶方法，其特征在于，所述共晶连接的方法如下：将第一共晶层和第二共晶层进行压合，其压合压力10g-500g，压合温度250℃-500℃，压合时间0.5秒-100秒。
11.一种半导体芯片的共晶结构，包括半导体芯片、基板，以及位于半导体芯片和基板之间的共晶连接层，其特征在于，所述共晶连接层由第一连接层和有孔结构的第二连接层共晶结合而成。
12.根据权利要求11所述的半导体芯片的共晶结构，其特征在于，所述第一连接层依次包括粘结层、缓冲层、层叠结构，所述孔结构位于层叠结构中。
13.根据权利要求12所述的半导体芯片的共晶结构，其特征在于，所述第一连接层还包括中空结构，所述中空结构与所述孔结构连通。
14.根据权利要求11-13任一项所述的半导体芯片的共晶结构，其特征在于，所述半导体芯片是发光二极管芯片。
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