WO2012025024A1 - Semiconductor chip assembly and method of preparing the same - Google Patents

Semiconductor chip assembly and method of preparing the same Download PDF

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Publication number
WO2012025024A1
WO2012025024A1 PCT/CN2011/078491 CN2011078491W WO2012025024A1 WO 2012025024 A1 WO2012025024 A1 WO 2012025024A1 CN 2011078491 W CN2011078491 W CN 2011078491W WO 2012025024 A1 WO2012025024 A1 WO 2012025024A1
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WO
WIPO (PCT)
Prior art keywords
layer
semiconductor chip
opening
forming
substrate
Prior art date
Application number
PCT/CN2011/078491
Other languages
French (fr)
Inventor
Yingce Liu
Dongming Huo
Tianbao Sun
Original Assignee
Byd Company Limited
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Filing date
Publication date
Application filed by Byd Company Limited filed Critical Byd Company Limited
Priority to EP11819399.4A priority Critical patent/EP2606509A4/en
Publication of WO2012025024A1 publication Critical patent/WO2012025024A1/en

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    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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Definitions

  • the present disclosure relates to a semiconductor chip, more particularly to a semiconductor chip assembly and a method of preparing the same.
  • a substrate and a semiconductor chip in a light emitting diode are commonly connected by: coating an adhesive (silver colloid, silica gel, gelatin, etc.) on the substrate and subsequently placing a semiconductor chip on the adhesive.
  • an adhesive silver colloid, silica gel, gelatin, etc.
  • the semiconductor chip may be bonded to the substrate after the adhesive is solidified.
  • the heat generated within the assembled semiconductor chip may not be transmitted outside from the semiconductor chip effectively. Therefore, the reliability of the semiconductor chip may be reduced.
  • the semiconductor chip is connected to the substrate by eutectic bonding. That is, a eutectic material with high thermal conductivity is coated on a surface of the substrate and another eutectic material with high thermal conductivity is coated on a surface of the semiconductor chip, and the eutectic materials are heated and pressurized at a predetermined temperature under a predetermined pressure to form a eutectic layer connecting the substrate and the semiconductor chip.
  • Fig. 1 shows a conventional method of preparing a semiconductor chip assembly by eutectic bonding. As shown in Fig.
  • the method comprises the steps of: forming a first eutectic material layer 11 on a surface of a substrate 1; forming a second eutectic material layer 21 on a surface of a semiconductor chip 2; connecting the first eutectic material layer 11 and the second eutectic material layer 21 by eutectic bonding at a temperature of 300 °C under a pressure of 50 grams to form a eutectic layer 3 between the substrate 1 and the semiconductor chip 2.
  • the bonding force between the first and second layers is weak, so that connection between the substrate and the semiconductor chip is poor and unreliable.
  • the present disclosure is directed to solve at least one of the problems existing in the prior art. Accordingly, a semiconductor chip assembly is provided with strong bonding force between the substrate and the semiconductor chip. Furthermore, a method of preparing the semiconductor chip assembly is provided.
  • An embodiment of the present disclosure provides a method of preparing a semiconductor chip assembly, comprising: forming a first layer on a surface of a substrate; forming a second layer on a surface of a semiconductor chip, in which one of the first and second layers has an opening therein; and connecting the first and second layers by eutectic bonding.
  • An embodiment of the present disclosure provides a semiconductor chip assembly, comprising: a semiconductor chip; a substrate; a first layer formed on a surface of the substrate; and a second layer formed on a surface of the semiconductor chip and connected to the first layer by eutectic bonding, in which one of the first and second layers has an opening therein.
  • an opening is formed in one of the first and second layers, so that a uniform eutectic layer may be formed between the first and second layers, thus increasing the bonding force between the semiconductor chip and the substrate greatly and improving the connection therebetween.
  • Fig. 1 shows a conventional method of preparing a semiconductor chip assembly by eutectic bonding
  • Fig. 2 is a schematic view of a semiconductor chip formed with an adhesive layer and a buffer layer thereon according to an embodiment of the present disclosure
  • Fig. 3 is a schematic cross-sectional view of a semiconductor chip formed with a second layer having an opening therein according to an embodiment of the present disclosure
  • Fig. 4 is a schematic view of a substrate formed with a first layer thereon according to an embodiment of the present disclosure
  • Fig. 5 is a schematic cross-sectional view of a semiconductor chip assembly according to an embodiment of the present disclosure
  • Fig. 6 shows that a photoresist layer is formed on the buffer layer on the semiconductor chip shown in Fig. 2 according to an embodiment of the present disclosure
  • Fig. 7 shows that a laminated layer is formed on the buffer layer on the semiconductor chip shown in Fig. 6 according to an embodiment of the present disclosure
  • Fig. 8 shows that an opening is formed in the laminated layer by removing the photoresist layer on the semiconductor chip shown in Fig. 7 according to an embodiment of the present disclosure
  • Fig. 9 shows that at least one groove is formed in laminated layer on the semiconductor chip shown in Fig. 8 according to an embodiment of the present disclosure
  • Fig. 10 shows a semiconductor chip with an adhesive layer, a buffer layer and a laminated layer formed thereon according to another embodiment of the present disclosure
  • Fig. 11 shows that a protective layer is formed on the laminated layer on the semiconductor chip shown in Fig. 10 according to another embodiment of the present disclosure
  • Fig. 12 shows that a photoresist layer is formed the protective layer on the semiconductor chip shown in Fig. 11 according to another embodiment of the present disclosure
  • Fig. 13 shows that a window is formed in the protective layer on the semiconductor chip shown in Fig. 12 according to another embodiment of the present disclosure
  • Fig. 14 shows that an opening is formed in the laminated layer on the semiconductor chip shown in Fig. 13 and at least one groove is formed in the laminated layer according to another embodiment of the present disclosure.
  • Fig. 15 shows that the protective layer is removed from the laminated layer on the semiconductor chip shown in Fig. 14 according to another embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a method of preparing a semiconductor chip assembly.
  • the method comprises the steps of: forming a first layer 101 on a surface of a substrate 10; forming a second layer 200 on a surface of a semiconductor chip 20; and connecting the first and second layers 101, 200 by eutectic bonding, in which one of the first and second layers 101, 200 has an opening 205 therein.
  • an opening 205 is formed in one of the first and second layers 101, 200 before connecting the first and second layers 101, 200 by eutectic bonding.
  • the semiconductor chip 20 may be an LED chip.
  • a uniform eutectic layer may be formed between the first and second layerslOl, 200, thus increasing the bonding force between the semiconductor chip 20 and the substrate 10 greatly and improving the connection therebetween.
  • the one layer having the opening 205 therein may be prepared by forming an adhesive layer 201 on the surface of a corresponding one of the substrate 10 and the semiconductor chip 20; and forming a laminated layer on the adhesive layer 201, in which the opening 205 is formed in and penetrates through the laminated layer.
  • At least one groove 2051 is formed in a wall of the opening 205 and extended along a circumferential direction of the opening 205.
  • the groove 2051 is an annular groove and extends continuously along the circumferential direction.
  • the groove 2051 may not be continuous in the circumferential direction.
  • a plurality of grooves 2051 are formed in the wall of the opening and the plurality of grooves 2051 are spaced from each other in the depth direction of the opening 205.
  • a buffer layer 202 is formed on the adhesive layer 201 and the laminated layer is formed on the buffer layer 202.
  • Figs. 2-5 illustrate the flow chart of a method of preparing the semiconductor chip assembly according to an embodiment of the present disclosure.
  • the opening 205 is formed in the second layer 200 on the semiconductor chip 20, and the second layer 200 may connect with the first layer 101 on the substrate 10 to form the eutectic layer (not shown). Alternatively, the opening 205 may be formed in the first layer 101 on the substrate 10.
  • an adhesive layer 201 is formed on the semiconductor chip 20 and a buffer layer 202 is formed on the adhesive layer 201.
  • the adhesive layer 201 may be formed on a surface (the upper surface in Fig.2) of the semiconductor chip 20.
  • the adhesive layer 201 may be formed by at least one selected from the group consisting of: Si, Ti, and Cr.
  • the adhesive layer 201 may have a thickness of about 0.02 microns to about 0.2 microns.
  • the adhesive layer 201 may be formed by any method known in the art, such as vacuum evaporation, sputtering, electroplating, or chemical plating.
  • the buffer layer 202 may be formed on the adhesive layer 201.
  • the buffer layer 202 may be formed by at least one selected from the group consisting of: Au, Ag, and Cu.
  • the buffer layer 202 may have a thickness of about 0.05 microns to about 1 micron.
  • the buffer layer 202 may be formed by any method known in the art, such as vacuum evaporation, sputtering, electroplating, or chemical plating.
  • the second layer 200 with the opening 205 is formed on the buffer layer 202.
  • a laminated layer is formed by forming a first metal layer 203 and a second metal layer 204 on the buffer layer 202 alternately.
  • two first metal layers 203 and two second metal layers 204 are shown on the buffer layer 202, in which the first metal layer 203 is contacted with the buffer layer 202 and the uppermost layer is the second metal layer 204.
  • the present disclosure is not limited to this.
  • the first metal layer 203 may be formed by a metal with a low melting point, such as at least one selected from the group consisting of: Sn, Bi, Cd, Pb, and Se.
  • the second metal layer 204 may be formed by at least one selected from the group consisting of: Au, Ag, and Cu.
  • the first and second metal layers 203, 204 each may have a thickness of about 0.1 microns to about 2 microns, and may be prepared by any method known in the art, such as vacuum evaporation, sputtering, electroplating, or chemical plating.
  • a first layer 101 is formed on a surface (the upper surface in Fig. 4) of a substrate 10.
  • the first layer 101 may be formed by a metal with a low melting point, such as at least one selected from the group consisting of: Sn, Bi, Cd, Pb, and Se.
  • the first layer 101 may have a thickness of about 0.1 microns to about 2 microns, and may be formed by any method known in the art, such as vacuum evaporation, sputtering, electroplating, or chemical plating.
  • a semiconductor chip assembly according to an embodiment of the present disclosure is shown.
  • the semiconductor chip assembly is formed by connecting the first layer 101 on the substrate
  • the eutectic bonding may be performed by: heating and pressurizing the first layer 101 and the second layer 200 under a pressure of about 10 grams to about 500 grams at a temperature of about 250°C to about 500°C for about 0.5 seconds to about 100 seconds.
  • a uniform eutectic layer (not shown) may be formed by the first layer 101 and the second metal layer 204 or the first metal layer 203 via eutectic boding.
  • the eutectic bonding can be used not only for connecting the semiconductor chip 20 and the substrate 10, but also for connecting a flip chip and a substrate.
  • the one layer such as the second layer 200 having the opening 205 therein may be prepared by forming the adhesive layer 201 on the surface of the semiconductor chip 20 and forming the laminated layer (comprising the first and second metal layers 203 and 204) on the adhesive layer 201, in which the opening 205 is formed in and penetrates through the laminated layer.
  • the opening 205 may be formed by removing a part of the laminated layer in the thickness direction thereof.
  • the groove 2051 is formed by removing a part of the wall of the opening 205 along the radial direction of the opening 205.
  • Fig. 5 shows one opening 205 and two grooves 2051.
  • the present disclosure is not limited to this.
  • Figs. 6-9 show the steps of forming the one layer having the opening 205 therein according to one embodiment.
  • the opening layer 205 is formed in the second layer 200.
  • the present disclosure is not limited to this.
  • the one layer having the opening 205 therein may be prepared by: forming the buffer layer 202 on the adhesive layer 201 which is formed on the semiconductor chip 20; forming a photoresist layer 210 on a part of the surface of the buffer layer 202; forming the laminated layer comprising at least one first metal layer 203 and at least one second metal layer 204 on the remaining part of the surface of the buffer layer 202; removing the photoresist layer 210 to form the opening 205 in the first metal layer 203 and the second metal layer 204 ; and forming the groove 2501 by etching a part of the wall using an etching solution.
  • at least one annular groove 2051 is formed in the wall of the opening 205 and extended along a circumferential direction of the opening 205.
  • the adhesive layer 201 is formed on the semiconductor chip 20 and the buffer layer 202 is formed on the adhesive layer 201.
  • the photoresist layer 210 is formed on a part of the surface of the buffer layer 202.
  • the photoresist layer 210 may have a thickness of more than 6 microns, and may have a column shape with a rectangular cross section. As shown in Fig. 6, only one photoresist layer 210 is shown, however, the present disclosure is not limited to this. There may be more photoresist layers 210 formed on the buffer layer 202. If there are a plurality of photoresist layers 210, a plurality of openings 205 may be formed in the laminated layer accordingly.
  • the laminated layer comprising at least one first metal layer 203 and at least one second metal layer 204 may be formed on the remaining part of the surface of the buffer layer 202, as shown in Fig. 7.
  • the laminated layer may comprise 3-10 first metal layers 203 and 3-10 second metal layers 204 formed alternately so as to subsequently form a uniform eutectic layer with the first layer 101 formed on the substrate 10.
  • the photoresist layer 210 may be removed from the buffer layer 202 to form the opening 205 in the laminated layer, as shown in Fig. 8.
  • a part of the wall of the opening 205 may be etched using an etching solution to form the groove 2051 in the laminated layer, as shown in Fig. 9.
  • the etching solution may be any one known in the art, such as at least one selected from the group consisting of: hydrochloric acid, nitric acid, sulfuric acid, and phosphoric acid.
  • the etching solution etches the first metal layer 203 but does not etch the buffer layer 202 and the second metal layer 204.
  • the groove 2051 is annular and extended in the circumferential direction of the opening 205.
  • two grooves 2051 are formed in the wall of the opening 205.
  • the present disclosure is not limited to this.
  • the first layer is formed on the substrate 10, then the first layer 101 on the substrate 10 is connected with the second layer 200 (i.e. the second metal layer 204) on the semiconductor chip 20 via eutectic bonding, so that a uniform eutectic layer (not shown) is formed between the first layer 101 and the second metal layer 204, thus connecting the substrate 10 and the semiconductor chip 20. Because of the opening 205, the eutectic layer is uniform and the bonding force is large, so that the connection strength between the substrate 10 and the semiconductor chip 20 is strong and reliable.
  • Figs. 10-15 show the steps of forming the one layer having the opening 205 therein according to another embodiment.
  • the one layer having the opening 205 therein may be prepared by: forming the laminated layer comprising at least one first metal layer 203 and at least one second metal layer 204 on the buffer layer 202, in which the buffer layer 202 is formed on the adhesive layer 201 on the semiconductor chip 20; forming a protective layer 220 on the laminated layer; performing photoetching on the protective layer 220 to form a window 2201 in the protective layer 220; forming the opening 205 and the groove 2051 by etching the first and second metal layers 203, 204 using an etching solution through the window in the protective layer 220; and removing the protective layer 220.
  • the adhesive layer 201 is formed on the semiconductor chip 20 and the buffer layer 202 is formed on the adhesive layer 201.
  • the protective layer 220 may be formed on the laminated layer formed by alternately forming the first and second metal layers 203, 204 on the buffer layer 202.
  • the protective layer 220 may be a Si0 2 or S1 3 N 4 layer.
  • a photoresist layer 230 may be formed on the protective layer 220, with at least one through hole 2301 formed in the photoresist layer 230, as shown in Fig. 12. In Fig. 12, only one through hole 2301 is shown in the photoresist layer 230.
  • An etching solution may be applied into the through hole (s) 2301 in the photoresist layer 230 to form a window 2201 in the protective layer 220, then the photoresist layer 230 may be removed, as shown in Fig. 13.
  • the etching solution may be a BOE solution which is a mixture of ammonium fluoride and hydrofluoric acid.
  • the laminated layer is etched by the etching solution via the window 2201 to form the opening 205 in the laminated layer, as shown in Fig. 14.
  • the etching solution may etch a part of the wall of the opening 205 to form at least one groove 2051 in the laminated layer, as shown in Fig. 14.
  • the etching solution may etch the first metal layer 203, but may not etch the buffer layer 202 and the second metal layer 204.
  • the etching solution may be aqua regia.
  • the protective layer 220 may be removed to form the second layer 200 (i.e. the second metal layer 204) having the opening 205, as shown in Fig. 15.
  • the removing may be performed using the BOE solution.
  • the second layer 200 having the opening 205 on the semiconductor chip 20 may finally connect with the first layer 101 on the substrate 10 by eutectic bonding.
  • metal atoms in the first layer 101 may be evenly diffused into the opening 205 and the groove 2051 in the second layer 200, so that a uniform eutectic layer is formed, thus enhancing the bonding force between the substrate 10 and the semiconductor chip 20.
  • the semiconductor chip assembly may comprise: the semiconductor chip 20; the substrate 10; the first layer 101 formed on a surface of the substrate 10; and the second layer 200 formed on a surface of the semiconductor chip 20 and connected to the first layer 101 by eutectic bonding.
  • One of the first and second layers has an opening therein before connecting the first layer 101 and the second layer 200.
  • the second layer having the opening 205 may comprise the adhesive layer 201, the buffer layer 202, and the laminated layer.
  • the opening 205 may be formed in and penetrates through the laminated layer.
  • the laminated layer may comprise at least one first metal layer 203 and at least one second metal layer 204 formed alternately on the buffer layer 202, particularly 3-10 first metal layer 203 and 3-10 second metal layer 204 formed alternately. Therefore, the finally manufactured semiconductor chip assembly may have a uniform eutectic layer formed between the semiconductor chip 20 and the substrate 10.
  • the first metal layer 203 may be formed by at least one selected from the group consisting of: Sn, Bi, Cd, Pb, and Se
  • the second metal layer 204 may be formed by at least one selected from the group consisting of: Au, Ag and Cu.
  • the first layer 101 may be formed by at least one selected from the group consisting of: Sn, Bi, Cd, Pb, and Se.
  • the opening 205 may be formed in the first layer 101.
  • the opening 205 may be formed in both the first and second layers 101, 200.
  • the first layer 101 may be formed on the semiconductor chip 20, and the second layer 200 may be formed on the substrate 10, then the first and second layers 101, 200 may be connected by eutectic bonding to form the eutectic layer between the semiconductor chip 20 and the substrate 10, thus forming the semiconductor chip assembly.
  • the second layer having an opening formed on the semiconductor chip may connect with the first layer on the substrate to form a uniform eutectic layer, thus increasing the bonding force between the semiconductor chip and the substrate greatly and improving the strength and reliability of the connection between the semiconductor chip and substrate.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Led Devices (AREA)

Abstract

A semiconductor chip assembly and a method for forming the same are provided. The semiconductor chip assembly comprises: a semiconductor chip (20), a substrate (10), a first layer (203) formed on a surface of the substrate (10), in which one of the first layer (203) and the second layer (204) has an opening (205) therein; and a second layer (204) formed on a surface of the semiconductor chip (20) and connected to the first layer (203) by eutectic bonding.

Description

SEMICONDUCTOR CHIP ASSEMBLY AND METHOD OF PREPARING THE SAME
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to, and benefits of Chinese Patent Application No. 201010261581.6 filed with State Intellectual Property Office, P. R. C. on August 21, 2010, the entire content of which is incorporated herein by reference.
FIELD
The present disclosure relates to a semiconductor chip, more particularly to a semiconductor chip assembly and a method of preparing the same.
BACKGROUD
Conventionally, a substrate and a semiconductor chip in a light emitting diode (LED) are commonly connected by: coating an adhesive (silver colloid, silica gel, gelatin, etc.) on the substrate and subsequently placing a semiconductor chip on the adhesive. In this way, the semiconductor chip may be bonded to the substrate after the adhesive is solidified. However, due to low thermal conductivity of the adhesive, the heat generated within the assembled semiconductor chip may not be transmitted outside from the semiconductor chip effectively. Therefore, the reliability of the semiconductor chip may be reduced.
To improve the reliability of the semiconductor chip, the semiconductor chip is connected to the substrate by eutectic bonding. That is, a eutectic material with high thermal conductivity is coated on a surface of the substrate and another eutectic material with high thermal conductivity is coated on a surface of the semiconductor chip, and the eutectic materials are heated and pressurized at a predetermined temperature under a predetermined pressure to form a eutectic layer connecting the substrate and the semiconductor chip. Fig. 1 shows a conventional method of preparing a semiconductor chip assembly by eutectic bonding. As shown in Fig. 1, the method comprises the steps of: forming a first eutectic material layer 11 on a surface of a substrate 1; forming a second eutectic material layer 21 on a surface of a semiconductor chip 2; connecting the first eutectic material layer 11 and the second eutectic material layer 21 by eutectic bonding at a temperature of 300 °C under a pressure of 50 grams to form a eutectic layer 3 between the substrate 1 and the semiconductor chip 2. However, the bonding force between the first and second layers is weak, so that connection between the substrate and the semiconductor chip is poor and unreliable.
SUMMARY
In viewing thereof, the present disclosure is directed to solve at least one of the problems existing in the prior art. Accordingly, a semiconductor chip assembly is provided with strong bonding force between the substrate and the semiconductor chip. Furthermore, a method of preparing the semiconductor chip assembly is provided.
An embodiment of the present disclosure provides a method of preparing a semiconductor chip assembly, comprising: forming a first layer on a surface of a substrate; forming a second layer on a surface of a semiconductor chip, in which one of the first and second layers has an opening therein; and connecting the first and second layers by eutectic bonding.
An embodiment of the present disclosure provides a semiconductor chip assembly, comprising: a semiconductor chip; a substrate; a first layer formed on a surface of the substrate; and a second layer formed on a surface of the semiconductor chip and connected to the first layer by eutectic bonding, in which one of the first and second layers has an opening therein.
With the semiconductor chip assembly and the method for forming the same according to embodiments of the present disclosure, an opening is formed in one of the first and second layers, so that a uniform eutectic layer may be formed between the first and second layers, thus increasing the bonding force between the semiconductor chip and the substrate greatly and improving the connection therebetween.
Additional aspects and advantages of the embodiments of the present disclosure will be given in part in the following descriptions, become apparent in part from the following descriptions, or be learned from the practice of the embodiments of the present disclosure. BRIEF DISCRIPTION OF THE DRAWINGS
These and other aspects and advantages of the present disclosure will become apparent and more readily appreciated from the following descriptions taken in conjunction with the drawings in which:
Fig. 1 shows a conventional method of preparing a semiconductor chip assembly by eutectic bonding;
Fig. 2 is a schematic view of a semiconductor chip formed with an adhesive layer and a buffer layer thereon according to an embodiment of the present disclosure;
Fig. 3 is a schematic cross-sectional view of a semiconductor chip formed with a second layer having an opening therein according to an embodiment of the present disclosure;
Fig. 4 is a schematic view of a substrate formed with a first layer thereon according to an embodiment of the present disclosure;
Fig. 5 is a schematic cross-sectional view of a semiconductor chip assembly according to an embodiment of the present disclosure;
Fig. 6 shows that a photoresist layer is formed on the buffer layer on the semiconductor chip shown in Fig. 2 according to an embodiment of the present disclosure;
Fig. 7 shows that a laminated layer is formed on the buffer layer on the semiconductor chip shown in Fig. 6 according to an embodiment of the present disclosure;
Fig. 8 shows that an opening is formed in the laminated layer by removing the photoresist layer on the semiconductor chip shown in Fig. 7 according to an embodiment of the present disclosure;
Fig. 9 shows that at least one groove is formed in laminated layer on the semiconductor chip shown in Fig. 8 according to an embodiment of the present disclosure;
Fig. 10 shows a semiconductor chip with an adhesive layer, a buffer layer and a laminated layer formed thereon according to another embodiment of the present disclosure;
Fig. 11 shows that a protective layer is formed on the laminated layer on the semiconductor chip shown in Fig. 10 according to another embodiment of the present disclosure;
Fig. 12 shows that a photoresist layer is formed the protective layer on the semiconductor chip shown in Fig. 11 according to another embodiment of the present disclosure;
Fig. 13 shows that a window is formed in the protective layer on the semiconductor chip shown in Fig. 12 according to another embodiment of the present disclosure;
Fig. 14 shows that an opening is formed in the laminated layer on the semiconductor chip shown in Fig. 13 and at least one groove is formed in the laminated layer according to another embodiment of the present disclosure; and
Fig. 15 shows that the protective layer is removed from the laminated layer on the semiconductor chip shown in Fig. 14 according to another embodiment of the present disclosure.
DETAILED DISCRIPTION Reference will be made in detail to embodiments of the present disclosure. The embodiments described herein are explanatory, illustrative, and used to generally understand the present disclosure. The embodiments shall not be construed to limit the present disclosure. The same or similar elements and the elements having same or similar functions are denoted by like reference numerals throughout the descriptions.
Embodiments of the present disclosure provide a method of preparing a semiconductor chip assembly. The method comprises the steps of: forming a first layer 101 on a surface of a substrate 10; forming a second layer 200 on a surface of a semiconductor chip 20; and connecting the first and second layers 101, 200 by eutectic bonding, in which one of the first and second layers 101, 200 has an opening 205 therein. In other words, an opening 205 is formed in one of the first and second layers 101, 200 before connecting the first and second layers 101, 200 by eutectic bonding.
In one embodiment, the semiconductor chip 20 may be an LED chip.
Since the opening 205 is formed in one of the first and second layers 101, 200, a uniform eutectic layer may be formed between the first and second layerslOl, 200, thus increasing the bonding force between the semiconductor chip 20 and the substrate 10 greatly and improving the connection therebetween.
In one embodiment, the one layer having the opening 205 therein may be prepared by forming an adhesive layer 201 on the surface of a corresponding one of the substrate 10 and the semiconductor chip 20; and forming a laminated layer on the adhesive layer 201, in which the opening 205 is formed in and penetrates through the laminated layer.
In some embodiments, at least one groove 2051 is formed in a wall of the opening 205 and extended along a circumferential direction of the opening 205. Advantageously, the groove 2051 is an annular groove and extends continuously along the circumferential direction. Alternatively, the groove 2051 may not be continuous in the circumferential direction. More advantageously, a plurality of grooves 2051 are formed in the wall of the opening and the plurality of grooves 2051 are spaced from each other in the depth direction of the opening 205.
In a further embodiment, a buffer layer 202 is formed on the adhesive layer 201 and the laminated layer is formed on the buffer layer 202.
Figs. 2-5 illustrate the flow chart of a method of preparing the semiconductor chip assembly according to an embodiment of the present disclosure.
In an embodiment shown in Figs. 2-5, the opening 205 is formed in the second layer 200 on the semiconductor chip 20, and the second layer 200 may connect with the first layer 101 on the substrate 10 to form the eutectic layer (not shown). Alternatively, the opening 205 may be formed in the first layer 101 on the substrate 10.
As shown in Fig. 2, an adhesive layer 201 is formed on the semiconductor chip 20 and a buffer layer 202 is formed on the adhesive layer 201.
Firstly, the adhesive layer 201 may be formed on a surface (the upper surface in Fig.2) of the semiconductor chip 20. The adhesive layer 201 may be formed by at least one selected from the group consisting of: Si, Ti, and Cr. The adhesive layer 201 may have a thickness of about 0.02 microns to about 0.2 microns. The adhesive layer 201 may be formed by any method known in the art, such as vacuum evaporation, sputtering, electroplating, or chemical plating.
Then, the buffer layer 202 may be formed on the adhesive layer 201. The buffer layer 202 may be formed by at least one selected from the group consisting of: Au, Ag, and Cu. The buffer layer 202 may have a thickness of about 0.05 microns to about 1 micron. The buffer layer 202 may be formed by any method known in the art, such as vacuum evaporation, sputtering, electroplating, or chemical plating.
As shown in Fig. 3, the second layer 200 with the opening 205 is formed on the buffer layer 202. A laminated layer is formed by forming a first metal layer 203 and a second metal layer 204 on the buffer layer 202 alternately. As shown in Fig. 3, two first metal layers 203 and two second metal layers 204 are shown on the buffer layer 202, in which the first metal layer 203 is contacted with the buffer layer 202 and the uppermost layer is the second metal layer 204. However, the present disclosure is not limited to this.
The first metal layer 203 may be formed by a metal with a low melting point, such as at least one selected from the group consisting of: Sn, Bi, Cd, Pb, and Se. The second metal layer 204 may be formed by at least one selected from the group consisting of: Au, Ag, and Cu.
In one embodiment, there may be 3-10 first metal layers 203 and 3-10 second metal layers
204 which are formed alternately. The first and second metal layers 203, 204 each may have a thickness of about 0.1 microns to about 2 microns, and may be prepared by any method known in the art, such as vacuum evaporation, sputtering, electroplating, or chemical plating.
As shown in Fig. 4, a first layer 101 is formed on a surface (the upper surface in Fig. 4) of a substrate 10. The first layer 101 may be formed by a metal with a low melting point, such as at least one selected from the group consisting of: Sn, Bi, Cd, Pb, and Se. The first layer 101 may have a thickness of about 0.1 microns to about 2 microns, and may be formed by any method known in the art, such as vacuum evaporation, sputtering, electroplating, or chemical plating.
As shown in Fig. 5, a semiconductor chip assembly according to an embodiment of the present disclosure is shown.
The semiconductor chip assembly is formed by connecting the first layer 101 on the substrate
10 with the second layer 200 on the semiconductor chip 20 via eutectic bonding. The eutectic bonding may be performed by: heating and pressurizing the first layer 101 and the second layer 200 under a pressure of about 10 grams to about 500 grams at a temperature of about 250°C to about 500°C for about 0.5 seconds to about 100 seconds. In this way, a uniform eutectic layer (not shown) may be formed by the first layer 101 and the second metal layer 204 or the first metal layer 203 via eutectic boding. In an embodiment of the present disclosure, the eutectic bonding can be used not only for connecting the semiconductor chip 20 and the substrate 10, but also for connecting a flip chip and a substrate.
In one embodiment, the one layer such as the second layer 200 having the opening 205 therein may be prepared by forming the adhesive layer 201 on the surface of the semiconductor chip 20 and forming the laminated layer (comprising the first and second metal layers 203 and 204) on the adhesive layer 201, in which the opening 205 is formed in and penetrates through the laminated layer.
The opening 205 may be formed by removing a part of the laminated layer in the thickness direction thereof. The groove 2051 is formed by removing a part of the wall of the opening 205 along the radial direction of the opening 205. Fig. 5 shows one opening 205 and two grooves 2051. However, the present disclosure is not limited to this.
Figs. 6-9 show the steps of forming the one layer having the opening 205 therein according to one embodiment. In the following description, the opening layer 205 is formed in the second layer 200. However, the present disclosure is not limited to this.
In one embodiment, the one layer having the opening 205 therein may be prepared by: forming the buffer layer 202 on the adhesive layer 201 which is formed on the semiconductor chip 20; forming a photoresist layer 210 on a part of the surface of the buffer layer 202; forming the laminated layer comprising at least one first metal layer 203 and at least one second metal layer 204 on the remaining part of the surface of the buffer layer 202; removing the photoresist layer 210 to form the opening 205 in the first metal layer 203 and the second metal layer 204 ; and forming the groove 2501 by etching a part of the wall using an etching solution. In one embodiment, at least one annular groove 2051 is formed in the wall of the opening 205 and extended along a circumferential direction of the opening 205.
Particularly, as shown in Fig. 6, the adhesive layer 201 is formed on the semiconductor chip 20 and the buffer layer 202 is formed on the adhesive layer 201. The photoresist layer 210 is formed on a part of the surface of the buffer layer 202. The photoresist layer 210 may have a thickness of more than 6 microns, and may have a column shape with a rectangular cross section. As shown in Fig. 6, only one photoresist layer 210 is shown, however, the present disclosure is not limited to this. There may be more photoresist layers 210 formed on the buffer layer 202. If there are a plurality of photoresist layers 210, a plurality of openings 205 may be formed in the laminated layer accordingly.
The laminated layer comprising at least one first metal layer 203 and at least one second metal layer 204 may be formed on the remaining part of the surface of the buffer layer 202, as shown in Fig. 7. The laminated layer may comprise 3-10 first metal layers 203 and 3-10 second metal layers 204 formed alternately so as to subsequently form a uniform eutectic layer with the first layer 101 formed on the substrate 10.
The photoresist layer 210 may be removed from the buffer layer 202 to form the opening 205 in the laminated layer, as shown in Fig. 8.
A part of the wall of the opening 205 may be etched using an etching solution to form the groove 2051 in the laminated layer, as shown in Fig. 9. The etching solution may be any one known in the art, such as at least one selected from the group consisting of: hydrochloric acid, nitric acid, sulfuric acid, and phosphoric acid. In the embodiment shown in Fig. 9, the etching solution etches the first metal layer 203 but does not etch the buffer layer 202 and the second metal layer 204. In some embodiments of the present disclosure, the groove 2051 is annular and extended in the circumferential direction of the opening 205. In addition, two grooves 2051 are formed in the wall of the opening 205. However, the present disclosure is not limited to this.
As described above, the first layer is formed on the substrate 10, then the first layer 101 on the substrate 10 is connected with the second layer 200 (i.e. the second metal layer 204) on the semiconductor chip 20 via eutectic bonding, so that a uniform eutectic layer (not shown) is formed between the first layer 101 and the second metal layer 204, thus connecting the substrate 10 and the semiconductor chip 20. Because of the opening 205, the eutectic layer is uniform and the bonding force is large, so that the connection strength between the substrate 10 and the semiconductor chip 20 is strong and reliable.
Figs. 10-15 show the steps of forming the one layer having the opening 205 therein according to another embodiment.
In another embodiment, the one layer having the opening 205 therein may be prepared by: forming the laminated layer comprising at least one first metal layer 203 and at least one second metal layer 204 on the buffer layer 202, in which the buffer layer 202 is formed on the adhesive layer 201 on the semiconductor chip 20; forming a protective layer 220 on the laminated layer; performing photoetching on the protective layer 220 to form a window 2201 in the protective layer 220; forming the opening 205 and the groove 2051 by etching the first and second metal layers 203, 204 using an etching solution through the window in the protective layer 220; and removing the protective layer 220.
Particularly, as shown in Fig. 10, the adhesive layer 201 is formed on the semiconductor chip 20 and the buffer layer 202 is formed on the adhesive layer 201.
As shown in Fig. 11, the protective layer 220 may be formed on the laminated layer formed by alternately forming the first and second metal layers 203, 204 on the buffer layer 202. In one embodiment, the protective layer 220 may be a Si02 or S13N4 layer.
A photoresist layer 230 may be formed on the protective layer 220, with at least one through hole 2301 formed in the photoresist layer 230, as shown in Fig. 12. In Fig. 12, only one through hole 2301 is shown in the photoresist layer 230.
An etching solution may be applied into the through hole (s) 2301 in the photoresist layer 230 to form a window 2201 in the protective layer 220, then the photoresist layer 230 may be removed, as shown in Fig. 13.
A part of the laminated layer is exposed through the window 2201 in the protective layer 220. The etching solution may be a BOE solution which is a mixture of ammonium fluoride and hydrofluoric acid.
Optionally, the laminated layer is etched by the etching solution via the window 2201 to form the opening 205 in the laminated layer, as shown in Fig. 14.
The etching solution may etch a part of the wall of the opening 205 to form at least one groove 2051 in the laminated layer, as shown in Fig. 14. The etching solution may etch the first metal layer 203, but may not etch the buffer layer 202 and the second metal layer 204. Advantageously, the etching solution may be aqua regia.
The protective layer 220 may be removed to form the second layer 200 (i.e. the second metal layer 204) having the opening 205, as shown in Fig. 15. The removing may be performed using the BOE solution.
The second layer 200 having the opening 205 on the semiconductor chip 20 may finally connect with the first layer 101 on the substrate 10 by eutectic bonding. During eutectic bonding, metal atoms in the first layer 101 may be evenly diffused into the opening 205 and the groove 2051 in the second layer 200, so that a uniform eutectic layer is formed, thus enhancing the bonding force between the substrate 10 and the semiconductor chip 20.
The semiconductor chip assembly according to embodiments of the present disclosure will be described.
Return to Fig. 5, the semiconductor chip assembly may comprise: the semiconductor chip 20; the substrate 10; the first layer 101 formed on a surface of the substrate 10; and the second layer 200 formed on a surface of the semiconductor chip 20 and connected to the first layer 101 by eutectic bonding. One of the first and second layers has an opening therein before connecting the first layer 101 and the second layer 200.
In one embodiment, the second layer having the opening 205 may comprise the adhesive layer 201, the buffer layer 202, and the laminated layer. The opening 205 may be formed in and penetrates through the laminated layer. The laminated layer may comprise at least one first metal layer 203 and at least one second metal layer 204 formed alternately on the buffer layer 202, particularly 3-10 first metal layer 203 and 3-10 second metal layer 204 formed alternately. Therefore, the finally manufactured semiconductor chip assembly may have a uniform eutectic layer formed between the semiconductor chip 20 and the substrate 10.
In one embodiment, the first metal layer 203 may be formed by at least one selected from the group consisting of: Sn, Bi, Cd, Pb, and Se, and the second metal layer 204 may be formed by at least one selected from the group consisting of: Au, Ag and Cu.
In one embodiment, the first layer 101 may be formed by at least one selected from the group consisting of: Sn, Bi, Cd, Pb, and Se.
In a further embodiment, the opening 205 may be formed in the first layer 101. Alternatively, the opening 205 may be formed in both the first and second layers 101, 200.
In one embodiment, the first layer 101 may be formed on the semiconductor chip 20, and the second layer 200 may be formed on the substrate 10, then the first and second layers 101, 200 may be connected by eutectic bonding to form the eutectic layer between the semiconductor chip 20 and the substrate 10, thus forming the semiconductor chip assembly.
With the semiconductor chip assembly and the method for forming the same according to embodiments of the present disclosure, the second layer having an opening formed on the semiconductor chip may connect with the first layer on the substrate to form a uniform eutectic layer, thus increasing the bonding force between the semiconductor chip and the substrate greatly and improving the strength and reliability of the connection between the semiconductor chip and substrate.
Although the present disclosure have been described in detail with reference to several embodiments, additional variations and modifications exist within the scope and spirit as described and defined in the following claims.

Claims

WHAT IS CLAIMED IS:
1. A method of preparing a semiconductor chip assembly comprising:
forming a first layer on a surface of a substrate;
forming a second layer on a surface of a semiconductor chip, in which one of the first and second layers has an opening therein; and
connecting the first and second layers by eutectic bonding.
2. The method according to claim 1, wherein the one layer having the opening therein of the first and second layers is prepared by:
forming an adhesive layer on the surface of a corresponding one of the substrate and the semiconductor chip; and
forming a laminated layer on the adhesive layer,
wherein the opening is formed in and penetrates through the laminated layer.
3. The method according to claim 2, wherein at least one groove is formed in a wall of the opening and extended along a circumferential direction of the opening
4. The method according to claim 3, wherein a buffer layer is formed on the adhesive layer and the laminated layer is formed on the buffer layer.
5. The method according to claim 4, wherein the laminated layer is prepared by:
forming a photoresist layer on a part of a surface of the buffer layer;
forming a first metal layer and a second metal layer alternately on the remaining part of the surface of the buffer layer;
removing the photoresist layer to form the opening in the first metal layer and the second metal layer; and
forming the groove by etching a part of the wall of the opening using an etching solution.
6. The method according to claim 4, wherein the laminated layer is prepared by:
forming a first metal layer and a second metal layer alternately on a surface of the buffer layer;
forming a protective layer on the first metal layer and the second metal layer;
forming a photoresist layer on the protective layer;
performing photoetching on the protective layer to form a window in the protective layer; forming the opening and the groove by etching the first and second metal layers using an etching solution through the window in the protective layer; and
removing the protective layer.
7. The method according to claim 5 or 6, wherein the first metal layer is formed by at least one selected from the group consisting of: Sn, Bi, Cd, Pb, and Se; and the second metal layer is formed by at least one selected from the group consisting of: Au, Ag and Cu.
8. The method according to claim 7, wherein the other layer of the first and second layers is formed by at least one selected from the group consisting of: Sn, Bi, Cd, Pb, and Se.
9. The method according to claim 4, wherein the buffer layer is formed by at least one selected from the group consisting of: Au, Ag, and Cu.
10. The method according to any of claims 2 to 6, wherein the adhesive layer is formed by at least one selected from the group consisting of: Si, Ti, and Cr.
11. The method according to any of claims 1 to 6, wherein the eutectic bonding is performed by heating and pressurizing the first and second layers under a pressure of about 10 grams to about 500 grams at a temperature of about 250°C to about 500°C for about 0.5 seconds to about 100 seconds.
12. A semiconductor chip assembly comprising:
a semiconductor chip;
a substrate;
a first layer formed on a surface of the substrate; and
a second layer formed on a surface of the semiconductor chip and connected to the first layer by eutectic bonding,
wherein one of the first and second layers has an opening therein.
13. The semiconductor chip assembly according to claim 12, wherein the one layer of the first and second layers comprises: an adhesive layer, a buffer layer formed on the adhesive layer, and a laminated layer formed on the buffer layer, wherein the opening is formed in and penetrates through the laminated layer.
14. The semiconductor chip assembly according to claim 12, wherein at least one groove is formed in a wall of the opening and extended along a circumferential direction of the opening.
15. The semiconductor chip assembly according to any of claims 12 to 14, wherein the semiconductor chip is an LED chip.
PCT/CN2011/078491 2010-08-21 2011-08-16 Semiconductor chip assembly and method of preparing the same WO2012025024A1 (en)

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