CN108305838B - Low-temperature chip mounting method and chip mounting structure without organic matters - Google Patents
Low-temperature chip mounting method and chip mounting structure without organic matters Download PDFInfo
- Publication number
- CN108305838B CN108305838B CN201710022374.7A CN201710022374A CN108305838B CN 108305838 B CN108305838 B CN 108305838B CN 201710022374 A CN201710022374 A CN 201710022374A CN 108305838 B CN108305838 B CN 108305838B
- Authority
- CN
- China
- Prior art keywords
- particles
- chip
- nanometer
- micrometers
- connecting layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
Abstract
The present disclosure relates to a low temperature chip mounting method and chip mounting structure without organic matter, the method comprising: depositing a connecting layer on the surface of the chip, and pasting the chip and a to-be-connected piece through the connecting layer; or depositing the connecting layer on the surface of the to-be-connected piece, and mounting the to-be-connected piece and the chip through the connecting layer; or depositing the connecting layer on the surfaces of the chip and the to-be-connected piece, and mounting the chip and the to-be-connected piece. The chip mounting method disclosed by the invention can realize low-temperature connection and high-temperature service of the mounting structure, and organic matters do not exist in the mounting structure formed in the sintering process and after sintering, so that the adverse effect of the organic matters on the chip mounting process and the overall performance of the mounting structure is eliminated.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to a low-temperature chip mounting method and a chip mounting structure without organic matters.
Background
Die attach (die attach) is one of the key steps in semiconductor device manufacturing. In recent years, the integration degree of an IC device is continuously increased, the overall volume of the device tends to be reduced, and higher energy density and more severe thermal management problems are brought about; the power capacity of power semiconductor devices is also increasing and is increasingly required to be used in severe operating situations above 300 ℃; with the research and development and application of new-generation semiconductor devices such as SiC-based and GaN-based semiconductors, it is still a development trend in the future to further improve the chip operating junction temperature and the device power density in order to fully exert the excellent material characteristics of such wide bandgap semiconductors. The traditional low-melting-point lead-based chip mounting material obviously cannot meet the use requirements of devices at higher temperature and higher energy density.
In order to improve the performance of the semiconductor device/module at high temperature, the bottleneck of insufficient high-temperature service performance of the existing mounting material needs to be broken through. On the other hand, too high chip mounting temperature can cause potential damage to some temperature sensitive devices in the semiconductor module, and can also cause larger residual stress due to different thermal expansion coefficients of the connecting material and the substrate, thereby influencing the mechanical property of the connecting layer. Thus, researchers have been working on developing die attach materials and/or methods that can meet both low temperature bonding and high temperature service requirements.
Currently, the mainstream technical route for chip mounting which can realize low-temperature connection and high-temperature service is as follows: a low-temperature instantaneous liquid phase diffusion connection technology and a micro-nano particle soldering paste low-temperature sintering technology. For the low-temperature transient liquid phase diffusion connection technology, long connection and post-treatment time is needed for homogenization of connection structure, and hard and brittle intermetallic compounds are easily formed in joints, so that the long-term use performance of the device is affected.
Compared with a low-temperature transient liquid phase diffusion connection technology, the micro-nano particle soldering paste connection technology has the advantages of short welding time, less brittle phases in joints and the like, shows more excellent electric conduction, heat conduction and mechanical properties than the traditional surface mounting material at high temperature, and is applied in practice. However, the micro-nano particle solder paste technology needs to use various organic substances as a dispersant (such as grease, polyacrylic acid, and the like), a binder (such as polyvinyl alcohol, wax, and the like), and a diluent (such as terpineol, and the like) of the micro-nano particles, and the presence of the organic substances has more negative effects on the chip mounting process and the joint performance: in the die attach process, additional time is required for volatilization of organic matters in the solder paste, and a significant decomposition process of the organic matters in the solder paste generally needs to be performed above a certain temperature (generally at least 180 ℃), which limits further reduction of the die attach temperature. After mounting, the organic matter near the center of the chip in the solder paste is decomposed and escaped due to the difficulty of reaching the edge of the chip, and remains in the joint for large chipArea (10 x 10 mm)2Above), the residue of organic matter is more obvious. Since organic substances are not conductive per se and have poor thermal conductivity and mechanical properties, the presence of these organic substances reduces the electrical conductivity, thermal conductivity and mechanical properties of the joint. Because of the adverse effects of organic matters in the solder paste on chip mounting, a low-temperature chip mounting method and a corresponding chip mounting structure without organic matters are urgently needed.
Disclosure of Invention
The chip mounting method can realize low-temperature connection and high-temperature service of the mounting structure, and organic matters do not exist in the mounting structure formed in the sintering process and after sintering, so that the adverse effect of the organic matters on the chip mounting process and the overall performance of the mounting structure is eliminated.
In order to achieve the above object, the present disclosure provides a low temperature chip mounting method without organic matter, the method including: depositing a connecting layer on the surface of the chip, and pasting the chip and a to-be-connected piece through the connecting layer; or depositing the connecting layer on the surface of the to-be-connected piece, and mounting the to-be-connected piece and the chip through the connecting layer; or depositing the connecting layer on the surfaces of the chip and the to-be-connected piece, and pasting the to-be-connected piece and the chip through the connecting layer; wherein the connection layer comprises pure metal particles and/or alloy particles, with or without ceramic particles, and without organic matter; the sizes of the pure metal particles, the alloy particles and the ceramic particles are respectively 1 nanometer to 50 micrometers.
Optionally, the to-be-connected component is a ceramic substrate, a lead frame, a printed circuit board or a strip.
Optionally, each of the pure metal particles, the alloy particles, and the ceramic particles is at least one selected from the group consisting of spherical particles, linear particles, plate-shaped particles, polyhedral particles, and irregular particles.
Optionally, the particle size of the spherical particles is 1 nanometer to 50 micrometers; the linear particles have a linear diameter of 1 nanometer to 50 micrometers and a length of 1 nanometer to 50 micrometers; the thickness of the flaky particles is 1 nanometer to 50 micrometers, and the length of the flaky particles is 1 nanometer to 50 micrometers; the length of the longest side of the polyhedral particle is 1 nanometer to 50 micrometers.
Optionally, the connection layer is flocculent, clustered, porous or film-shaped.
Optionally, the thickness of the connecting layer is 1-1000 microns, and the porosity is 0-95%.
Optionally, the material of the pure metal particles is copper, aluminum, titanium, nickel, silver, gold, tin or indium, the material of the alloy particles is at least two selected from copper, aluminum, titanium, nickel, silver, gold, tin and indium, and the material of the ceramic particles is at least one selected from boron oxide, silicon dioxide, aluminum oxide, magnesium oxide, zirconium oxide, silicon nitride, aluminum nitride, gallium nitride, boron nitride, titanium nitride, boron carbide, silicon carbide, titanium carbide and titanium boride; wherein the metal element having a bulk melting point of 600 ℃ or higher accounts for 50 wt% or more of the total weight of the joining layer.
Optionally, the deposition mode is at least one selected from pulsed laser deposition, molecular beam epitaxy, magnetron sputtering, ion plating, vacuum evaporation, chemical vapor deposition, electroplating, and a template method.
Optionally, the mounting enables a connection interface between particles inside the connection layer, a connection interface between the connection layer and the to-be-connected component, and a connection interface between the connection layer and the chip to form a metallurgical bond, and the forming means is at least one selected from solid-phase sintering, liquid-phase sintering, soldering, and diffusion welding.
Optionally, the mounting temperature is room temperature-400 ℃, and the pressure is 0-100 MPa.
The disclosure also provides a chip mounting structure, which comprises a chip, a to-be-connected piece and a connecting layer mounted between the chip and the to-be-connected piece; wherein the connection layer comprises pure metal particles and/or alloy particles, with or without ceramic particles, and without organic matter; the sizes of the pure metal particles, the alloy particles and the ceramic particles are respectively 1 nanometer to 50 micrometers.
Optionally, the to-be-connected component is a ceramic substrate, a lead frame, a printed circuit board or a strip.
Optionally, each of the pure metal particles, the alloy particles, and the ceramic particles is at least one selected from the group consisting of spherical particles, linear particles, plate-shaped particles, polyhedral particles, and irregular particles.
Optionally, the particle size of the spherical particles is 1 nanometer to 50 micrometers; the linear particles have a linear diameter of 1 nanometer to 50 micrometers and a length of 1 nanometer to 50 micrometers; the thickness of the flaky particles is 1 nanometer to 50 micrometers, and the length of the flaky particles is 1 nanometer to 50 micrometers; the length of the longest side of the polyhedral particle is 1 nanometer to 50 micrometers.
Optionally, the pure metal particles are made of copper, aluminum, titanium, nickel, silver, gold, tin or indium, the purity of the pure metal particles is more than 99 wt%, the alloy particles are made of at least two selected from copper, aluminum, titanium, nickel, silver, gold, tin and indium, and the ceramic particles are made of at least one selected from boron oxide, silicon dioxide, aluminum oxide, magnesium oxide, zirconium oxide, silicon nitride, aluminum nitride, gallium nitride, boron nitride, titanium nitride, boron carbide, silicon carbide, titanium carbide and titanium boride; wherein the metal element having a bulk melting point of 600 ℃ or higher accounts for 50 wt% or more of the total weight of the joining layer.
The connecting piece composed of the micro-nano particles is adopted for mounting the chip and the to-be-connected piece, and due to the small size effect and the surface effect, the connecting temperature can be reduced, and low-temperature connection is realized; in addition, as the main component forming the connecting layer is high-melting-point metal, after the connecting layer is mounted by a proper process, the mounting structure joint which forms metallurgical bonding has the property of certain block metal, so that the connecting layer has good high-temperature service performance; meanwhile, the micro-nano structure connecting layer does not contain soldering paste or organic matters, so that compared with a soldering paste method, chip mounting can further shorten the soldering time, reduce the soldering temperature and reduce the porosity of the joint, thereby improving the electrical conductivity, the thermal conductivity and the mechanical property of the joint. The micro-nano structure connecting layer prepared by adopting the deposition technology has accurate, controllable, tidy and uniform boundary dimensions, the phenomenon of solder paste overflow in the chip mounting process by using a solder paste method is avoided, and the process stability is guaranteed; meanwhile, the patterned deposition of the micro-nano structure connecting layer can be realized through the mask, and the applicability of the method is improved.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
FIG. 1 is a schematic flow diagram of a first embodiment of the disclosed method (downward arrow indicates pressurization, wavy line indicates heating, the same applies below).
Fig. 2 is a Scanning Electron Microscope (SEM) image of the connection layer composed of nanoparticles obtained in example 1 of the present disclosure.
FIG. 3 is a schematic flow chart of a second embodiment of the disclosed method.
FIG. 4 is a schematic flow chart of a third embodiment of the method of the present disclosure.
FIG. 5 is a schematic flow chart of a fourth embodiment of the method of the present disclosure.
Fig. 6 is a schematic flow chart of a fifth embodiment of the disclosed method.
Description of the reference numerals
1 chip 2 copper-clad ceramic substrate 3 silver nano-particles
4 copper silver alloy nanoparticles 5 tin nanoparticles 6 ceramic nanoparticles
7 strips
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
The connecting material adopted by the existing low-temperature chip mounting method contains more organic matters, the organic matters can be removed only by needing enough temperature and time during mounting, and certain organic matters still remain in the mounting structure after the mounting is finished, so that the overall electrical conductivity, thermal conductivity and mechanical property of the mounting structure are influenced. To this end, the present disclosure provides a low temperature chip mounting method without organic matter, the method comprising: depositing a connecting layer on the surface of the chip, and pasting the chip and a to-be-connected piece through the connecting layer; or depositing the connecting layer on the surface of the to-be-connected piece, and mounting the to-be-connected piece and the chip through the connecting layer; or depositing the connecting layer on the surfaces of the chip and the to-be-connected piece, and pasting the to-be-connected piece and the chip through the connecting layer; the to-be-connected piece can be a ceramic substrate, a lead frame, a printed circuit board and a strip. Before mounting, the connecting layer is a film with certain porosity, the film is composed of pure metal particles and/or alloy particles, and includes or does not include ceramic particles and organic matters; the sizes of the pure metal particles, the alloy particles and the ceramic particles are respectively 1 nanometer to 50 micrometers, and preferably 1 nanometer to 500 nanometers. After the mounting is finished, the particles in the connecting layer and the particles and the surfaces to be connected form joints with metallurgical bonding.
The chip mounting method is adopted to carry out chip mounting, organic matters are not contained in the mounting structure in the mounting process and after the mounting is finished, the adverse effect of the organic matters on the overall performance of the mounting process and the mounting structure can be avoided, the size of the connecting layer deposited by the deposition method is accurate and controllable, and graphical deposition can be realized.
The connection layer is a film with certain porosity, and the film is composed of particles, can be one kind of particles, and can also be various kinds of particles, such as single pure metal particles, pure metal particles and alloy particles, pure metal particles and ceramic particles, and the like. The ceramic particles can adjust the thermal expansion coefficient of the connecting layer, improve the matching degree of the thermal expansion coefficient of the connecting layer and the to-be-connected piece, and improve the thermal reliability of the surface mounting structure. Pure metals, alloys and ceramics and their materials are well known to those skilled in the art, for example, the material of the pure metal particles may be copper, aluminum, titanium, nickel, silver, gold, tin or indium, the material of the alloy particles may be at least two selected from copper, aluminum, titanium, nickel, silver, gold, tin and indium, the material of the ceramic particles may be at least one selected from boron oxide, silicon dioxide, aluminum oxide, magnesium oxide, zirconium oxide, silicon nitride, aluminum nitride, gallium nitride, boron nitride, titanium nitride, boron carbide, silicon carbide, titanium carbide and titanium boride, and others may be used by those skilled in the art, and the disclosure will not be repeated. The metal element with the melting point of more than 600 ℃ preferably accounts for more than 50 wt% of the total weight of the connecting layer, and the high-temperature service performance of the surface mounting structure is improved. The melting point of the metal element means the melting point of the bulk metal simple substance, and for example, the melting point of copper is 1083.4 ℃.
The term "particles" in the present disclosure means geometric bodies having a specific shape in the range of 1 nm to 50 μm, for example, the pure metal particles, the alloy particles and the ceramic particles are each at least one selected from the group consisting of spherical particles, linear particles, plate-shaped particles, polyhedral particles and irregular particles, which refer to a combination of particles having a plurality of shapes, so that it is difficult to describe with one single shape.
The "size of particles" in the present disclosure refers to the size of particles, such as the diameter of spherical particles, the length and wire diameter of linear particles, the thickness and length of flaky particles, etc., and the present disclosure is not particularly limited to specific values of the particle size as long as it is in the range of 1 nm to 50 μm, for example, the particle diameter (diameter) of the spherical particles may be 1 nm to 50 μm; the linear particles can have a linear diameter (diameter) of 1 nm to 50 microns and a length of 1 nm to 50 microns; the thickness of the flaky particles can be 1 nanometer to 50 micrometers, and the length of the flaky particles can be 1 nanometer to 50 micrometers; the length of the longest side of the polyhedral particle may be 1 nm to 50 μm.
According to the present disclosure, the connection layer is attached to the surface of the chip and the to-be-connected component, which may be a ceramic substrate, a lead frame, a printed circuit board, or a strip, by deposition, which is well known to those skilled in the art, and may be, for example, at least one selected from pulsed laser deposition, molecular beam epitaxy, magnetron sputtering, ion plating, vacuum evaporation, chemical vapor deposition, electroplating, chemical wet process, and template process. The morphology of the tie layer may vary depending on the deposition method and conditions, for example, the tie layer may be flocculent, clustered, porous or thin film, the thickness of the tie layer may be 1 to 1000 μm, and the porosity may be 0 to 95%.
According to the present disclosure, the term "mounting" refers to the metallurgical bonding between the surfaces to be mounted, which are bonded together by the interatomic bonding action between the chip and the connection layer, between the particles in the connection layer, and between the members to be connected and the connection layer, in a certain atmosphere, at a certain temperature and pressure by the input of external energy. The means of metallurgical bond formation may be at least one selected from the group consisting of solid phase sintering, liquid phase sintering, brazing and diffusion welding. For example, the temperature is room temperature to 400 ℃, the pressure is 0 to 100 MPa, the atmosphere of argon, helium, nitrogen, hydrogen, oxygen or carbon dioxide, and the pressure is 10 DEG-4And pressing the connecting layer on the chip or the to-be-connected piece under the condition of Pa-atmospheric pressure, wherein the heat preservation time can be 1-240 minutes, so as to finish the mounting.
The present disclosure also provides a chip mounting structure, comprising a chip, a to-be-connected member, and a connection layer between the chip and a substrate; the to-be-connected piece can be a ceramic substrate, a lead frame, a printed circuit board and a strip. Before mounting, the connecting layer is a film with certain porosity, the film is composed of pure metal particles and/or alloy particles, and includes or does not include ceramic particles and organic matters; the sizes of the pure metal particles, the alloy particles and the ceramic particles are respectively 1 nanometer to 50 micrometers, and preferably 1 nanometer to 500 nanometers. After the mounting is finished, metallurgical bonding is formed between the particles in the connecting layer and between the particles and the surface to be connected.
The connection layer is a film with certain porosity, and the film is composed of particles, can be one kind of particles, and can also be various kinds of particles, such as single pure metal particles, pure metal particles and alloy particles, pure metal particles and ceramic particles, and the like. The ceramic particles can adjust the thermal expansion coefficient of the connecting layer, improve the matching degree of the thermal expansion coefficient of the connecting layer and the to-be-connected piece, and improve the thermal reliability of the surface mounting structure. Metals, alloys, and ceramics and materials thereof are well known to those skilled in the art, for example, the material of the metal particles may be copper, aluminum, titanium, nickel, silver, gold, tin, or indium, the material of the alloy particles may be at least two selected from copper, aluminum, titanium, nickel, silver, gold, tin, and indium, the material of the ceramic particles may be at least one selected from boron oxide, silicon dioxide, aluminum oxide, magnesium oxide, zirconium oxide, silicon nitride, aluminum nitride, gallium nitride, boron nitride, titanium nitride, boron carbide, silicon carbide, titanium carbide, and titanium boride, and others may be used by those skilled in the art, and the disclosure will not be repeated. Among them, the metal element having a melting point of 600 ℃ or higher is preferably 50% by weight or more based on the total weight of the joining layer. The melting point of the metal element means the melting point of the bulk metal simple substance, and for example, the melting point of copper is 1083.4 ℃.
The term "particle" in the present disclosure means a geometric body having a specific shape in the range of 1 nm to 50 μm, for example, the pure metal particles, the alloy particles and the ceramic particles are each at least one selected from the group consisting of spherical particles, linear particles, plate-shaped particles, polyhedral particles and irregular particles, which means an aggregate of particles having a plurality of shapes, so that it is difficult to describe with one single shape.
The "size of particles" in the present disclosure refers to the size of particles, such as the diameter of spherical particles, the length and wire diameter of linear particles, the thickness and length of flaky particles, etc., and the present disclosure is not particularly limited to specific values of the size of particles as long as they are in the range of 1 nm to 50 μm, for example, the size of spherical particles may be 1 nm to 50 μm; the linear particle has a linear diameter of 1 nanometer to 50 micrometers and a length of 1 nanometer to 50 micrometers; the thickness of the flaky particles can be 1 nanometer to 50 micrometers, and the length of the flaky particles can be 1 nanometer to 50 micrometers; the length of the longest side of the polyhedral particle may be 1 nm to 50 μm.
The present disclosure is further illustrated by the following examples, but is not to be construed as being limited thereby.
The test conditions of the scanning electron microscope in the embodiment of the disclosure are as follows: zeiss EVO MA10, germany, acceleration voltage 15 kV.
Example 1
As shown in fig. 1, a connection layer composed of silver nanoparticles 3 is deposited on the bottom surface of a chip 1 by using the ultrafast pulsed laser deposition technique. The method specifically comprises the following steps: and depositing for 40 minutes under the working gas pressure of 1Pa argon by adopting a silver target material with the pulse width of 10Ps, the average power of 60W and the pulse frequency of 3MHz to obtain the connecting layer consisting of the silver nano particles 3. The thickness of the connecting layer was 45 μm and the porosity 25%. As shown in fig. 2, which is a top SEM image of the connection layer before mounting, the silver nanoparticles constituting the connection layer are spherical and have a diameter distribution of 10nm to 300 nm. And (3) mutually attaching the bottom surface of the chip 1 deposited with the silver nanoparticle 3 connecting layer and the upper surface of the copper-clad ceramic substrate 2. And carrying out solid-phase sintering at the mounting temperature of 200 ℃, the mounting pressure of 5MPa and the mounting time of 20 minutes, and cooling to room temperature to obtain the chip mounting structure forming metallurgical bonding.
If the soldering paste consisting of silver nanoparticles and organic matters is used for chip mounting, in order to avoid chip dislocation (during pressureless sintering) caused by one-time large-scale volatilization of the organic matters during sintering and difficulty in escape of the organic matters (during pressure sintering), the soldering paste is generally pre-dried for more than 40min at the temperature of below 250 ℃ so that a part of the organic matters are decomposed and escaped in advance; meanwhile, if the organic matter with high decomposition temperature in the solder paste is to be fully released, the final sintering temperature is not too low, and generally above 280 ℃. Therefore, by adopting the low-temperature chip mounting method provided by the disclosure, the sintering temperature can be further reduced, and the time of the whole sintering process is shortened. And organic matters do not exist in the mounting structure formed in the sintering process and after sintering, so that the adverse effect of the existence of the organic matters on the overall performance of the mounting structure can be avoided, and the influence of high-temperature sintering on the chip and the to-be-connected piece is reduced.
Example 2
As shown in fig. 3, a connection layer composed of silver-copper alloy nanoparticles 4 is deposited on the upper surface of the copper-clad ceramic substrate 2 by ultrafast pulsed laser deposition. The method specifically comprises the following steps: and replacing the target material with a silver-copper alloy target, depositing for 45 minutes under the working gas pressure of argon gas of 10Pa by using a laser pulse width of 10Ps, an average power of 60W and a pulse frequency of 3MHz, and obtaining the connecting layer consisting of silver-copper alloy nano particles 4. The thickness of the connecting layer is 40 μm, the porosity is 55%, the nanoparticles forming the connecting layer are spherical, the diameter is distributed between 10nm and 550nm, and the copper content in the copper-silver alloy nanoparticles is 30 wt%. And (3) mutually attaching the upper surface of the copper-clad ceramic substrate 2 deposited with the silver-copper alloy nanoparticle 4 connecting layer and the bottom surface of the chip 1. Under the nitrogen atmosphere, the chip mounting structure forming metallurgical bonding is obtained after cooling to room temperature at the mounting temperature of 300 ℃, the mounting pressure of 5MPa and the mounting time of 30 minutes, and the existence of copper in the mounting joint is favorable for improving the electromigration resistance of the joint.
Example 3
As shown in fig. 4, a connection layer composed of silver nanoparticles 3 and tin nanoparticles 5 is deposited on the bottom surface of the chip 1 and the upper surface of the copper-clad ceramic substrate 2 by ultrafast pulse laser deposition. The method specifically comprises the following steps: and (3) replacing the target material with a silver target and a tin target, depositing for 50 minutes under the working gas pressure of 10Pa argon by using laser pulse width of 10Ps, average power of 30W and pulse frequency of 3MHz, and obtaining the connecting layer consisting of silver nanoparticles 3 and tin nanoparticles 5. The thickness of the connecting layer is 35 μm, the porosity is 40%, the silver nanoparticles 3 and the tin nanoparticles 5 constituting the connecting layer are both spherical, the diameter is distributed between 10nm and 700nm, and the silver content in the connecting layer is 70 wt%. And (3) mutually attaching the bottom surface of the chip 1 deposited with the silver and tin nanoparticle connecting layer and the upper surface of the copper-clad ceramic substrate 2. Under the nitrogen atmosphere, the mounting temperature is 180 ℃, the mounting pressure is 1MPa, and the mounting time is 15 minutes. As the melting point (232 ℃) of the bulk tin is far lower than that (962 ℃) of the bulk silver, during the mounting process, the tin nano particles are melted or plastically flowed, which is beneficial to filling the pores in the connecting layer and promoting the sintering, diffusion and metallurgical reaction. And cooling to room temperature to obtain the chip mounting structure forming metallurgical bonding.
Example 4
As shown in fig. 5, a connection layer composed of silver nanoparticles 3 and ceramic nanoparticles 6 is deposited on the bottom surface of the chip 1 by ultrafast pulsed laser deposition. The method specifically comprises the following steps: and (3) replacing the target material with a silver target and a ceramic target (SiC), depositing for 45 minutes under the working gas pressure of 10Pa argon gas with the laser pulse width of 10Ps, the average power of 60W and the pulse frequency of 300KHz to obtain the connecting layer consisting of the silver nanoparticles 3 and the ceramic nanoparticles 6. The thickness of the connecting layer is 40 μm, the porosity is 35%, the nanoparticles forming the connecting layer are all spherical, the diameter is distributed between 10nm and 500nm, and the silver content in the connecting layer is 80 wt%. And (3) mutually attaching the bottom surface of the chip 1 deposited with the silver and ceramic nanoparticle connecting layer and the upper surface of the copper-clad ceramic substrate 2. The solid-phase sintering is carried out at the mounting temperature of 300 ℃, the mounting pressure of 10MPa and the mounting time of 30 minutes, and after the chip is cooled to room temperature, the chip mounting structure forming metallurgical bonding is obtained, and the existence of the ceramic reinforcing particles in the mounting joint is beneficial to improving the comprehensive mechanical property of the joint through the effects of second-phase reinforcement, joint linear expansion coefficient adjustment and the like.
Example 5
As shown in fig. 6, a connection layer composed of silver nanoparticles 3 is deposited on the top surface of the chip 1 and the upper surface of the copper-clad ceramic substrate 2 by using the ultrafast pulsed laser deposition technique. The method specifically comprises the following steps: and depositing for 40 minutes under the working gas pressure of 1Pa argon by adopting a silver target material with the pulse width of 10Ps, the average power of 60W and the pulse frequency of 3MHz to obtain the connecting layer consisting of the silver nano particles 3. The thickness of the connecting layer was 45 μm and the porosity was 40%. The silver nanoparticles forming the connecting layer are spherical and have a diameter ranging from 10nm to 300 nm. And (3) mutually attaching the upper surface of the copper-clad ceramic substrate 2 deposited with the silver nanoparticle 3 connecting layer and the bottom surface of the chip 1, and mutually attaching the top surface of the chip 1 deposited with the silver nanoparticle 3 connecting layer and the strip 7. And performing solid-phase sintering at the mounting temperature of 280 ℃, the mounting pressure of 10MPa and the mounting time of 30 minutes, and cooling to room temperature to obtain the chip mounting structure forming metallurgical bonding. Compared with the lead in the lead bonding, the strip in the mounting structure of the embodiment can reduce the packaging resistance, the thermal resistance and the packaging inductance, and has higher rated current capability and efficiency.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations will not be separately described in this disclosure.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (14)
1. An organic-free low-temperature chip mounting method, comprising:
depositing a connecting layer on the surface of the chip, and pasting the chip and a to-be-connected piece through the connecting layer; or
Depositing the connecting layer on the surface of the to-be-connected piece, and mounting the to-be-connected piece and the chip through the connecting layer; or
Depositing the connecting layers on the surfaces of the chip and the to-be-connected piece, and mounting the to-be-connected piece and the chip through the connecting layers;
wherein the connection layer comprises pure metal particles and/or alloy particles, with or without ceramic particles, and without organic matter; the sizes of the pure metal particles, the alloy particles and the ceramic particles are respectively 1 nanometer to 50 micrometers;
the connecting layer is flocculent, clustered or porous;
the temperature of the pasting is room temperature-400 ℃.
2. The method of claim 1, wherein the component to be connected is a ceramic substrate, a lead frame, a printed circuit board, or a strip.
3. The method according to claim 1, wherein the pure metal particles, alloy particles, and ceramic particles are each at least one selected from the group consisting of spherical particles, wire-shaped particles, plate-shaped particles, polyhedral-shaped particles, and irregular particles.
4. The method of claim 3, wherein the spherical particles have a particle size of 1 nanometer to 50 micrometers; the linear particles have a linear diameter of 1 nanometer to 50 micrometers and a length of 1 nanometer to 50 micrometers; the thickness of the flaky particles is 1 nanometer to 50 micrometers, and the length of the flaky particles is 1 nanometer to 50 micrometers; the length of the longest side of the polyhedral particle is 1 nanometer to 50 micrometers.
5. The method of claim 1, wherein the tie layer has a thickness of 1 to 1000 microns.
6. The method according to claim 1, wherein the material of the pure metal particles is copper, aluminum, titanium, nickel, silver, gold, tin or indium, the material of the alloy particles is at least two selected from copper, aluminum, titanium, nickel, silver, gold, tin and indium, and the material of the ceramic particles is at least one selected from boron oxide, silicon dioxide, aluminum oxide, magnesium oxide, zirconium oxide, silicon nitride, aluminum nitride, gallium nitride, boron nitride, titanium nitride, boron carbide, silicon carbide, titanium carbide and titanium boride; wherein the metal element having a bulk melting point of 600 ℃ or higher accounts for 50 wt% or more of the total weight of the joining layer.
7. The method of claim 1, wherein the deposition is by at least one selected from pulsed laser deposition, molecular beam epitaxy, magnetron sputtering, ion plating, vacuum evaporation, chemical vapor deposition, electroplating, and templating.
8. The method of claim 1, wherein the attaching metallurgically bonds a connection interface between the connection layer internal particles, a connection interface between the connection layer and the member to be connected, and a connection interface between the connection layer and the chip by at least one selected from the group consisting of solid phase sintering, liquid phase sintering, brazing, and diffusion welding.
9. The method according to claim 1 or 8, wherein the pressure of the mounting is 0 to 100 MPa.
10. A chip mounting structure comprises a chip, a to-be-connected piece and a connecting layer mounted between the chip and the to-be-connected piece; wherein the connection layer comprises pure metal particles and/or alloy particles, with or without ceramic particles, and without organic matter; the sizes of the pure metal particles, the alloy particles and the ceramic particles are respectively 1 nanometer to 50 micrometers; the connecting layer is flocculent, clustered or porous.
11. The chip mounting structure according to claim 10, wherein the to-be-connected member is a ceramic substrate, a lead frame, a printed circuit board, or a tape.
12. The die attach structure of claim 10, wherein the pure metal particles, alloy particles, and ceramic particles are each at least one selected from the group consisting of spherical particles, wire-like particles, flake particles, polyhedral particles, and irregular particles.
13. The die attach structure of claim 12, wherein the spherical particles have a particle size of 1 nanometer to 50 micrometers; the linear particles have a linear diameter of 1 nanometer to 50 micrometers and a length of 1 nanometer to 50 micrometers; the thickness of the flaky particles is 1 nanometer to 50 micrometers, and the length of the flaky particles is 1 nanometer to 50 micrometers; the length of the longest side of the polyhedral particle is 1 nanometer to 50 micrometers.
14. The chip mounting structure according to claim 10, wherein the material of the pure metal particles is copper, aluminum, titanium, nickel, silver, gold, tin, or indium, the material of the alloy particles is at least two selected from copper, aluminum, titanium, nickel, silver, gold, tin, and indium, and the material of the ceramic particles is at least one selected from boron oxide, silicon dioxide, aluminum oxide, magnesium oxide, zirconium oxide, silicon nitride, aluminum nitride, gallium nitride, boron nitride, titanium nitride, boron carbide, silicon carbide, titanium carbide, and titanium boride; wherein the metal element having a bulk melting point of 600 ℃ or higher accounts for 50 wt% or more of the total weight of the joining layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710022374.7A CN108305838B (en) | 2017-01-12 | 2017-01-12 | Low-temperature chip mounting method and chip mounting structure without organic matters |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710022374.7A CN108305838B (en) | 2017-01-12 | 2017-01-12 | Low-temperature chip mounting method and chip mounting structure without organic matters |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108305838A CN108305838A (en) | 2018-07-20 |
| CN108305838B true CN108305838B (en) | 2020-05-29 |
Family
ID=62871812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710022374.7A Active CN108305838B (en) | 2017-01-12 | 2017-01-12 | Low-temperature chip mounting method and chip mounting structure without organic matters |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108305838B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112440025B (en) * | 2019-09-02 | 2022-02-18 | 清华大学 | Double-sided micro-nano composite preformed soldering lug for electronic device and low-temperature interconnection method |
| CN110465670B (en) * | 2019-09-12 | 2022-03-04 | 哈尔滨工业大学 | Method for preparing layered composite material by spark plasma sintering |
| CN112185889B (en) * | 2020-09-22 | 2022-09-20 | 北京航空航天大学 | Method for connecting chip by metal soldering lug with micro-nano structure on surface |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024717A (en) * | 2010-08-21 | 2011-04-20 | 比亚迪股份有限公司 | Eutectic method and eutectic structure of semiconductor chip |
| CN104588905A (en) * | 2014-11-27 | 2015-05-06 | 哈尔滨工业大学 | Ag-Cu-Ti/Sn nano-particle soldering paste and preparation method thereof |
| CN104862701A (en) * | 2015-05-11 | 2015-08-26 | 哈尔滨工业大学 | Method for fast preparing high-temperature service total IMC microscale solder joint through multi-layer micron and submicron film |
| CN105070693A (en) * | 2015-09-14 | 2015-11-18 | 北京科技大学 | Low-temperature-connected high-temperature-resistant encapsulation connecting material and encapsulation connecting technology thereof |
| CN105304512A (en) * | 2014-07-28 | 2016-02-03 | 西门子公司 | Method used for manufacturing power module, and power module |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002009236A (en) * | 2000-06-21 | 2002-01-11 | Shinko Electric Ind Co Ltd | Multiple layer semiconductor device and its manufacturing method |
-
2017
- 2017-01-12 CN CN201710022374.7A patent/CN108305838B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024717A (en) * | 2010-08-21 | 2011-04-20 | 比亚迪股份有限公司 | Eutectic method and eutectic structure of semiconductor chip |
| CN105304512A (en) * | 2014-07-28 | 2016-02-03 | 西门子公司 | Method used for manufacturing power module, and power module |
| CN104588905A (en) * | 2014-11-27 | 2015-05-06 | 哈尔滨工业大学 | Ag-Cu-Ti/Sn nano-particle soldering paste and preparation method thereof |
| CN104862701A (en) * | 2015-05-11 | 2015-08-26 | 哈尔滨工业大学 | Method for fast preparing high-temperature service total IMC microscale solder joint through multi-layer micron and submicron film |
| CN105070693A (en) * | 2015-09-14 | 2015-11-18 | 北京科技大学 | Low-temperature-connected high-temperature-resistant encapsulation connecting material and encapsulation connecting technology thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108305838A (en) | 2018-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3217424B1 (en) | Electroconductive assembly for electronic component, semiconductor device in which said assembly is used, and method for manufacturing electroconductive assembly | |
| JP5156658B2 (en) | Electronic components for LSI | |
| CN108847395B (en) | Preparation and packaging method of presintered nano-network silver film for low-temperature quick connection | |
| TWI624356B (en) | Metal joint structure using metal nanoparticle, metal joint method, and metal joint material | |
| JP2017514995A (en) | Low pressure sintering powder | |
| JP2006352080A (en) | Semiconductor device and its manufacturing method | |
| CN108305838B (en) | Low-temperature chip mounting method and chip mounting structure without organic matters | |
| CN108666297B (en) | Low-temperature electronic interconnection material, preparation method thereof and low-temperature electronic interconnection method | |
| KR102248760B1 (en) | Bonding composition and bonding method using the same | |
| WO2019088285A1 (en) | Heat sink-equipped power module substrate and manufacturing method for heat sink-equipped power module substrate | |
| CN114043123A (en) | Nano copper soldering paste and application thereof in chip packaging interconnection structure | |
| WO2015029152A1 (en) | Semiconductor device | |
| Zhang et al. | Effects of sintering pressure on the densification and mechanical properties of nanosilver double-side sintered power module | |
| JP2012038790A (en) | Electronic member and electronic component and manufacturing method thereof | |
| WO2017150096A1 (en) | Semiconductor device | |
| JP6170045B2 (en) | Bonding substrate and manufacturing method thereof, semiconductor module using bonding substrate, and manufacturing method thereof | |
| JP6070092B2 (en) | Power module and method for manufacturing power module | |
| KR101929750B1 (en) | Bonding paste for high temperature applications and bonding method using the in situ formation of fine Ag bumps | |
| Zhang et al. | Thermal properties of silver nanoparticle sintering bonding paste for high-power led packaging | |
| JP2017152638A (en) | Junction structure, electronic component including junction structure, and formation method of junction structure | |
| Deng et al. | Bonding below 150 C using nano-ag film for power electronics packaging | |
| CN111033703A (en) | Mounting structure and nanoparticle mounting material | |
| Zhang et al. | Development of Silver Paste with High Sintering Driving Force for Reliable Packaging of Power Electronics | |
| Sakamoto et al. | Low temperature die-bonding with Ag flakes | |
| CN114473110B (en) | Electromigration-resistant and oxidation-resistant soldering paste and application thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |