CN101897010A - 形成具有低栅电阻的沟槽栅晶体管的结构及方法 - Google Patents

形成具有低栅电阻的沟槽栅晶体管的结构及方法 Download PDF

Info

Publication number
CN101897010A
CN101897010A CN2008801206235A CN200880120623A CN101897010A CN 101897010 A CN101897010 A CN 101897010A CN 2008801206235 A CN2008801206235 A CN 2008801206235A CN 200880120623 A CN200880120623 A CN 200880120623A CN 101897010 A CN101897010 A CN 101897010A
Authority
CN
China
Prior art keywords
groove
tagma
dielectric
gate
source region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2008801206235A
Other languages
English (en)
Inventor
潘南西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of CN101897010A publication Critical patent/CN101897010A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种场效应晶体管包括在第二导电类型的半导体区上方的第一导电类型的体区，使得该体区与半导体区形成p-n结。沟槽延伸穿过体区并在半导体区中终止。第二导电类型的源区在邻近沟槽的体区上方延伸，使得该源区与体区形成p-n结。栅极介电层衬于每个沟槽的侧壁。金属衬里衬于每个沟槽中的栅极介电层。包含金属材料的栅电极设置在每个沟槽中。

Description

形成具有低栅电阻的沟槽栅晶体管的结构及方法
相关申请
本申请要求于2007年12月14日提交的美国临时申请第61/013985号的权益，其全部内容结合于此供参考。
技术领域
本发明总体上涉及半导体技术，并且更具体地涉及具有低栅电阻的沟槽栅(槽栅，trench gate)场效应晶体管(FET)以及形成其的方法。
背景技术
一般，n-沟槽栅功率(n-沟道槽栅功率，n-channel trench-gatepower)MOSFET包括n-型衬底，其上形成有n-型外延层。衬底包括有(embody)MOSFET的漏极(drain)。p-型体区延伸到外延层中。沟槽延伸穿过体区并进入由体区和衬底界定的外延层的部分(通常称为漂移区)。栅极介电层形成在每个沟槽的侧壁和底部上。源区在沟槽的侧面。重体区形成在相邻源区之间的体区中。栅电极(例如，由多晶硅制成)填充沟槽并包括有MOSFET的栅极。介质盖(dielectric cap)覆盖沟槽并且部分地在源区上延伸。顶侧金属层电接触源区和重体区。底侧金属层接触衬底。
已经良好记载了由于在这样的沟槽栅晶体管以及它们的屏蔽栅极变型中的栅电阻降低导致晶体管性能提高。然而，至今提出的用于降低栅电阻的技术取得的成功很有限。因此，对于低栅电阻沟槽化栅晶体管以及用于形成这样的晶体管的方法存在需要。
发明内容
根据本发明的一个实施方式，一种场效应晶体管包括在第二导电类型的半导体区上方的第一导电类型的体区，使得该体区与半导体区形成p-n结。沟槽延伸穿过体区并在半导体区中终止。第二导电类型的源区在邻近沟槽的体区上方延伸，使得源区与体区形成p-n结。栅极介电层衬于(内衬于或作为...的内衬，line)每个沟槽的侧壁。金属衬里衬于每个沟槽中的栅极介电层。包含金属材料的栅电极设置在每个沟槽中。
在一个实施方式中，接触开口(contact opening)延伸到在相邻沟槽之间的体区中。第一导电类型的重体区沿着每个接触开口的底部在每个体区中延伸。互联层(interconnect layer)填充每个接触开口，并沿接触开口的侧壁直接接触源区。
在另一实施方式中，源区的顶表面完全被介质盖材料覆盖，使得互联层仅沿接触开口的侧壁与源区直接接触。
在另一实施方式中，栅极介电层包括高-k电介质。
在另一实施方式中，每个沟槽进一步包括设置在栅电极下方的屏蔽电极。栅电极和屏蔽电极通过电极间介电层彼此绝缘。
在另一实施方式中，每个沟槽进一步包括沿着在栅电极下方的沟槽的底部延伸的厚底介电。
根据本发明的另一实施方式，一种形成场效应晶体管的方法包括在第二导电类型的半导体区中形成第一导电类型的体区，使得体区与半导体区形成p-n结。形成延伸到半导体区中的沟槽。在邻近沟槽的体区上方形成第二导电类型的源区，使得源区与体区形成p-n结。形成衬于每个沟槽侧壁的栅极介电层。形成衬于每个沟槽中的栅极介电层的金属衬里。在每个沟槽中形成金属栅电极。
在一个实施方式中，该方法进一步包括形成延伸到在相邻沟槽之间的体区中的接触开口。形成沿着每个接触开口的底部在每个体区中延伸的第一导电类型的重体区。形成填充每个接触开口且沿接触开口的侧壁直接接触源区的互联层。
在另一实施方式中，形成完全覆盖源区的顶表面的介质盖材料，以使互联层仅沿接触开口的侧壁直接接触源区。
在另一实施方式中，栅极介电层包括高-k电介质。
在另一实施方式中，在形成栅电极之前：形成衬于每个沟槽的下侧壁和底部的屏蔽介电层；在每个沟槽的下部分中形成屏蔽电极；以及在屏蔽电极方法的每个沟槽中形成电极间介电层。
在另一实施方式中，在形成金属栅电极之前：在每个沟槽中形成多晶硅栅极材料；以及从每个沟槽中去除多晶硅栅极材料。
在另一实施方式中，金属材料包括钨。
在另一实施方式中，金属栅电极在形成体区之后形成。
附图说明
图1A-1F是简化的剖视图，示出了根据本发明一个实施方式的用于形成屏蔽栅极沟槽MOSFET的示例性方法；
图2是简化的剖视图，示出了根据本发明一个实施方式的示例性沟槽栅功率MOSFET；以及
图3是对应于图2中的示例性剖视图，并且提供用于示出根据本发明一个实施方式的沟槽和各种其他区的轮廓的更准确表示。
具体实施方式
根据本发明的实施方式，描述了涉及集成电路和它们的加工技术。更具体地，在一些实施方式中，功率场效应晶体管(FET)包括金属栅电极，以相比于传统多晶硅栅极有利地显著降低栅电阻。公开了一种简单的工艺技术，其中在不使用任何掩蔽步骤的情况下，根据常规技术在沟槽中形成的多晶硅栅电极被去除并用金属栅电极替代。在不需要额外的掩蔽步骤的情况下，用于去除并用金属栅极代替多晶(硅)栅极的简单工艺步骤能够容易地与用于形成功率MOSFET的现有工艺集成。仅通过实例的方式，根据本发明的技术已被应用于沟槽功率MOSFET，但是本发明具有更宽得多的应用范围。例如，根据本发明的技术能够应用于槽栅IGBT，并且一般地能够应用于可以从这样的技术中受益的任何半导体器件。以下将详细描述这些技术。
图1A-1F是简化的剖视图，示出了根据本发明一个实施方式的用于形成具有金属栅极的屏蔽栅极沟槽MOSFET的示例性方法。在图1A中，外延层110利用已知技术形成在衬底100上方。衬底100可以例如是硅衬底、III-V族化合物衬底、硅/锗(SiGe)衬底、epi-衬底(磊晶硅衬底，epi-substrate)、绝缘体上硅(silicon-on-insulator，SOI)衬底、显示器衬底(如液晶显示器(LCD)、等离子体显示器、电发光(EL)灯显示器或发光二级管(LED)衬底)。示出的实施方式是一种n-沟槽MOSFET，并且衬底100和外延层110可以包括n-型掺杂剂如磷、砷和/或其他的第V族元素。
P-型体区125可以形成在外延层110中或上方。在一些实施方式中，体区125可以通过在外延层110中植入掺杂剂而形成。在其他实施方式中，体区125可以通过在外延层110上方的外延工艺而形成。延伸穿过体区125并且在由体区125和衬底100界定的外延层110的区域内终止的沟槽102利用常规技术形成。由体区125和衬底100界定的外延层10的的区域通常称为漂移区。衬于沟槽102底部与下侧壁的屏蔽介电层101利用常规工艺形成。屏蔽电极113(例如包括掺杂或未掺杂多晶硅)利用已知技术形成在沟槽102的底部中。
在屏蔽电极113上方延伸的电极间电介质103(例如包括氧化物)利用常规技术形成在沟槽102中。衬于上沟槽侧壁的栅极介电层115(例如，包括氧化物)根据已知技术形成。在一些实施方式至，栅极介电层115比屏蔽介电层101薄。栅电极120(例如包括掺杂或未掺杂多晶硅)利用常规方法形成在沟槽102的上部分中。N-型源区130利用已知技术形成在邻近沟槽102的体区125中。在一些实施方式中，体区125可以在形成沟槽102之前形成。可替换地，可以在形成沟槽102和其中的各种区和层之后形成体区125和源区130。在源区130上方延伸的介电层116可以在形成栅极介电层115的同时形成。较薄的介电层在栅电极120上方延伸。
尽管图1A-1F仅仅示出一个沟槽102并且该结构看起来是不对称的，但是应该理解，本文所示出的和所描述的剖视图对应的设计是一种基于单元的设计，其中一个单元重复多次以形成完整器件。
在图1B中，去除工艺135完全将介电层从栅电极120上方除去。去除工艺135可以包括干蚀刻工艺和/或湿蚀刻工艺。在一些实施方式中，栅电极120上的介电层是一个氧化层并且去除工艺135是利用氟化氢(HF)溶液的湿蚀刻工艺。去除工艺135还可以去除源区130上方的介电层116的一部分。然而，介电层116比栅电极120上方的介电层厚，使得在去除工艺135之后保留的介电层116的一部分116a仍完全覆盖源区130。在去除工艺135中没有使用掩膜。
在图1C中，去除工艺140基本上去除栅电极。在一些实施方式中，去除工艺140可以包括干蚀刻和/或湿蚀刻。在栅电极120包含多晶硅的情况下，去除工艺140可以利用溴化氢(HBr)溶液以去除多晶(硅)栅极120。去除工艺140可以是选择性蚀刻工艺，由此可完全去除多晶硅栅电极120同时不影响介电层115和116a。
在图1D中，形成了衬于栅极介电层115的金属衬里155、电极间介电层103以及介电层116a。金属衬里155有利地防止金属离子扩散到栅极介电层中。金属衬里155可以通过例如CVD工艺、PVD工艺、其他薄膜工艺或它们的各种组合形成。衬里155可以包括例如钛(Ti)层、氮化钛(TiN)层、钽(Ta)层、氮化钽(TaN)层、或与栅极介电层115适当地形成界面的其他材料。在一个实施方式中，在形成金属衬里155之前，实施热工艺以提高栅极介电层115的质量。例如，可以使用在氧气环境中的高温处理。可替换地，可在栅极介电层115上方形成适于与金属衬里155形成界面的第二介电层。在又一实施方式中，在形成衬里155之前，可完全去除栅极介电层115(通常包括氧化物)并在其位置中形成高-k介电层。
将高-k电介质作为栅极介电层的使用在多个方面可以是有利的。首先，金属栅极与高-k电介质比氧化物更相容。其次，高-k电介质使得能够使用更薄的栅极介电层，这降低了晶体管阈值电压，从而导致改善的Rdson(导通电阻)。高-k电介质可以是氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、硅酸铪(HfSiO4)、氧化锆(ZrO2)、氮氧化锆(ZrON)、硅酸锆(ZrSiO4)、氧化钇(Y2O3)、氧化镧(La2O3)、氧化铈(CeO2)、氧化钛(TiO2)、(氧化钽(Ta2O5)或它们的任意组合中的一种或多种。高-k介电层可以通过例如化学气相沉积(CVD)工艺、物理气相沉积(PVD)工艺、或用于形成高-k材料层的其他已知工艺形成。
在图1D中，然后形成金属填充材料160以填充沟槽102。金属填充材料160可以包括：例如Ru、Ti、Ta、W、Hf、Cu、Al；金属氮化物堆叠栅极；金属氧化物栅极如RuO2或IrO2；金属氮化物栅极如MoN、WN、TiN；栅极硅化物如CoSi2或NiSi；或者它们的各种组合。在一些实施方式中，金属层160可以通过CVD工艺、PVD工艺、电化学镀工艺、非电镀工艺或它们的各种组合而形成。
在图1E中，使用去除工艺165以使金属填充材料160凹入在沟槽102中的金属衬里155。由此形成替代多晶硅栅电极120的金属栅电极160a。在一些实施方式中，去除工艺165可以包括干蚀刻(例如深蚀刻工艺)、湿蚀刻、多步骤化学机械平整(CMP)工艺或它们的各种组合。注意到，在实施以金属栅电极160a替代多晶硅栅电极120的工艺中，没有一个工艺要求掩蔽步骤。
在图1F中，介质盖层170形成在金属栅电极160a和源区130上方。盖层170可以是氧化物层、氮化物层、氮氧化物层、其他介电层或它们的各种组合。在一些实施方式中，盖层170可以是硼磷硅酸盐玻璃(BPSG)层。利用常规工艺技术形成延伸入体区125中的接触开口。然后实施常规的重体植入(heavy bodyimplant)以沿着接触开口的底部在体区125中形成P+重体区175。形成顶侧源互联(层)180以填充接触开口。源互联层180沿着接触开口的底部形成与重体区175的电接触，并沿着接触开口的侧壁形成与源区130的电接触。盖层170使金属栅电极160a与顶侧源互联层180绝缘。
源互联层180可以包含例如钨、铜、铝、钛、钽、铂、钴、硅化物或其他导电材料。互联层180可以通过例如CVD工艺、PVD工艺、电化学镀工艺和/或非电镀工艺而形成。背侧漏极互联层(未示出)可以形成以沿衬底100的背侧形成电接触。漏极互联层可以包含与源互联层180类似的材料，并且可以利用与用于形成源互联层180相同的技术形成。
因此，如上所述通过用金属栅极代替多晶硅栅极，栅电极的电阻被显著降低。根据本发明的实施方式，金属晶体管栅极160a可以提供期望的电阻，因为它的电阻低于多晶硅的电阻。而且，在其中高-k介电层用作栅极介电层115的实施方式中，由于它的高介电常数，所以高-k介电层可以形成为物理上比传统的栅极氧化物更薄，但是具有与传统栅极氧化物层相似的有效氧化物厚度(EOT)。
由于传统的栅极多晶硅通常在体植入和推阱(drive-in)之后形成，所以替代栅极多晶硅的金属栅极有利地不经受与形成体区相关的高温热工艺。另外，也可以理想地避免关注金属栅电极的金属离子可能脱气并污染用于实施热处理的炉子。
图2是根据本发明另一实施方式的示例性沟槽栅极MOSFET的简化剖视图。该实施方式与图1F中示出的实施方式基本相似，只是在栅电极183之下没有形成屏蔽电极。相反，在一些实施方式中比栅极介电层厚(即，通常称为厚底部介电层TBO)的介电层沿沟槽底部在栅电极183下方延伸。
图3是对应于图2中所示的示例性剖视图，并且提供用来显示沟槽和各种其他区域的轮廓的更准确表示。
本文中描述的根据本发明的技术不局限于任何特定类型的晶体管，并且可以在各种各样的器件中实施。例如，在图1A-1F中描述的工艺步骤可以用来形成：p-沟道屏蔽的栅沟槽栅极MOSFET(即，结构上类似于图1F的晶体管，只是所有硅区的导电类型反转)；n-沟道屏蔽的栅极沟槽IGBT(即，结构上类似于图1F的晶体管，只是使用p-型衬底代替n-型衬底)；p-沟道屏蔽的栅极IGBT(即，结构上类似于图1F的晶体管，但其中除了衬底保持为n-型之外，硅区的导电性相反)；图2中的沟槽栅极MOSFET的p-沟道变型；图2中的沟槽栅极MOSFET的p-沟道和n-沟道IGBT变型；沟槽栅极同步FET(即，集成沟槽栅极或屏蔽栅极MOSFET和肖特基(Schottky)整流器)；侧向导电MOSFET的沟槽栅极和遮蔽栅极变型(即，其中漏极接触制成没有顶侧的晶体管)以及所有上述器件的超结(suprejunction)变型(即，具有多列交替导电类型硅的器件)。
因此，尽管以上是本发明具体实施方式的完整描述，但是可以采用各种修改、变型和替换。因此本发明的范围不局限于本文中描述的这些实施方式，而是由所附权利要求限定。

Claims (14)

1.一种场效应晶体管(FET)，包括：
在第二导电类型的半导体区上方的第一导电类型的体区，所述体区与所述半导体区形成p-n结；
延伸穿过所述体区并在所述半导体区中终止的沟槽；
在邻近所述沟槽的所述体区上方的第二导电类型的源区，所述源区与所述体区形成p-n结；
衬于每个沟槽的侧壁的栅极介电层；
衬于每个沟槽中的所述栅极介电层的金属衬里；以及
设置在每个沟槽中的包含金属材料的栅电极。
2.根据权利要求1所述的FET，进一步包括：
延伸到在相邻沟槽之间的所述体区中的接触开口；
沿着每个接触开口的底部在每个体区中延伸的第一导电类型的重体区；以及
填充每个接触开口并且沿着所述接触开口的侧壁直接接触源区的互联层。
3.根据权利要求2所述的FET，其中，所述源区的顶表面被介质盖材料完全覆盖，使得所述互联层仅沿着所述接触开口的侧壁形成与所述源区的直接接触。
4.根据权利要求1所述的FET，其中，所述栅极介电层包含高-k电介质。
5.根据权利要求1所述的FET，其中，每个沟槽进一步包括设置在所述栅电极下方的屏蔽电极，所述栅电极和屏蔽电极通过电极间介电层彼此绝缘。
6.根据权利要求1所述的FET，其中，每个沟槽进一步包括在所述栅电极下方沿着所述沟槽的底部延伸的厚底部电介质。
7.一种形成场效应晶体管(FET)的方法，包括：
在第二导电类型的半导体区中形成第一导电类型的体区，所述体区与所述半导体区形成p-n结；
形成延伸到所述半导体区中的沟槽；
在邻近所述沟槽的所述体区上方形成第二导电类型的源区，所述源区与所述体区形成p-n结；
形成衬于每个沟槽的侧壁的栅极介电层；
形成衬于每个沟槽中的所述栅极介电层的金属衬里；以及
在每个沟槽中形成金属栅电极，所述金属栅电极包含金属材料。
8.根据权利要求7所述的方法，进一步包括：
形成延伸到在相邻沟槽之间的所述体区中的接触开口；
形成沿着每个接触开口的底部在每个体区中延伸的第一导电类型的重体区；
形成填充每个接触开口并且沿着所述接触开口的侧壁直接接触所述源区的互联层。
9.根据权利要求8所述的方法，进一步包括：
形成完全覆盖所述源区的顶表面的介质盖材料，使得所述互联层仅沿着所述接触开口的侧壁形成与所述源区的直接接触。
10.根据权利要求7所述的方法，其中，所述栅极介电层包含高-k电介质。
11.根据权利要求7所述的方法，进一步包括：
在形成所述栅电极之前：
形成衬于每个沟槽的下侧壁和底部的屏蔽介电层；
在每个沟槽的下部分中形成屏蔽电极；以及
在所述屏蔽电极上方的每个沟槽中形成电极间介电层。
12.根据权利要求7所述的方法，进一步包括：
在形成所述金属栅电极之前：
在每个沟槽中形成多晶硅栅极材料；以及
从每个沟槽中去除所述多晶硅栅极材料。
13.根据权利要求7所述的方法，其中，所述金属材料包括钨。
14.根据权利要求7所述的方法，其中，所述金属栅电极是在形成所述体区之后形成的。
CN2008801206235A 2007-12-14 2008-12-15 形成具有低栅电阻的沟槽栅晶体管的结构及方法 Pending CN101897010A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US1398507P 2007-12-14 2007-12-14
US61/013,985 2007-12-14
US12/333,707 2008-12-12
US12/333,707 US20100013009A1 (en) 2007-12-14 2008-12-12 Structure and Method for Forming Trench Gate Transistors with Low Gate Resistance
PCT/US2008/086868 WO2009079473A1 (en) 2007-12-14 2008-12-15 Structure and method for forming trench gate transistors with low gate resistance

Publications (1)

Publication Number Publication Date
CN101897010A true CN101897010A (zh) 2010-11-24

Family

ID=40795896

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008801206235A Pending CN101897010A (zh) 2007-12-14 2008-12-15 形成具有低栅电阻的沟槽栅晶体管的结构及方法

Country Status (4)

Country Link
US (1) US20100013009A1 (zh)
CN (1) CN101897010A (zh)
TW (1) TW200935604A (zh)
WO (1) WO2009079473A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104078507A (zh) * 2013-03-27 2014-10-01 力士科技股份有限公司 一种沟槽金属氧化物半导体场效应管
CN105336735A (zh) * 2014-08-05 2016-02-17 英飞凌科技奥地利有限公司 具有场效应结构的半导体器件及制造其的方法
CN112768513A (zh) * 2016-07-18 2021-05-07 英飞凌科技奥地利有限公司 具有场电极的功率半导体器件
CN114628496A (zh) * 2022-05-13 2022-06-14 江苏游隼微电子有限公司 一种多沟槽功率mosfet结构及其制作方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932536B2 (en) * 2007-03-09 2011-04-26 Diodes Incorporated Power rectifiers and method of making same
US8193579B2 (en) * 2008-07-29 2012-06-05 Rohm Co., Ltd. Trench type semiconductor device and fabrication method for the same
KR101025743B1 (ko) * 2008-10-13 2011-04-04 한국전자통신연구원 중거리 무선 전력 전송 기술을 이용한 인공 망막 구동 장치
JP2011066303A (ja) * 2009-09-18 2011-03-31 Elpida Memory Inc 半導体装置の製造方法
US8193081B2 (en) * 2009-10-20 2012-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for metal gate formation with wider metal gate fill margin
US20110198689A1 (en) * 2010-02-17 2011-08-18 Suku Kim Semiconductor devices containing trench mosfets with superjunctions
US9472405B2 (en) * 2011-02-02 2016-10-18 Rohm Co., Ltd. Semiconductor power device and method for producing same
US9318336B2 (en) 2011-10-27 2016-04-19 Globalfoundries U.S. 2 Llc Non-volatile memory structure employing high-k gate dielectric and metal gate
US8853076B2 (en) * 2012-09-10 2014-10-07 International Business Machines Corporation Self-aligned contacts
US9741797B2 (en) * 2013-02-05 2017-08-22 Mitsubishi Electric Corporation Insulated gate silicon carbide semiconductor device and method for manufacturing same
US10002941B2 (en) 2015-05-20 2018-06-19 Fairchild Semiconductor Corporation Hybrid gate dielectrics for semiconductor power devices
US11031478B2 (en) * 2018-01-23 2021-06-08 Infineon Technologies Austria Ag Semiconductor device having body contacts with dielectric spacers and corresponding methods of manufacture
EP3863066A1 (en) * 2020-02-06 2021-08-11 Infineon Technologies Austria AG Transistor device and method of fabricating a gate of a transistor device
TWI773029B (zh) * 2020-12-17 2022-08-01 國立清華大學 具有溝槽式接面蕭基位障二極體的半導體結構
US20220293786A1 (en) * 2021-03-10 2022-09-15 Nami MOS CO., LTD. An improved shielded gate trench mosfet with low on-resistance
JP2023147422A (ja) * 2022-03-30 2023-10-13 株式会社 日立パワーデバイス 半導体装置および電力変換装置

Family Cites Families (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441247A (en) * 1981-06-29 1984-04-10 Intel Corporation Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate
US4983535A (en) * 1981-10-15 1991-01-08 Siliconix Incorporated Vertical DMOS transistor fabrication process
US4503601A (en) * 1983-04-18 1985-03-12 Ncr Corporation Oxide trench structure for polysilicon gates and interconnects
US4568958A (en) * 1984-01-03 1986-02-04 General Electric Company Inversion-mode insulated-gate gallium arsenide field-effect transistors
US5208657A (en) * 1984-08-31 1993-05-04 Texas Instruments Incorporated DRAM Cell with trench capacitor and vertical channel in substrate
US4859621A (en) * 1988-02-01 1989-08-22 General Instrument Corp. Method for setting the threshold voltage of a vertical power MOSFET
US4881105A (en) * 1988-06-13 1989-11-14 International Business Machines Corporation Integrated trench-transistor structure and fabrication process
JPH02206175A (ja) * 1989-02-06 1990-08-15 Fuji Electric Co Ltd Ｍｏｓ型半導体装置
US5281548A (en) * 1992-07-28 1994-01-25 Micron Technology, Inc. Plug-based floating gate memory
US5326711A (en) * 1993-01-04 1994-07-05 Texas Instruments Incorporated High performance high voltage vertical transistor and method of fabrication
US5341011A (en) * 1993-03-15 1994-08-23 Siliconix Incorporated Short channel trenched DMOS transistor
JP3311070B2 (ja) * 1993-03-15 2002-08-05 株式会社東芝 半導体装置
JP3481287B2 (ja) * 1994-02-24 2003-12-22 三菱電機株式会社 半導体装置の製造方法
US5424231A (en) * 1994-08-09 1995-06-13 United Microelectronics Corp. Method for manufacturing a VDMOS transistor
US5455190A (en) * 1994-12-07 1995-10-03 United Microelectronics Corporation Method of making a vertical channel device using buried source techniques
US5648670A (en) * 1995-06-07 1997-07-15 Sgs-Thomson Microelectronics, Inc. Trench MOS-gated device with a minimum number of masks
US5689128A (en) * 1995-08-21 1997-11-18 Siliconix Incorporated High density trenched DMOS transistor
FR2738394B1 (fr) * 1995-09-06 1998-06-26 Nippon Denso Co Dispositif a semi-conducteur en carbure de silicium, et son procede de fabrication
US5879971A (en) * 1995-09-28 1999-03-09 Motorola Inc. Trench random access memory cell and method of formation
US5770878A (en) * 1996-04-10 1998-06-23 Harris Corporation Trench MOS gate device
US5808340A (en) * 1996-09-18 1998-09-15 Advanced Micro Devices, Inc. Short channel self aligned VMOS field effect transistor
JPH10256550A (ja) * 1997-01-09 1998-09-25 Toshiba Corp 半導体装置
US6057558A (en) * 1997-03-05 2000-05-02 Denson Corporation Silicon carbide semiconductor device and manufacturing method thereof
DE19720193C2 (de) * 1997-05-14 2002-10-17 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mindestens zwei vertikalen MOS-Transistoren und Verfahren zu deren Herstellung
US5981995A (en) * 1997-06-13 1999-11-09 Advanced Micro Devices, Inc. Static random access memory cell having buried sidewall transistors, buried bit lines, and buried vdd and vss nodes
US6110799A (en) * 1997-06-30 2000-08-29 Intersil Corporation Trench contact process
KR100304716B1 (ko) * 1997-09-10 2001-11-02 김덕중 모스컨트롤다이오드및그제조방법
US6051468A (en) * 1997-09-15 2000-04-18 Magepower Semiconductor Corp. Method of forming a semiconductor structure with uniform threshold voltage and punch-through tolerance
US6097061A (en) * 1998-03-30 2000-08-01 Advanced Micro Devices, Inc. Trenched gate metal oxide semiconductor device and method
US6048772A (en) * 1998-05-04 2000-04-11 Xemod, Inc. Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
KR100304717B1 (ko) * 1998-08-18 2001-11-15 김덕중 트렌치형게이트를갖는반도체장치및그제조방법
US6351009B1 (en) * 1999-03-01 2002-02-26 Fairchild Semiconductor Corporation MOS-gated device having a buried gate and process for forming same
US6157081A (en) * 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication
US6291298B1 (en) * 1999-05-25 2001-09-18 Advanced Analogic Technologies, Inc. Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses
US6274905B1 (en) * 1999-06-30 2001-08-14 Fairchild Semiconductor Corporation Trench structure substantially filled with high-conductivity material
US6461918B1 (en) * 1999-12-20 2002-10-08 Fairchild Semiconductor Corporation Power MOS device with improved gate charge performance
US6312993B1 (en) * 2000-02-29 2001-11-06 General Semiconductor, Inc. High speed trench DMOS
JP2002043571A (ja) * 2000-07-28 2002-02-08 Nec Kansai Ltd 半導体装置
DE10063443B4 (de) * 2000-12-20 2005-03-03 Infineon Technologies Ag Verfahren zur Herstellung einer Elektrode eines mittels Feldeffekt steuerbaren Halbleiterbauelements und mittels Feldeffekt steuerbares Halbleiterbauelement
US6870220B2 (en) * 2002-08-23 2005-03-22 Fairchild Semiconductor Corporation Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6916745B2 (en) * 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
JP4236848B2 (ja) * 2001-03-28 2009-03-11 セイコーインスツル株式会社 半導体集積回路装置の製造方法
JP4073176B2 (ja) * 2001-04-02 2008-04-09 新電元工業株式会社 半導体装置およびその製造方法
JP2003023150A (ja) * 2001-07-10 2003-01-24 Sony Corp トレンチゲート型半導体装置及びその作製方法
US7045859B2 (en) * 2001-09-05 2006-05-16 International Rectifier Corporation Trench fet with self aligned source and contact
US6822288B2 (en) * 2001-11-20 2004-11-23 General Semiconductor, Inc. Trench MOSFET device with polycrystalline silicon source contact structure
GB0129450D0 (en) * 2001-12-08 2002-01-30 Koninkl Philips Electronics Nv Trenched semiconductor devices and their manufacture
US6452229B1 (en) * 2002-02-21 2002-09-17 Advanced Micro Devices, Inc. Ultra-thin fully depleted SOI device with T-shaped gate and method of fabrication
US7091573B2 (en) * 2002-03-19 2006-08-15 Infineon Technologies Ag Power transistor
DE10212149B4 (de) * 2002-03-19 2007-10-04 Infineon Technologies Ag Transistoranordnung mit Schirmelektrode außerhalb eines aktiven Zellenfeldes und reduzierter Gate-Drain-Kapazität
TWI248136B (en) * 2002-03-19 2006-01-21 Infineon Technologies Ag Method for fabricating a transistor arrangement having trench transistor cells having a field electrode
JP3637330B2 (ja) * 2002-05-16 2005-04-13 株式会社東芝 半導体装置
AU2003228073A1 (en) * 2002-05-31 2003-12-19 Koninklijke Philips Electronics N.V. Trench-gate semiconductor device,corresponding module and apparatus ,and method of operating the device
JP2004228342A (ja) * 2003-01-23 2004-08-12 Denso Corp 半導体装置およびその製造方法
US7652326B2 (en) * 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP4892172B2 (ja) * 2003-08-04 2012-03-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
DE10339455B3 (de) * 2003-08-27 2005-05-04 Infineon Technologies Ag Vertikales Halbleiterbauelement mit einer eine Feldelektrode aufweisenden Driftzone und Verfahren zur Herstellung einer solchen Driftzone
EP1671374B1 (en) * 2003-10-08 2018-05-09 Toyota Jidosha Kabushiki Kaisha Insulated gate type semiconductor device and manufacturing method thereof
DE10350684B4 (de) * 2003-10-30 2008-08-28 Infineon Technologies Ag Verfahren zur Herstellung einer Leistungstransistoranordnung und mit diesem Verfahren hergestellte Leistungstransistoranordnung
JP4917246B2 (ja) * 2003-11-17 2012-04-18 ローム株式会社 半導体装置およびその製造方法
US7405452B2 (en) * 2004-02-02 2008-07-29 Hamza Yilmaz Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics
KR100526891B1 (ko) * 2004-02-25 2005-11-09 삼성전자주식회사 반도체 소자에서의 버티컬 트랜지스터 구조 및 그에 따른형성방법
US7470967B2 (en) * 2004-03-12 2008-12-30 Semisouth Laboratories, Inc. Self-aligned silicon carbide semiconductor devices and methods of making the same
US7400014B2 (en) * 2004-04-20 2008-07-15 International Rectifier Corporation ACCUFET with schottky source contact
US7153784B2 (en) * 2004-04-20 2006-12-26 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7268395B2 (en) * 2004-06-04 2007-09-11 International Rectifier Corporation Deep trench super switch device
US20050269644A1 (en) * 2004-06-08 2005-12-08 Brask Justin K Forming integrated circuits with replacement metal gate electrodes
US7465986B2 (en) * 2004-08-27 2008-12-16 International Rectifier Corporation Power semiconductor device including insulated source electrodes inside trenches
DE102004046697B4 (de) * 2004-09-24 2020-06-10 Infineon Technologies Ag Hochspannungsfestes Halbleiterbauelement mit vertikal leitenden Halbleiterkörperbereichen und einer Grabenstruktur sowie Verfahren zur Herstellung desselben
US7371641B2 (en) * 2004-10-29 2008-05-13 International Rectifier Corporation Method of making a trench MOSFET with deposited oxide
US7109552B2 (en) * 2004-11-01 2006-09-19 Silicon-Based Technology, Corp. Self-aligned trench DMOS transistor structure and its manufacturing methods
US20060091483A1 (en) * 2004-11-02 2006-05-04 Doczy Mark L Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode
JP4552603B2 (ja) * 2004-11-08 2010-09-29 エルピーダメモリ株式会社 半導体装置の製造方法
US7091118B1 (en) * 2004-11-16 2006-08-15 Advanced Micro Devices, Inc. Replacement metal gate transistor with metal-rich silicon layer and method for making the same
KR100629356B1 (ko) * 2004-12-23 2006-09-29 삼성전자주식회사 필라 패턴을 갖는 플래시메모리소자 및 그 제조방법
CN102867825B (zh) * 2005-04-06 2016-04-06 飞兆半导体公司 沟栅场效应晶体管结构及其形成方法
KR101254835B1 (ko) * 2005-05-26 2013-04-15 페어차일드 세미컨덕터 코포레이션 트랜치-게이트 전계 효과 트랜지스터 및 그 형성 방법
TWI400757B (zh) * 2005-06-29 2013-07-01 Fairchild Semiconductor 形成遮蔽閘極場效應電晶體之方法
US7514743B2 (en) * 2005-08-23 2009-04-07 Robert Kuo-Chang Yang DMOS transistor with floating poly-filled trench for improved performance through 3-D field shaping
DE102005041358B4 (de) * 2005-08-31 2012-01-19 Infineon Technologies Austria Ag Feldplatten-Trenchtransistor sowie Verfahren zu dessen Herstellung
US7768064B2 (en) * 2006-01-05 2010-08-03 Fairchild Semiconductor Corporation Structure and method for improving shielded gate field effect transistors
US7449354B2 (en) * 2006-01-05 2008-11-11 Fairchild Semiconductor Corporation Trench-gated FET for power device with active gate trenches and gate runner trench utilizing one-mask etch
US7807536B2 (en) * 2006-02-10 2010-10-05 Fairchild Semiconductor Corporation Low resistance gate for power MOSFET applications and method of manufacture
US7633119B2 (en) * 2006-02-17 2009-12-15 Alpha & Omega Semiconductor, Ltd Shielded gate trench (SGT) MOSFET devices and manufacturing processes
US7521773B2 (en) * 2006-03-31 2009-04-21 Fairchild Semiconductor Corporation Power device with improved edge termination
US7319256B1 (en) * 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US7592230B2 (en) * 2006-08-25 2009-09-22 Freescale Semiconductor, Inc. Trench power device and method
JP5232377B2 (ja) * 2006-10-31 2013-07-10 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20080246082A1 (en) * 2007-04-04 2008-10-09 Force-Mos Technology Corporation Trenched mosfets with embedded schottky in the same cell
US8497549B2 (en) * 2007-08-21 2013-07-30 Fairchild Semiconductor Corporation Method and structure for shielded gate trench FET
JP5587535B2 (ja) * 2007-11-14 2014-09-10 ローム株式会社 半導体装置
US7772668B2 (en) * 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104078507A (zh) * 2013-03-27 2014-10-01 力士科技股份有限公司 一种沟槽金属氧化物半导体场效应管
CN105336735A (zh) * 2014-08-05 2016-02-17 英飞凌科技奥地利有限公司 具有场效应结构的半导体器件及制造其的方法
US10693000B2 (en) 2014-08-05 2020-06-23 Infineon Technologies Austria Ag Semiconductor device having field-effect structures with different gate materials
CN105336735B (zh) * 2014-08-05 2020-07-07 英飞凌科技奥地利有限公司 具有场效应结构的半导体器件及制造其的方法
CN112768513A (zh) * 2016-07-18 2021-05-07 英飞凌科技奥地利有限公司 具有场电极的功率半导体器件
CN112768513B (zh) * 2016-07-18 2024-07-30 英飞凌科技奥地利有限公司 具有场电极的功率半导体器件
CN114628496A (zh) * 2022-05-13 2022-06-14 江苏游隼微电子有限公司 一种多沟槽功率mosfet结构及其制作方法

Also Published As

Publication number Publication date
WO2009079473A1 (en) 2009-06-25
US20100013009A1 (en) 2010-01-21
TW200935604A (en) 2009-08-16

Similar Documents

Publication Publication Date Title
CN101897010A (zh) 形成具有低栅电阻的沟槽栅晶体管的结构及方法
US7994573B2 (en) Structure and method for forming power devices with carbon-containing region
CN101971346B (zh) 用于形成具有高纵横比接触开口的功率器件的结构和方法
US7825465B2 (en) Structure and method for forming field effect transistor with low resistance channel region
TWI459561B (zh) 用以形成具有其中含有低ｋ介電體之極間電極介電體之屏蔽閘極溝渠場效電晶體（ｆｅｔ）的結構及方法
US20100264488A1 (en) Low Qgd trench MOSFET integrated with schottky rectifier
US7791136B1 (en) Trench MOSFET having trench contacts integrated with trench Schottky rectifiers having planar contacts
CN102097378B (zh) 一种沟槽金属氧化物半导体场效应管的制造方法
US11380787B2 (en) Shielded gate trench MOSFET integrated with super barrier rectifier having short channel
CN101615632A (zh) 用于形成具有包括氮化层的极间电介质的屏蔽栅沟槽fet的结构和方法
TWI567830B (zh) 溝槽式功率電晶體結構及其製造方法
CN103311275B (zh) 半导体器件和制造半导体器件的方法
US10128368B2 (en) Double gate trench power transistor and manufacturing method thereof
US20220045184A1 (en) Shielded gate trench mosfet with esd diode manufactured using two poly-silicon layers process
TWI678805B (zh) 溝槽式功率半導體元件及其製造方法
KR100656239B1 (ko) 선택적 에피택셜 성장에 의해 형성된 트렌치 벽을 갖는 트렌치-게이트 파워 디바이스
US20120267708A1 (en) Termination structure for power devices
TWI732182B (zh) 半導體裝置及其形成方法
CN113964176A (zh) 半导体结构及其形成方法
US20240120418A1 (en) Ldmos semiconductor device and method of manufacturing the same
CN111697050B (zh) 半导体装置及其形成方法
US20240178270A1 (en) Semiconductor device and methods for forming the same
CN117894847A (zh) 半导体器件及其形成方法
TW201507154A (zh) 溝渠式閘極金氧半場效電晶體

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20101124