CN101796636B - 芯片连接方法 - Google Patents

芯片连接方法 Download PDF

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Publication number
CN101796636B
CN101796636B CN200680029328XA CN200680029328A CN101796636B CN 101796636 B CN101796636 B CN 101796636B CN 200680029328X A CN200680029328X A CN 200680029328XA CN 200680029328 A CN200680029328 A CN 200680029328A CN 101796636 B CN101796636 B CN 101796636B
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CN
China
Prior art keywords
chip
wafer
contact
contacts
ductile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN200680029328XA
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English (en)
Chinese (zh)
Other versions
CN101796636A (zh
Inventor
约翰·特雷扎
约翰·卡拉汉
格雷戈里·杜多夫
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Cufer Asset Ltd LLC
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Cufer Asset Ltd LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/329,875 external-priority patent/US7969015B2/en
Application filed by Cufer Asset Ltd LLC filed Critical Cufer Asset Ltd LLC
Priority to CN201310019765.5A priority Critical patent/CN103178031B/zh
Priority claimed from PCT/US2006/023246 external-priority patent/WO2006138423A2/en
Publication of CN101796636A publication Critical patent/CN101796636A/zh
Application granted granted Critical
Publication of CN101796636B publication Critical patent/CN101796636B/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
CN200680029328XA 2005-06-14 2006-06-14 芯片连接方法 Expired - Lifetime CN101796636B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310019765.5A CN103178031B (zh) 2005-06-14 2006-06-14 芯片连接方法

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US69075905P 2005-06-14 2005-06-14
US60/690,759 2005-06-14
US11/329,874 2006-01-10
US11/329,875 US7969015B2 (en) 2005-06-14 2006-01-10 Inverse chip connector
US11/329,575 2006-01-10
US11/329,875 2006-01-10
US11/329,575 US7884483B2 (en) 2005-06-14 2006-01-10 Chip connector
US11/329,874 US20060278966A1 (en) 2005-06-14 2006-01-10 Contact-based encapsulation
PCT/US2006/023246 WO2006138423A2 (en) 2005-06-14 2006-06-14 Chip connector

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201310019765.5A Division CN103178031B (zh) 2005-06-14 2006-06-14 芯片连接方法

Publications (2)

Publication Number Publication Date
CN101796636A CN101796636A (zh) 2010-08-04
CN101796636B true CN101796636B (zh) 2013-02-27

Family

ID=40239700

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200680029328XA Expired - Lifetime CN101796636B (zh) 2005-06-14 2006-06-14 芯片连接方法

Country Status (3)

Country Link
JP (4) JP2008547205A (cg-RX-API-DMAC7.html)
KR (1) KR101191523B1 (cg-RX-API-DMAC7.html)
CN (1) CN101796636B (cg-RX-API-DMAC7.html)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8309396B2 (en) * 2009-01-26 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for 3D integrated circuit stacking
CN103378031B (zh) * 2012-04-20 2016-02-03 南亚科技股份有限公司 半导体芯片与封装结构以及其形成方法
KR102190382B1 (ko) 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
KR102244435B1 (ko) 2014-09-03 2021-04-26 삼성디스플레이 주식회사 회로판 및 이를 포함하는 전자 장치
EP3235354B1 (en) * 2014-12-16 2024-01-24 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Contacting embedded electronic component via wiring structure in a component carrier's surface portion with homogeneous ablation properties
US20180340056A1 (en) * 2015-08-28 2018-11-29 Hitachi Chemical Company, Ltd. Buffer sheet composition and buffer sheet
JP6424297B2 (ja) * 2016-03-25 2018-11-14 住友精密工業株式会社 充填方法
CN106252318B (zh) * 2016-09-29 2019-01-04 华进半导体封装先导技术研发中心有限公司 植球工艺和结构
JP7148300B2 (ja) * 2018-07-12 2022-10-05 上村工業株式会社 導電性バンプ、及び無電解Ptめっき浴
CN113675722B (zh) * 2021-07-14 2024-10-29 威科赛乐微电子股份有限公司 一种Cap layer层蚀刻优化方法
AU2021480187A1 (en) * 2021-12-22 2024-07-11 Viasat, Inc. Antenna apparatus employing radiation shield for integrated circuits

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608264A (en) * 1995-06-05 1997-03-04 Harris Corporation Surface mountable integrated circuit with conductive vias
CN2399842Y (zh) * 1999-10-29 2000-10-04 富士康(昆山)电脑接插件有限公司 电连接器
CN1608319A (zh) * 2000-11-28 2005-04-20 东京毅力科创株式会社 用于双重镶嵌式金属线的最佳衬层

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07112041B2 (ja) * 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
JP4026882B2 (ja) * 1997-02-24 2007-12-26 三洋電機株式会社 半導体装置
JPH10270498A (ja) * 1997-03-27 1998-10-09 Toshiba Corp 電子装置の製造方法
JP3731378B2 (ja) * 1999-03-31 2006-01-05 セイコーエプソン株式会社 半導体素子の製造方法、および半導体素子、ならびに実装モジュール
JP2001085600A (ja) * 1999-09-16 2001-03-30 Seiko Epson Corp 半導体チップ、マルチチップパッケージ、半導体装置、並びに電子機器
JP4547523B2 (ja) * 2000-09-25 2010-09-22 太陽誘電株式会社 チップ部品組立体とその製造方法
US7242099B2 (en) 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
US6732908B2 (en) * 2002-01-18 2004-05-11 International Business Machines Corporation High density raised stud microjoining system and methods of fabricating the same
JP2004047537A (ja) * 2002-07-09 2004-02-12 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2004119773A (ja) * 2002-09-27 2004-04-15 Toshiba Corp 半導体装置及びその製造方法
JP4074862B2 (ja) * 2004-03-24 2008-04-16 ローム株式会社 半導体装置の製造方法、半導体装置、および半導体チップ
JP4551255B2 (ja) * 2005-03-31 2010-09-22 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608264A (en) * 1995-06-05 1997-03-04 Harris Corporation Surface mountable integrated circuit with conductive vias
CN2399842Y (zh) * 1999-10-29 2000-10-04 富士康(昆山)电脑接插件有限公司 电连接器
CN1608319A (zh) * 2000-11-28 2005-04-20 东京毅力科创株式会社 用于双重镶嵌式金属线的最佳衬层

Also Published As

Publication number Publication date
JP5696016B2 (ja) 2015-04-08
JP2012028802A (ja) 2012-02-09
JP5542763B2 (ja) 2014-07-09
KR101191523B1 (ko) 2012-10-15
JP2008547205A (ja) 2008-12-25
JP5542762B2 (ja) 2014-07-09
JP2012039129A (ja) 2012-02-23
KR20110132485A (ko) 2011-12-07
JP2012028801A (ja) 2012-02-09
CN101796636A (zh) 2010-08-04

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Granted publication date: 20130227

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