CN101779529A - 电子电路装置以及建立电子电路装置的方法 - Google Patents

电子电路装置以及建立电子电路装置的方法 Download PDF

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CN101779529A
CN101779529A CN200880103164A CN200880103164A CN101779529A CN 101779529 A CN101779529 A CN 101779529A CN 200880103164 A CN200880103164 A CN 200880103164A CN 200880103164 A CN200880103164 A CN 200880103164A CN 101779529 A CN101779529 A CN 101779529A
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M·弗朗茨
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Robert Bosch GmbH
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Abstract

本发明涉及一个包含至少一个第一电路装置(1)和至少一个第二电路装置(3)的电子电路的装置(4),其中所述两个电路装置(1,3)通过至少一个传递装置(2)的中间连接而互相电连接。依据本发明,所述传递装置(2)与所述第一电路装置(1)通过导电胶粘连接(32)电连接,且所述传递装置(2)与所述第二电路装置(3)通过导电胶粘连接(32)和/或通过焊接连接(29)电连接。本发明进一步涉及一个建立相应的电子电路装置(1)的方法。

Description

电子电路装置以及建立电子电路装置的方法
技术领域
本发明涉及一个包含至少一个第一电路装置和至少一个第二电路装置的电子电路装置,其中所述电路装置通过至少一个传递装置的中间连接而互相电连接。
此外本发明还涉及一个建立电子电路装置的方法,所述电子电路装置包括至少一个第一电路装置以及至少一个第二电路装置,为了所述电路装置进行电连接,在所述电路装置中间至少安置一个传递装置,且所述电路装置与所述传递装置电连接。
背景技术
这样的包含两个电路装置的电路装置例如不同功能的电子设备是公知的。所述电子设备通常由一个作为控制电子的第一电路装置和一个作为功率电子的第二电路装置组成。所述控制电子和所述功率电子在多种情况下由不同的电路技术实现。多数控制电子和功率电子的机械和电连接表现为平滑的组装。不同技术的电路装置在使用时,采用的不同组装方法进行电和/或机械连接,常用的有插头、电线、引线框架、粘结,弹性导电板和/或其他电连接介质。所述常规组装方法需要附加的空间来进行布线,以完成所述第一和第二电路装置的电连接。
发明内容
为了简单的组装以及为了在通过至少一个传递装置节省空间地进行电路装置电连接/接触连接,进行如下设计:所述传递装置与所述第一电路装置通过导电胶粘连接进行电连接,且所述传递装置与所述第二电路装置通过导电胶粘连接和/或焊接连接进行电连接。为彼此之间的电连接,所述两个电路装置包含接触区,其通过所述传递装置彼此电连接。为此所述传递装置有一个相应的电导体结构,其将所述第一电路装置的接触区与相应分配的第二电路装置的接触区电连接。为此,所述传递装置也包含接触区。所述第一电路装置的接触区与所分配的传递装置的接触区通过导电胶粘连接电连接。所述第二电路装置的接触区与所分配的传递装置的接触区通过导电胶粘连接和/或焊接连接电连接。分配给所述第一电路装置的传递装置的接触区与分配给所述第二电路装置的传递装置的接触区通过所述传递装置的一个电导体结构相互连接,使得所述第一电路装置的接触区与所分配的所述第二电路装置的接触区通过所述组装电连接。所述第一电路装置与所述传递装置的连接材料以及所述传递装置与第二电路装置的连接材料可以是不同的或相同的。在建立各连接之前,准备好用于构成所述连接的各材料,优选膏状。
所述传递装置优选地如此构成,使其与所述电路装置也相互机械连接,由此形成一个紧密的和稳定的电子电路装置。此外,在本发明的一个有利的设计方案中,为了所述电路装置的电连接和/或机械连接,安排至少一个另外的传递装置和/或至少一个传递元件。
在本发明的一个有利的设计方案中有如下设计:所述传递装置为连接所述第一电路装置,在其上面包含导电胶粘连接;为连接所述第二电路装置,在其下面包含导电胶粘连接和/或焊接连接。所述两面是所述传递装置两个彼此相对的面,与传递装置实际上的定位不相关。
本发明具有的优点在于,所述传递装置是一个传递电路板或至少包含一个传递电路板。所述传递装置由n层构成,其中n=1,2,3......。
此外本发明具有的优点还在于,所述第一电路装置是一个第一电路板,或至少包含一个第一电路板。所述第一电路装置由m层构成,其中m=1,2,3......
在本发明的一个有利的设计方案中有如下设计:所述第二电路装置是一个第二电路板或包含至少一个第二电路板。所述第二电路装置由o层构成,其中o=1,2,3......
在本发明的一个扩展中做如下设计:所述第一电路装置采用第一电路载体技术实现。所述第一电路装置优选地是传统技术下通过印刷电路板或LTTC技术(低温共烧陶瓷)采用LTCC基底实现的。
此外本发明具有的优点还在于,所述第二电路装置采用第二电路载体技术实现。所述第二电路装置优选通过DCB技术(DCB:直接敷铜)采用DCB基底实现。
特别地对于如下设计:所述第一电路装置是一个低电流电路装置和/或所述第二电路装置是一个高电流电路装置。在本申请中将低电流电路装置理解为如下的电路装置:其功率消耗低,不超过导电连接媒介,即导电胶的电流承载能力。在本申请中将高电流电路装置理解为如下的电路装置:在至少一个工作情况下,其功率消耗高,不超过导电连接媒介(导电胶和/或焊锡)的导电能力。
优选地进行如下设计:所述导电胶粘连接采用导电胶,尤其是印刷导电胶实现。为了所述第一电路装置与所述传递装置的电连接,优选在所述第一电路装置和/或所述传递装置的接触区上,以及为了所述第二电路装置与所述传递装置的电连接,优选在所述第二电路装置和/或所述传递装置的接触区上,印刷所述导电胶。
此外本发明具有的优点还在于如下设计:所述焊接连接采用焊锡,尤其是印刷焊锡实现。其中在所述第二电路装置和所述传递装置的组装之前,在所述传递装置和/或所述第二电路装置的接触区印刷焊锡,之后相互焊接。
本发明具有的优点还在于所述两个电路装置以及所述传递装置通过电绝缘填充物(底充胶)彼此机械连接,使所述电子电路装置形成电子电路模块。在SMD技术中已知一个此类的底充胶。
依据本发明的方法特征在于,所述传递装置与所述第一电路装置通过导电胶电连接,并且所述传递装置与所述第二电路装置通过导电粘贴连接和/或通过焊接连接进行电连接。优选地得出如下包括两个电路装置的电路装置的建立步骤如下:
-在所述传递装置的第二面上印刷焊锡
-焊接所述传递装置与所述第二电路装置,随后可进行一个第一功能测试,
-在所述传递装置的第一面上印刷导电胶,
-将由第二电路装置与传递装置组成的系统(中间模块)与所述第一电路装置粘贴,随后可以进行一个整个电路装置的功能测试,且
-引入填充物(底充胶)以提高模块的机械稳定性。
附图说明
下面将依据附图进一步阐述本发明。附图为:
图1:一个第一电路装置,一个第二电路装置和一个传递装置
图2:印刷焊锡的传递装置,
图3:由传递装置与该焊接的第二电路装置组成的中间模块,
图4:图3中所示的由传递装置与该焊接的第二电路装置组成的中间模块,其上面印有导电胶,
图5:一个由所述第一电路装置、所述传递装置以及所述第二电路装置组成的电子电路装置,
图6:图5所示的电子电路装置带有用于机械稳定的底充胶,且
图7:所述电路装置与一个冷却体的热接触。
具体实施方式
图1示出了建立一个电路装置4的电连接之前的一个第一电路装置1、一个传递装置2以及一个第二电路装置3。所述电路装置4是一个电子设备的特定部分。
所述第一电路装置1是通过一个由m层构成的第一电路板5构成,其中m=4。在所述第一电路装置1的上面6与在其下面7同样,固定有电元件8,尤其是电子元件,并与所述第一电路装置1的导电线路9(仅部分示出)接触。所述第一电路装置1的不同位置借助未示出的作为通孔构成的贯穿接触彼此电连接。所述第一电路装置1在其下面7包含多个接触区10,其在电路装置的装配时起到使所述第一电路装置1与所述传递装置2相接触的作用。所述第一电路装置作为低电流电路装置11构成。
所述传递装置2是通过一个由n层构成的电路板12构成,其中n=2,在其作为上面13构成的第一面13上以及在作为下面14构成的第二面14上分别包含接触区15。所述接触区15通过所述传递装置2的导电线路16彼此电连接。所述连接是所述上面13上的接触区15之间的连接,是所述下面14上的接触区15之间的连接,也是所述上面13和所述下面14的接触区15之间的连接。所述传递装置2上面13上的接触区15是安置在与所述第一电路装置1的下面8上所分配的接触区10相对应的装配位置。
所述第二电路装置3是通过一个由o层构成的第二电路板17构成,其中o=1。所述第二电路装置3在其上面18包含电元件19,尤其是电子元件。所述第二电路装置3的下面20在本实施例中不包含电元件19,且可以用于例如在图7中所示的一个冷却体21的热接触。所述第二电路装置3的电元件19通过导电线路23与所述第二电路装置3的上面18上的接触区22相互接触。所述第二电路装置3的接触区22安置在与所述传递装置2的下面14上的接触区15相对应的装配位置。在电路装置4组装时,所述第二电路装置3和所述传递装置2,通过所述第二电路装置3的接触区22以及位于所述传递装置2的下面14上的接触区15,彼此电接触。所述第二电路装置3是一个高电流电路装置24。
所述电元件8,19是-或者至少部分是-电子元件,尤其是SMD元件。所述第一电路装置1在装配完成的电路装置4内构成一个控制电子25,且所述第二电路装置3在装配完成的电路装置4中构成一个功率电子26。与此相应地,所述第一电路装置1的电元件8是控制电子25的元件,所述第二电路装置3的电元件19是功率电子26的元件。所述第二电路装置3的电元件19至少部分是无外壳的带有相应电接口的功率半导体。
接着在图2到图7中将描述由所述第一电路装置1、所述传递装置2以及所述第二电路装置3构成的所述电路装置4的一个装配的装配过程。通过所述装配形成一个电路装置4,其被构造为三维多位置电路装置27,如图6和图7所示。所述装配过程如下:
1.在所述传递装置2的下面14印刷焊锡28。一个相应的传递装置2如图2所示,其下面14上的接触区15印有焊锡28。
2.焊接所述传递装置2与所述第二电路装置3。图3中示出了彼此电接触的装置2、3,其通过所述传递装置2和所述第二电路装置3的接触区15,22,以及通过焊锡28构成的焊接连接29彼此电接触。在此形成了一个由装置2,3构成的中间模块30。之后,可以在所述传递装置2与第二电路装置3的该第一接触进行该模块30的一个第一功能测试。
3.在所述传递装置2的上面13上的接触区15印刷导电胶31。图4中所示为图3中的模块30,在所述模块30中,传递装置2的上面13上的接触区15印有导电胶31,用于与未示出的所述第一电路装置1电接触。
4.通过导电胶31粘贴所述模块30与所述第一电路装置1,用于所述模块30与所述第一电路装置1的电连接。图5示出了所述电路装置4,其由所述第一电路装置1、传递装置2以及所述第二电路装置3构成。与在图3和图4中所示的模块30相比,为了电接触,所述第一电路装置的接触区10与所述传递装置2的接触区15彼此粘贴。所述第一电路装置1的上面6上的元件8通过粘结连接33与导电线路9接触。
为提高被构造为三维多位置电路装置27的电路装置4的机械稳定性,在所述第一电路装置1和所述第二电路装置3之间,引入电绝缘的底充胶34,其至少部分包围所述传递装置2。例如在SMD技术的表层装配中已知一个此类的底充胶34。之后可以进行所述电路装置4的一个最终的功能测试。
在引入所述底充胶34后,所述三维多位置电路装置27可以装入外壳,且进行所述电路装置4的外部连接。在此,所述电路装置1,3中的至少一个,优选地通过导热膏35与一个冷却体21热接触(图7)。
有如下的实施方式:导电板/印刷电路板5,12,17所有的元件组载体,例如STD-基底,低温共烧陶瓷(LTCC),DCB-基底(DCB:直接敷铜),传统导电板。
此外还有如下优点:
-避免了浪费空间的连接元件,如插头、电线、引线框架、粘结,弹性导电板。
-统一了焊接和导电胶装配,尤其是为了互相连接一个控制电子和一个功率电子25,26。
在此,焊接连接29用于高电流区或者所述功率电子26,所述导电粘贴连接32用于低电流区或者控制电子25。
焊接和粘贴装配技术的统一是通过所述传递装置2的使用来实现的。所述传递装置2的任务如下:
-所述第一与第二电路装置1,3的电接触(“布线”)
-所述第一与第二电路装置1,3的热分离,优点特别体现于一个高电流电路装置24和一个低电流电路装置11
-补偿第一与第二电路装置之间的材料电压,且
-分离焊接连接区29与导电粘贴连接区32,其中可以附加引入导电胶31或者底充胶34。
所述装置(第一电路装置1,传递装置2,第二电路装置3)中的每一个优选地首先采用其分别对应的技术(传统电路板,LTCC,DBC,......)进行处理,其中每个装置1,2,3在一个大的基底上进行构造和测试,并随后进行分离。
可替换地对于所示的包含两个电路装置1,3以及一个传递装置2的电路装置4,所述电路装置4也可以包含多于2个的电路装置,所述电路装置通过至少两个传递装置彼此电连接/接触。优选地在此只有一个传递装置的导电连接由焊接连接构成。

Claims (10)

1.一种包括至少一个第一电路装置与至少一个第二电路装置的电子电路装置,其中所述电路装置通过至少一个传递装置的中间连接而互相电连接,其特征在于,传递装置(2)与第一电路装置(1)通过导电胶粘连接(32)电连接,且所述传递装置(2)与所述第二电路装置(3)通过导电胶粘连接(32)和/或通过焊接连接(29)电连接。
2.一种按照权利要求1所述的电路装置,其特征在于,所述传递装置(2)在其上面(13)包含导电胶粘连接(32)用于与所述第一电路装置(1)连接,在其下面(14)包含导电胶粘连接(32)和/或焊接连接(29)用于与所述第二电路装置(3)连接。
3.按照上述权利要求中任一项所述的电路装置,其特征在于,所述传递装置(2)是一个传递电路板(12)或包含至少一个传递电路板(12)。
4.按照上述权利要求中任一项所述的电路装置,其特征在于,所述第一电路装置(1)是一个第一电路板(5)或包含至少一个第一电路板(5)。
5.按照上述权利要求中任一项所述的电路装置,其特征在于,所述第二电路装置(3)是一个第二电路板(17)或包含至少一个第二电路板(17)。
6.按照上述权利要求中任一项所述的电路装置,其特征在于,所述第一电路装置(1)在一个第一电路载体技术下实现。
7.按照上述权利要求中任一项所述的电路装置,其特征在于,所述第二电路装置(3)在一个第二电路载体技术下实现。
8.按照上述权利要求中任一项所述的电路装置,其特征在于,所述导电胶粘连接(32)采用导电胶(31),尤其是印刷导电胶(31)实现。
9.按照上述权利要求中任一项所述的电路装置,其特征在于,所述焊接连接(29)采用焊锡(28),尤其是印刷焊锡(28)实现。
10.用于建立电子电路装置的方法,其所述电子电路装置包含至少一个第一电路装置和至少一个第二电路装置,其中为了电路装置的电连接,在所述电路装置之间安置了一个传递装置,且所述电路装置与所述传递装置电连接,其特征在于,所述传递装置与所述第一电路装置通过导电胶电连接,所述传递装置与所述第二电路装置通过导电胶粘连接和/或通过焊接连接电连接。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8959762B2 (en) 2005-08-08 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
US8572840B2 (en) * 2010-09-30 2013-11-05 International Business Machines Corporation Method of attaching an electronic module power supply
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
US9627230B2 (en) 2011-02-28 2017-04-18 Qorvo Us, Inc. Methods of forming a microshield on standard QFN package
US9807890B2 (en) * 2013-05-31 2017-10-31 Qorvo Us, Inc. Electronic modules having grounded electromagnetic shields
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules

Family Cites Families (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3316017A1 (de) * 1983-05-03 1984-11-08 Siegert GmbH, 8501 Cadolzburg Verfahren zur herstellung elektrischer verbindungen an multisubstratschaltungen, sowie hiernach hergestellte multisubstratschaltungen
US5048717A (en) * 1987-10-26 1991-09-17 Unidynamics Corporation Multiple-product merchandizing machine
US5285926A (en) * 1987-10-26 1994-02-15 Unidynamics Corporation Multiple-product merchandising machine
JPH0363967U (zh) * 1989-10-23 1991-06-21
JPH0426184A (ja) * 1990-05-21 1992-01-29 Nec Corp 厚膜回路基板
US5768109A (en) * 1991-06-26 1998-06-16 Hughes Electronics Multi-layer circuit board and semiconductor flip chip connection
US5329695A (en) * 1992-09-01 1994-07-19 Rogers Corporation Method of manufacturing a multilayer circuit board
US5309629A (en) * 1992-09-01 1994-05-10 Rogers Corporation Method of manufacturing a multilayer circuit board
US5727310A (en) * 1993-01-08 1998-03-17 Sheldahl, Inc. Method of manufacturing a multilayer electronic circuit
US5854302A (en) * 1993-04-29 1998-12-29 The Dow Chemical Company Partially polymerized divinylsiloxane linked bisbenzocyclobutene resins and methods for making said resins
US5719749A (en) * 1994-09-26 1998-02-17 Sheldahl, Inc. Printed circuit assembly with fine pitch flexible printed circuit overlay mounted to printed circuit board
US5604673A (en) * 1995-06-07 1997-02-18 Hughes Electronics Low temperature co-fired ceramic substrates for power converters
US5661647A (en) * 1995-06-07 1997-08-26 Hughes Electronics Low temperature co-fired ceramic UHF/VHF power converters
US6297559B1 (en) * 1997-07-10 2001-10-02 International Business Machines Corporation Structure, materials, and applications of ball grid array interconnections
US6583354B2 (en) * 1999-04-27 2003-06-24 International Business Machines Corporation Method of reforming reformable members of an electronic package and the resultant electronic package
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
SE514424C2 (sv) * 1999-06-17 2001-02-19 Ericsson Telefon Ab L M Övergång mellan symmetrisk och asymmetrisk stripline i ett flerlagers mönsterkort
US6384473B1 (en) * 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US20020061665A1 (en) * 2000-07-03 2002-05-23 Victor Batinovich Method and apparatus for vertically stacking and interconnecting ball grid array (BGA) electronic circuit devices
US6507118B1 (en) * 2000-07-14 2003-01-14 3M Innovative Properties Company Multi-metal layer circuit
US6477054B1 (en) * 2000-08-10 2002-11-05 Tektronix, Inc. Low temperature co-fired ceramic substrate structure having a capacitor and thermally conductive via
US6373348B1 (en) * 2000-08-11 2002-04-16 Tektronix, Inc. High speed differential attenuator using a low temperature co-fired ceramic substrate
US6535083B1 (en) * 2000-09-05 2003-03-18 Northrop Grumman Corporation Embedded ridge waveguide filters
US6600224B1 (en) * 2000-10-31 2003-07-29 International Business Machines Corporation Thin film attachment to laminate using a dendritic interconnection
US6663399B2 (en) * 2001-01-31 2003-12-16 High Connection Density, Inc. Surface mount attachable land grid array connector and method of forming same
US6495771B2 (en) * 2001-03-29 2002-12-17 International Business Machines Corporation Compliant multi-layered circuit board for PBGA applications
CN2481114Y (zh) * 2001-05-08 2002-03-06 富莉科技股份有限公司 一种印刷电路内层基板固著装置
US6707671B2 (en) * 2001-05-31 2004-03-16 Matsushita Electric Industrial Co., Ltd. Power module and method of manufacturing the same
US6788171B2 (en) * 2002-03-05 2004-09-07 Xytrans, Inc. Millimeter wave (MMW) radio frequency transceiver module and method of forming same
US6835682B2 (en) * 2002-06-04 2004-12-28 E. I. Du Pont De Nemours And Company High thermal expansion glass and tape composition
US7141874B2 (en) * 2003-05-14 2006-11-28 Matsushita Electric Industrial Co., Ltd. Electronic component packaging structure and method for producing the same
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US20050225222A1 (en) * 2004-04-09 2005-10-13 Joseph Mazzochette Light emitting diode arrays with improved light extraction
US7241680B2 (en) * 2004-04-30 2007-07-10 Intel Corporation Electronic packaging using conductive interposer connector
FR2872992B1 (fr) * 2004-07-09 2006-09-29 Valeo Vision Sa Assemblage electronique a drain thermique notamment pour module de commande de lampe a decharge de projecteurs de vehicule automobile
US7252408B2 (en) * 2004-07-19 2007-08-07 Lamina Ceramics, Inc. LED array package with internal feedback and control
US7105918B2 (en) * 2004-07-29 2006-09-12 Micron Technology, Inc. Interposer with flexible solder pad elements and methods of manufacturing the same
US7365273B2 (en) * 2004-12-03 2008-04-29 Delphi Technologies, Inc. Thermal management of surface-mount circuit devices
US7317249B2 (en) * 2004-12-23 2008-01-08 Tessera, Inc. Microelectronic package having stacked semiconductor devices and a process for its fabrication
TWI280593B (en) * 2005-06-16 2007-05-01 Via Tech Inc Inductor
TWI268627B (en) * 2005-07-27 2006-12-11 Impac Technology Co Ltd Image sensing module and method for packing the same
US7529013B2 (en) * 2005-08-29 2009-05-05 Samsung Electro-Mechanics Co., Ltd. Optical modulator module package
US20070092179A1 (en) * 2005-10-11 2007-04-26 Samsung Electro-Mechanics Co., Ltd. MEMS module package
US7679201B2 (en) * 2005-12-20 2010-03-16 Intel Corporation Device package
US7365553B2 (en) * 2005-12-22 2008-04-29 Touchdown Technologies, Inc. Probe card assembly
US8704349B2 (en) * 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
JP4916241B2 (ja) * 2006-07-28 2012-04-11 パナソニック株式会社 半導体装置及びその製造方法
US20080029884A1 (en) * 2006-08-03 2008-02-07 Juergen Grafe Multichip device and method for producing a multichip device
US8163600B2 (en) * 2006-12-28 2012-04-24 Stats Chippac Ltd. Bridge stack integrated circuit package-on-package system
US20080218988A1 (en) * 2007-03-08 2008-09-11 Burns Jeffrey H Interconnect for an electrical circuit substrate
US7742311B2 (en) * 2007-04-13 2010-06-22 Hewlett-Packard Development Company, L.P. Damage prevention interposer for electronic package and electronic interconnect structure
TW200906263A (en) * 2007-05-29 2009-02-01 Matsushita Electric Ind Co Ltd Circuit board and method for manufacturing the same
US7687899B1 (en) * 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
KR101373010B1 (ko) * 2007-11-12 2014-03-14 삼성전자주식회사 멀티레이어 cpw 필터유니트 및 그 제조방법
US20090207568A1 (en) * 2008-02-18 2009-08-20 Haveri Heikki Antti Mikael Method and apparatus for cooling in miniaturized electronics
KR20100037300A (ko) * 2008-10-01 2010-04-09 삼성전자주식회사 내장형 인터포저를 갖는 반도체장치의 형성방법
US8405229B2 (en) * 2009-11-30 2013-03-26 Endicott Interconnect Technologies, Inc. Electronic package including high density interposer and circuitized substrate assembly utilizing same
US8245392B2 (en) * 2009-12-01 2012-08-21 Endicott Interconnect Technologies, Inc. Method of making high density interposer and electronic package utilizing same
US8653654B2 (en) * 2009-12-16 2014-02-18 Stats Chippac Ltd. Integrated circuit packaging system with a stackable package and method of manufacture thereof

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