CN101771037A - 减小衬底中的高频信号损失 - Google Patents
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Abstract
本发明涉及减小衬底中的高频信号损失。一种集成电路结构，包括：第一导电类型的半导体衬底；和半导体衬底中的耗尽区。深阱区基本被耗尽区包围，其中深阱区是与第一导电类型相反的第二导电类型。耗尽区包括直接位于深阱区之上的第一部分和直接位于深阱区之下的第二部分。集成电路装置直接设置在耗尽区之上。
Description
技术领域
本发明一般涉及集成电路，并且特别涉及高频集成电路装置，尤其是减小衬底中信号损失的结构和方法。
背景技术
高频电路被广泛使用于现代应用中，如无线通信应用。设计者面对的普遍问题是位于高频电路下面的衬底中的信号损失，部分信号损失由形成在高频电路和下面的衬底之间的寄生电容导致。通常，随着信号频率的增大，损失也增大。这大大限制了高频电路的设计。
图1说明了形成在半导体衬底2之上的传统射频(RF)变压器4。电介质层8将射频变压器4与半导体衬底2分隔开。射频变压器4和半导体衬底2一起形成寄生电容6。不希望产生的寄生电容6将射频变压器4的工作频率限制在10G赫兹左右和更低的频率。当频率进一步增大，半导体衬底2中的信号损失大大增大。
当其它集成电路装置工作在高频下时，这些装置也发生信号损失。例如，图2说明了形成于P+扩散区14和N型阱区16之间的结型二极管12。P+扩散区14和N型阱区16都形成在衬底18内。同样，在P+扩散区14，N型阱区16和衬底18之间，在衬底18和连接到结型二极管12的金属线之间和其他类似区域形成寄生电容20。寄生电容20导致结型二极管12携带的信号中的极大信号损失，这个损失可能严重到大约4到5分贝。类似地，其他二极管如鳍式场效应晶体管二极管和肖特基二极管也遭受类似的问题。
而且，信号损失问题可能随着集成电路尺寸的不断缩小而加剧，集成电路尺寸的缩小导致高频装置和各自的底层衬底之间的距离越来越小。减小的距离导致寄生电容的增加。因此，需要方案解决上述问题。
发明内容
根据本发明的一个方面，一种集成电路结构包括：第一导电类型的半导体衬底；和在半导体衬底中的耗尽区。深阱区基本上被耗尽区包围，并且深阱区是与第一导电类型相反的第二导电类型。耗尽区包括直接位于深阱区之上的第一部分和直接位于深阱区下的第二部分。集成电路装置直接位于耗尽区之上。也公开了其他实施例。
实施例的优势特征包括减少了高频装置的信号损失。另外，实施例可能与现有的制造工艺相结合，不要求额外工艺步骤和光刻掩模。
附图说明
为了更全面地理解本发明和其优点，参考下述的附图描述，其中：
图1说明了形成在半导体衬底之上的传统射频变压器；
图2说明了形成在半导体衬底之上的传统二极管；
图3A和3B分别说明了本发明的变压器实施例的透视图和俯视图；
图4，5和6分别说明了结型二极管实施例，鳍式场效应晶体管二极管实施例和肖特基二极管实施例的横截面图；
图7和8显示了从传统二极管和本发明的二极管实施例获得的仿真结果的比较。
具体实施方式
下面详细讨论实施例的制造和使用。然而，应该意识到，实施例提供了很多可以广泛体现在各种不同的具体情况中的的应用发明概念。讨论的具体实施例只是说明发明的制造和使用的具体方法，不限制发明范围。
本发明提出了一种新的衬底-损失减少的结构和方法。讨论本发明的制造实施例的中间步骤。也讨论了不同实施例。在本发明的不同视图和说明性实施例中，使用相似的参考数字标记相似的元件。
图3A说明本发明的一个实施例的透视图，其中包括衬底30。衬底30可能包含硅，锗，砷化镓，和/或其它普遍使用的半导体材料。衬底30可能是体材料衬底，或者具有绝缘底半导体结构。实施例中，衬底30轻掺杂p型杂质，例如，浓度低于1011/cm3，因此，以下被称为P型衬底。或者，衬底30可能轻掺杂n型杂质。射频变压器32形成在衬底30之上。射频变压器32和衬底30之间的间隔34可能包括电介质层，如层间电介质(ILD)，在其中形成晶体管的栅电极(未显示)和接触栓塞48的，和金属间电介质层(IMD)，在其中形成金属线和通孔(未显示)的。
变压器32可能有四个端子，命名为X1A，X1B，X2A和X2B。端子X1A和X2A通过金属线和通孔互连。端子X1B和X2B通过金属线和通孔互连。因此，变压器32包括两个电感，一个连接在端子X1A和X2A之间，另一个连接在端子X1B和X2B之间。
深N型阱区36形成在衬底30内，其顶表面38比衬底30的顶表面40低。实施例中，深N型阱区36通过在衬底30的深处注入n型杂质如磷和砷形成。或者，深N型阱区36可能是通过对衬底30的表层进行扩散和掺杂而形成。因此，深N型阱区36内埋在衬底30内，并且p型层位于深N型阱区36之上。应该意识到，由于注入n型杂质的分布，深N型阱区36可能没有明显的顶表面和底层。实施例中，位于深N型阱区36的顶表面和底层之间的中间层的深度D为大约1μm。然而，本领域的普通技术人员也应该认识到，描述中列举的尺寸仅是例子，如果使用不同的构成技术，尺寸将改变。
深N型阱区36通过n型栓塞44，46和接触栓塞48连接到电压源50。实施例中，n型栓塞44与n型阱区同时形成，用来组成其中的pMOS晶体管(未显示)。因此，n型栓塞44基本上和n型阱区有同样的杂质浓度。深N型阱区的顶表面38不比n型栓塞44的底层低，因此它们相互连接。N型栓塞46可能与nMOS晶体管的源极/漏极区域同时形成(未显示)，因此N+区域的浓度可能，例如，比大约1×1020/cm3高。接触栓塞48可能形成于ILD内，并可能与连接到pMOS和NMOS晶体管的源极/漏极区域和栅极的接触栓塞(未显示)同时形成。注意，深N型阱区36可能使用任何其他的适当连接方式连接到电压源50。
电压源50提供正向偏置电压给深N型阱区36。因此，耗尽区形成于包围深N型阱区36的衬底30的一部分中。实施例中，应用到深N型阱区36的电压足够高，能够耗尽直接位于深N型阱区36之上的衬底30的一部分。换句话说，耗尽区52延伸到衬底30的顶表面40。认识到，寄生电容54存在于射频变压器32和衬底30之间。耗尽区52的形成的影响是以耗尽区52的厚度增加寄生电容54的电容绝缘体的等效厚度。结果，寄生电容54的电容减小了，导致衬底30中的信号损失降低了(信号损失下述被称为衬底损失)。实施例中，所有寄生电容的总电容值可能被减小了约50％。
为了使得减小寄生电容值的作用最大化，最好增加耗尽区52的厚度T，这可以通过增加正向偏置电压获得。实施例中，偏置电压是工作电压VDD，是提供给核心电路的正向电源电压，但是偏置电压也可以是任何其他的正向电压。为了进一步增大耗尽区52的面积，正向偏置电压可能被增大到比电压VDD高。例如，电压源50可能是提供比电压VDD高的正向电源电压的输入/输出(I/O)电压源。
图3B说明了射频变压器32，深N型阱区36和耗尽区52的典型俯视图。耗尽区52可能是在所有平面方向(平行于衬底30的表面的方向)延伸到变压器32的边缘外的连续区域。因此，耗尽区52的面积(俯视)可能至少基本接近于射频变压器32的面积，甚至比它大。耗尽区52的面积可能比射频变压器32的面积大10％，甚至100％。如图3A所示，耗尽区52的增加可能有利于减小寄生电容54的电容值。实施例中，深N型阱区36包括多个彼此之间被p型衬底30的部分分隔开的平行指(也标记为36)。平行指36之间可能通过深N型阱区36连接。为了减小形成在深N型阱区36内的感应电流，指最好尽可能的窄，宽度W接近或者甚至等于最小规则所定义的尺寸(形成技术允许的最小宽度)。使用偏置电压时，邻近指的耗尽区重叠形成连续的耗尽区52。在另一类实施例中，深N型阱区36可能有任意其他样式，如网状，只要它能够形成连续耗尽区52。在又另一类实施例中，深N型阱区36可能是连续N型阱板。
耗尽区52的形成导致衬底损失的减小。仿真结果显示射频变压器32的品质因数从37左右增加到45左右。
图4到图6是具有深N型阱区36和与二极管结合的对应耗尽区52的实施例。这些实施例中，深N型阱区36，电压源50，和应用到N型阱区36的偏置电压可以基本上与图3A和3B中的实施例一样。为了简化，在此不再重复这些区域的设计细节和说明。图4说明了形成在P+扩散区62和N型阱区64之间的结二极管60。P+扩散区62和N型阱区64可通过注入形成，因此，P+扩散区62和N型阱区64的顶表面也可以是衬底30的顶表面。N型阱区64通过p型的衬底30的一部分与深N型阱区36分离。类似地，耗尽区52从顶部，底部和所有可能的外侧方向包围深N型阱区36。而且，耗尽区52延伸到N型阱区64和深N型阱区36之间的间隔中，因此，N型阱区64和深N型阱区36彼此分离。接触栓塞66连接到P+扩散区62和N型阱区64，并进一步连接到可能形成于底部金属层的金属线68(通常记为M1)。由于等效电容绝缘体厚度的增加，结型二极管60和衬底30之间的寄生电容69的电容值被有效减小，结果，衬底损失减小了。
图5说明本发明的另一实施例，包括形成在衬底30之上的鳍式场效应晶体管二极管70。鳍式场效应晶体管二极管70包括P+扩散区72(也被称为鳍(fin)72)和N+扩散区74(也被称为fin 74)，它们相互接触形成P-N结。P+扩散区72和N+扩散区74的底层可能与衬底30的顶表面接触。形成接触栓塞66和金属线68连接到扩散区72和74。P+扩散区72和N+扩散区74通过p型衬底30的一部分与深N型阱区36分隔开。类似地，耗尽区52从顶部，底部和所有可能的外侧方向充分地包围深N型阱区36。而且，耗尽区52将P+扩散区72和N+扩散区74同深N型阱区36分离开。
图6说明了本发明的又另一实施例，包括形成在耗尽区52之上的肖特基二极管80。肖特基二极管形成在N型阱区82和可能包含钨的金属接触栓塞661之间，可能与金属栓塞48和662同时形成。N+区84形成在N型阱区82内，作为N型阱区82的拾取区。再次，p型区存在于N型阱区82和深N型阱区36之间，当应用来自于电压源50的偏置电压时，p型区被耗尽。
图4到图6所示的实施例中，耗尽区52的面积至少基本接近于各自覆盖的二极管60，70和80的面积，最好比它们大。耗尽区52的面积可能也比各自覆盖的二极管60，70和80的面积达10％，或者甚至约100％。因此，除了基本重叠所有的覆盖二极管60，70和80(分别见图4，5和6)，耗尽区52可能进一步水平延伸，至少在一些或可能所有的外侧方向超出覆盖二极管60，70和80的边缘。
尽管上述段落讨论的实施例中，使用正向电压偏置深N型阱区36形成p型衬底30中的耗尽区，在另一类实施例中，区域30，36，44，46，48和/或形成二极管的其他区域的导电类型可能是相反的。这种情况下，现在是p型的深阱区，可能用负向电压偏置形成耗尽区52。
图7和8说明二极管的仿真结果，其中衬底损失(Y轴)作为频率(X轴)的函数。图7从传统的无耗尽区结构的二极管采样获得。注意到，大约67G赫兹时，衬底损失在大约4.5到5分贝之间。随着频率的增大，衬底损失变得越来越严重。作为对比，图8是从本发明的实施例采样获得的。注意到，大约67G赫兹时，衬底损失在大约2.2到5.7分贝之间，大大低于图7所示的衬底损失。本发明的实施例的进一步优势特征是：随着频率的增大，没有观测到衬底损失的增加。这意味着，本发明实施例的工作频率可以扩展到更高的频率范围。
尽管详细描述了本发明和它的优点，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改和替换。而且，本应用的范围不局限于说明书中描述的过程，装置，制造，和组成的问题，手段，方法和步骤的具体实例。对于本领域的普通技术人员，应感激本发明的公开，根据本发明，现存的或今后开发的执行相同的功能或获得相同结果的过程，装置，制造，组成的问题，手段，方法或步骤可能被使用。因此，所附权利要求应该包括在这样的过程，装置，制造，组成的问题，手段，方法，或步骤的范围内。另外，每个要求构成一个单独的实施例，各种不同的要求和实施例的结合在本发明的范围内。
Claims (15)
1.一种集成电路结构，包括：
第一导电类型的半导体衬底；
半导体衬底中的耗尽区；
基本被耗尽区包围的深阱区，其中深阱区是与第一导电类型相反的第二导电类型，而耗尽区包括直接位于深阱区之上的第一部分和直接位于深阱区之下的第二部分；以及
直接位于深阱区之上的集成电路装置。
2.根据权利要求1的集成电路结构，其中深阱区是n型的，直接位于深阱区之上的半导体衬底的部分和直接位于深阱区之下的半导体衬底的部分是p型的。
3.权利要求2的集成电路结构，还包括连接到深阱区的电压源，其中电压源被设置为提供正向电压给深阱区。
4.根据权利要求3的集成电路结构，其中正向电压是核心电路的正向电源电压或输入/输出电路的正向电源电压。
5.根据权利要求1的集成电路结构，其中集成电路装置是射频变压器，所述集成电路结构还包括在半导体衬底之上、且将耗尽区与射频变压器分隔的电介质层。
6.根据权利要求1的集成电路结构，其中集成电路装置是二极管，其中二极管是结型二极管，其包括在半导体衬底中的第一阱区和在第一阱区中的第二阱区，其中第一阱区和第二阱区具有相反的导电类型；或者，其中二极管是鳍式场效应晶体管二极管，其包括在半导体衬底上的第一鳍式区，和在半导体衬底上与第一鳍式区接触的第二鳍式区；其中第一鳍式区和第二鳍式区具有相反的导电类型；
或者，其中二极管是肖特基二极管。
7.根据权利要求1的集成电路结构，其中深阱区包括多个相互平行的深阱指，其中多个深阱指的宽度接近于形成集成电路结构的技术的最小宽度。
8.一种集成电路结构，包括：
第一导电类型的半导体衬底；
在半导体衬底中的深阱区，其顶表面比半导体衬底的顶表面低，其中所述深阱区是与第一导电类型相反的第二导电类型；
连接到深阱区的电压源；
直接位于深阱区之上的射频变压器；以及
将射频变压器与半导体衬底的顶表面分隔开的电介质层。
9.根据权利要求8的集成电路结构，其中第一导电类型是p型，第二导电类型是n型，其中电压源被设置为提供正向电压，其中电压源被设置为提供核心电路的正向电源电压给深阱区。
10.权利要求8的集成电路结构，还包括基本包围深阱区的耗尽区，其中耗尽区从深阱区的顶表面延伸到半导体衬底的顶表面，且耗尽区的面积基本上不比射频变压器的面积小，其中耗尽区的面积比射频变压器的面积大，且耗尽区在所有外侧方向上侧向延伸到超过相应射频变压器的边缘，优选地其中深阱区包括多个深阱指，耗尽区在这些深阱指之间延伸。
11.一种集成电路结构，包括：
第一导电类型的半导体衬底；
二极管；
在半导体衬底中且直接位于二极管之下的深阱区，其中深阱区是与第一导电类型相反的第二导电类型；以及
包括直接位于深阱区之上的第一部分和直接位于深阱区之下的第二部分的耗尽区，其中第一部分将深阱区与二极管分隔开。
12.根据权利要求11的集成电路结构，其中二极管是结型二极管，包括在半导体衬底中的第一阱区和在第一阱区中的第二阱区，其中第一阱区和第二阱区具有相反的导电类型；
或者，其中耗尽区延伸到半导体衬底的顶表面，其中二极管是鳍式场效应晶体管二极管，包括在半导体衬底之上的第一鳍式区和在半导体衬底之上并与第一鳍式区接触的第二鳍式区，其中第一鳍式区和第二鳍式区具有相反的导电类型；
或者，其中二极管是肖特基二极管，包括：
半导体衬底中的掺杂半导体区；和
与掺杂半导体区接触的金属接触栓塞。
13.权利要求11的集成电路结构，还包括连接到深阱区、提供正向电压来产生耗尽区的电压源。
14.根据权利要求8、11的集成电路结构，其中第一导电类型是n型，第二导电类型是p型，其中电压源被设置为提供负向电压。
15.根据权利要求11的集成电路结构，其中耗尽区的面积基本不比二极管的面积小，优选地其中耗尽区的面积比二极管的面积大，其中耗尽区基本在所有外侧方向上侧向延伸到超过相应二极管的边缘。
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101866919A (zh) * | 2009-04-15 | 2010-10-20 | 中国台湾积体电路制造股份有限公司 | 集成电路结构 |
| CN101866919B (zh) * | 2009-04-15 | 2012-12-12 | 台湾积体电路制造股份有限公司 | 集成电路结构 |
Also Published As
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| US20120161285A1 (en) | 2012-06-28 |
| US8390095B2 (en) | 2013-03-05 |
| US8129817B2 (en) | 2012-03-06 |
| CN101771037B (zh) | 2013-03-13 |
| US20100164069A1 (en) | 2010-07-01 |
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