CN101715604B - 深硅刻蚀上掩膜底切的最小化 - Google Patents

深硅刻蚀上掩膜底切的最小化 Download PDF

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Publication number
CN101715604B
CN101715604B CN2008800201535A CN200880020153A CN101715604B CN 101715604 B CN101715604 B CN 101715604B CN 2008800201535 A CN2008800201535 A CN 2008800201535A CN 200880020153 A CN200880020153 A CN 200880020153A CN 101715604 B CN101715604 B CN 101715604B
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China
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mask
polymer
gas
plasma
silicon layer
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Expired - Fee Related
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CN2008800201535A
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Chinese (zh)
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CN101715604A (zh
Inventor
塔玛拉克·潘杜姆索波尔恩
帕特里克·钟
杰基濑户
S.M·列扎·萨贾迪
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Lam Research Corp
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Lam Research Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)
CN2008800201535A 2007-06-18 2008-06-02 深硅刻蚀上掩膜底切的最小化 Expired - Fee Related CN101715604B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/820,334 US8262920B2 (en) 2007-06-18 2007-06-18 Minimization of mask undercut on deep silicon etch
US11/820,334 2007-06-18
PCT/US2008/065578 WO2008157018A1 (en) 2007-06-18 2008-06-02 Minimization of mask undercut on deep silicon etch

Publications (2)

Publication Number Publication Date
CN101715604A CN101715604A (zh) 2010-05-26
CN101715604B true CN101715604B (zh) 2012-02-01

Family

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CN2008800201535A Expired - Fee Related CN101715604B (zh) 2007-06-18 2008-06-02 深硅刻蚀上掩膜底切的最小化

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Country Link
US (2) US8262920B2 (enExample)
JP (1) JP5437237B2 (enExample)
KR (1) KR101476477B1 (enExample)
CN (1) CN101715604B (enExample)
TW (1) TWI446437B (enExample)
WO (1) WO2008157018A1 (enExample)

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JP5093854B2 (ja) * 2009-03-25 2012-12-12 Ｓｐｐテクノロジーズ株式会社 エッチング方法
US8158522B2 (en) * 2009-09-25 2012-04-17 Applied Materials, Inc. Method of forming a deep trench in a substrate
KR101908113B1 (ko) * 2009-11-16 2018-10-15 삼성전자 주식회사 전기활성 폴리머 엑츄에이터 및 그 제조방법
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US9059101B2 (en) * 2011-07-07 2015-06-16 Lam Research Corporation Radiofrequency adjustment for instability management in semiconductor processing
CN102956543B (zh) * 2011-08-25 2015-06-03 上海华虹宏力半导体制造有限公司 一种硅通孔的制作方法
US8597982B2 (en) * 2011-10-31 2013-12-03 Nordson Corporation Methods of fabricating electronics assemblies
KR102223145B1 (ko) 2014-07-04 2021-03-05 삼성디스플레이 주식회사 박막 트랜지스터 기판, 이를 갖는 액정 표시 패널 및 이의 제조방법
US10049892B2 (en) * 2015-05-07 2018-08-14 Tokyo Electron Limited Method for processing photoresist materials and structures
US9711359B2 (en) * 2015-08-13 2017-07-18 Lam Research Corporation Shadow trim line edge roughness reduction
US10366902B2 (en) 2016-02-22 2019-07-30 Tokyo Electron Limited Methods for cyclic etching of a patterned layer
US9773643B1 (en) * 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10002773B2 (en) * 2016-10-11 2018-06-19 Lam Research Corporation Method for selectively etching silicon oxide with respect to an organic mask
US10134600B2 (en) * 2017-02-06 2018-11-20 Lam Research Corporation Dielectric contact etch
US9779956B1 (en) * 2017-02-06 2017-10-03 Lam Research Corporation Hydrogen activated atomic layer etching
CN111063655A (zh) * 2018-10-17 2020-04-24 无锡华润上华科技有限公司 一种半导体器件的制造方法
CN114127890B (zh) 2019-05-01 2025-10-14 朗姆研究公司 调整的原子层沉积
KR20220006663A (ko) 2019-06-07 2022-01-17 램 리써치 코포레이션 원자 층 증착 동안 막 특성들의 인-시츄 (in-situ) 제어
US11177137B2 (en) * 2020-01-17 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer etching process and methods thereof

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Also Published As

Publication number Publication date
US20120298301A1 (en) 2012-11-29
TWI446437B (zh) 2014-07-21
KR20100035159A (ko) 2010-04-02
TW200908141A (en) 2009-02-16
US20080308526A1 (en) 2008-12-18
JP2010530643A (ja) 2010-09-09
CN101715604A (zh) 2010-05-26
JP5437237B2 (ja) 2014-03-12
US8262920B2 (en) 2012-09-11
KR101476477B1 (ko) 2014-12-24
WO2008157018A1 (en) 2008-12-24

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