CN101656206B - 形成半导体元件及其金属栅极堆叠的方法 - Google Patents
形成半导体元件及其金属栅极堆叠的方法 Download PDFInfo
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- CN101656206B CN101656206B CN2009101658760A CN200910165876A CN101656206B CN 101656206 B CN101656206 B CN 101656206B CN 2009101658760 A CN2009101658760 A CN 2009101658760A CN 200910165876 A CN200910165876 A CN 200910165876A CN 101656206 B CN101656206 B CN 101656206B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 115
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 93
- 239000002184 metal Substances 0.000 title claims abstract description 93
- 238000000034 method Methods 0.000 title claims abstract description 83
- 238000001312 dry etching Methods 0.000 claims abstract description 53
- 239000003989 dielectric material Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 39
- 239000011435 rock Substances 0.000 claims description 33
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 26
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 14
- 239000001301 oxygen Substances 0.000 claims description 14
- 229910052760 oxygen Inorganic materials 0.000 claims description 14
- 229910052786 argon Inorganic materials 0.000 claims description 13
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 9
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 238000001556 precipitation Methods 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 93
- 239000000463 material Substances 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 238000000059 patterning Methods 0.000 description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 239000000908 ammonium hydroxide Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 125000001153 fluoro group Chemical group F* 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 150000002978 peroxides Chemical class 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- -1 -tert-butyl amino silane Chemical compound 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- VGRFVJMYCCLWPQ-UHFFFAOYSA-N germanium Chemical compound [Ge].[Ge] VGRFVJMYCCLWPQ-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- VYIRVGYSUZPNLF-UHFFFAOYSA-N n-(tert-butylamino)silyl-2-methylpropan-2-amine Chemical compound CC(C)(C)N[SiH2]NC(C)(C)C VYIRVGYSUZPNLF-UHFFFAOYSA-N 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
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Abstract
本发明提供一种形成半导体元件及其金属栅极堆叠的方法,包括下列步骤:于一蚀刻腔室内,通过一图案化掩模的定义栅极区的开口对一半导体基底进行一第一干蚀刻步骤,以移除位于该半导体基底上的一多晶硅层及一金属栅极层;于该蚀刻腔室内提供一水蒸汽至该半导体基底,以移除位于该半导体基底上的一盖层;以及于该蚀刻腔室内对该半导体基底进行一第二干蚀刻步骤,以移除一高介电常数(high k)介电材料层。本发明具有工艺简单、制造周期短及有效降低成本的优点。
Description
技术领域
本发明涉及半导体元件的制造方法,特别涉及半导体元件的金属栅极堆叠的制造方法。
背景技术
当例如金属氧化物半导体场效应晶体管(metal-oxide-semiconductorfield-effect transistor;MOSFET)的半导体元件随着各种技术节点(technologynode)的改变而微缩化时,高介电常数(high k)介电材料及金属被用来形成栅极堆叠(gate stack)。于一形成金属栅极堆叠(metal gate stack)的方法中,需进行多个干蚀刻步骤及湿蚀刻步骤。举例而言,当盖层设置于high k介电材料层及金属栅极层之间时,需要在两个干蚀刻步骤之间进行一湿蚀刻步骤以移除盖层,并减少严重影响产品特性的残余物。因此,为形成金属栅极堆叠,需要进行多重蚀刻步骤且应用多个蚀刻装置。在此例子中,蚀刻方法包括一干蚀刻步骤、一湿蚀刻步骤、以及一第二干蚀刻步骤。然而,如此金属栅极蚀刻方法具有工艺复杂及制造周期时间长的缺点,且提高了制造成本。
发明内容
为了解决现有技术存在的上述问题,本发明提供一种形成半导体元件的金属栅极堆叠的方法,包括下列步骤:于一蚀刻腔室内,通过一图案化掩模的定义栅极区的开口对一半导体基底进行一第一干蚀刻步骤,以移除位于该半导体基底上的一多晶硅层及一金属栅极层;于该蚀刻腔室内提供一水蒸汽至该半导体基底,以移除位于该半导体基底上的一盖层;以及于该蚀刻腔室内对该半导体基底进行一第二干蚀刻步骤,以移除一高介电常数(high k)介电材料层。
本发明也提供一种形成半导体元件的金属栅极堆叠的方法,包括下列步骤:于一蚀刻腔室内,通过一图案化掩模的定义栅极区的开口对一半导体基底进行一第一干蚀刻步骤,以移除位于该半导体基底上的一栅极金属层;于该蚀刻腔室内提供一氧等离子体及氩等离子体中的至少一个至该半导体基底,以移除一盖层;于该蚀刻腔室内对该半导体基底进行一第二干蚀刻步骤,以移除一high k介电材料层;以及对该半导体基底进行一湿蚀刻步骤以移除一聚合残余物。
本发明还提供一种形成半导体元件的方法,包括下列步骤:于一蚀刻腔室内对一半导体基底进行一第一干蚀刻步骤以移除位一金属栅极层;于该蚀刻腔室内提供一水蒸汽、氧等离子体、及氩等离子体中的至少一个至该半导体基底以移除一盖层;以及于该蚀刻腔室内对该半导体基底进行一第二干蚀刻步骤以移除一high k介电材料层,借此形成一栅极堆叠。
本发明具有工艺简单、制造周期短及有效降低成本的优点。
附图说明
图1为根据本发明概念所构成的一实施例的方法100的流程图,用以形成具有金属栅极堆叠的半导体元件。
图2为根据本发明概念的一实施例,其所形成的具有金属栅极堆叠的半导体结构的剖面图。
上述附图中的附图标记说明如下:
210~基底;212~氧化硅层;214~高介电常数介电材料层;216~盖层;218~金属栅极层;220~多晶硅层;222~图案化掩模。
具体实施方式
有关各实施例的制造和使用方式如以下所详述。然而,值得注意的是,本发明所提供的各种可应用的发明概念依具体内文的各种变化据以实施,且在此所讨论的具体实施例仅是用来显示具体使用和制造本发明的方法,而不用以限制本发明的范围。以下通过各种附图及例式说明本发明较佳实施例的制造过程。在本发明各种不同的各种实施例和附图中,相同的符号代表相同或类似的元件。此外,当一层材料层是位于另一材料层或基板之上时,其可以是直接位于其表面上或另外插入有其他中介层。
图1为根据本发明概念所构成的一实施例的方法100的流程图,用以形成具有金属栅极堆叠(metal gate stack)的半导体元件。图2为一实施例所形成的具有金属栅极堆叠的半导体结构200的剖面图。半导体元件的形成方法100参照图1及图2作说明。
方法100起始于步骤102,提供一半导体基底210。半导体基底210包括硅。半导体基底210也可包括锗(germanium)或硅锗(silicon germanium)。在其他实施例中,可使用其他半导体材料用作半导体基底210,例如钻石(diamond)、碳化硅(silicon carbide;SiC)、砷化镓(gallium arsenic;GaAs)、磷砷化镓(gallium arsenic phosphorous;GaAsP)、砷化铝铟(aluminum indiumarsenic;AlInAs)、砷化铝镓(aluminum gallium arsenic;AlGaAs)、磷化镓铟(gallium indium phosphorus;GaInP)、或其其他适合的组合。
方法100进行至步骤104,于半导体基底210上形成多个金属栅极堆叠材料层(metal-gate-stack material layers)。在一实施例中,高介电常数(high k)介电材料层形成于半导体基底上。金属栅极层形成于high k介电材料层上。此外,盖层更插介于high k介电材料层及金属栅极层之间。high k介电材料层是以适当的方法形成,例如原子层沉积法(atomic layer deposition;ALD)。其他形成high k介电材料层的方法包括金属有机化学气相沉积法(metalorganic chemical vapor deposition;MOCVD)、物理气相沉积法(physical vapordeposition;PVD)、紫外光臭氧氧化法(ultraviolet UV-Ozone Oxidation)、及分子束外延法(molecular beam epitaxy;MBE)。在一实施例中,high k介电材料包括氧化铪(hafnium oxide;HfO2)。在其他实施例中,high k介电材料包括氧化铝(aluminum oxide;Al2O3)。或者是,high k介电材料包括金属氮化物(metalnitride)、金属硅化物(metal silicate)、或其他金属氧化物(metal oxide)。
金属栅极层是以PVD法或其他适合的方法形成。金属栅极层包括氮化钛(titanium nitride)。在其他实施例中,金属栅极层包括氮化钽(tantalumnitride)、氮化钼(molybdenum nitride)、或氮化铝钛(titanium aluminum nitride)。盖层插介于high k介电材料层及金属栅极层之间。盖层包括氧化镧(lanthanumoxide;LaO)。盖层也可包括其他适合的材料。
图2显示一实施例的金属栅极层,并叙述如下。薄热氧化硅层212形成于硅基底210上。以ALD法或其他适合的方法于热氧化硅层212上形成highk介电材料层214。high k介电材料包括氧化铪(HfO2)或其他适合的材料。盖层216形成于high k介电材料层214上。盖层216包括氧化镧或其他适合的材料。以PVD法或其他适合的方法于盖层216上形成金属栅极层218。金属栅极层包括氮化钛或其他前述适合的材料。以CVD法或其他适合的方法于金属栅极层218上形成多晶硅层220。
方法100进行至步骤106,于一干蚀刻装置中,尤其是于一干蚀刻腔室中,利用具有多个开口的图案化掩模222进行第一干蚀刻步骤,以图案化多晶硅层220及金属栅极层218。第一干蚀刻步骤移除位于图案化掩模的开口内的多晶硅层及金属栅极层。在一实施例中,第一干蚀刻步骤利用含氟等离子体(fluorine-containing plasma)移除多晶硅层及金属栅极层。尤其是,第一干蚀刻步骤是使用氟碳等离子体(fluorocarbon plasma)。在一实施例中,蚀刻气体包括CF4。在其他实施例中,是分开进行两个具有不同蚀刻气体的蚀刻步骤,以分别蚀刻多晶硅层及金属栅极层。举例而言,蚀刻多晶硅的气体可包括Cl2、HBr、O2、或其组合。
图案化掩模222形成于多层的金属栅极堆叠层(multiple metal-gate-stacklayers)上。在一实施例中,图案化掩模222形成于多晶硅层220上,如图2所示。在一实施例中,图案化掩模层222包括以光刻(photolithography)步骤所形成的图案化光致抗蚀剂层。光刻步骤可包括光致抗蚀剂层涂布、软烤(softbaking)、掩模对准、曝光、曝光后烘烤(post-exposure baking)、显影(developingphotoresist)及硬烤(hard baking)步骤。也可以例如无光掩模光刻(masklessphotolithography)、电子束刻写(electron-beam writing)、离子束刻写(ion-beamwriting)及分子转印(molecular imprint)的其他适合的方法进行或取代光刻曝光步骤。
在其他实施例中,图案化掩模层222包括图案化硬掩模层。在一实施例中,图案化掩模层222包括氮化硅。于形成图案化氮化硅硬掩模的例子中,以低压化学气相沉积法(low pressure chemical vapor deposition;LPCVD)于多晶硅层上形成氮化硅层。在以CVD法形成氮化硅层的步骤中,所使用的前驱物包括二氯硅烷(dichlorosilane;DCS或SiH2Cl2)、双叔丁基氨基硅烷(bis(TertiaryButylAmino)Silane;BTBAS或C8H22N2Si)、及二硅烷disilane(DS或Si2H6)。接着利用光刻步骤将光致抗蚀剂层图案化,并进行蚀刻步骤蚀刻位于图案化光致抗蚀剂层的开口内的氮化硅以进一步图案化氮化硅层。或者,可利用其他介电材料作为图案化硬掩模。举例而言,可以氮氧化硅(siliconoxynitride)用作硬掩模。
方法100进行至步骤108,于相同的干蚀刻装置中提供水蒸汽(H2O steam)至半导体结构200以图案化盖层216。在一实施例中,步骤108于进行第一干蚀刻步骤的相同蚀刻腔室中进行。位于图案化掩模层222的开口内的盖层216于此步骤中以水蒸汽移除。优点是,于先前蚀刻步骤所形成的聚合残余物(polymeric residue)可实质上同样地以水蒸汽移除。镧/氧化镧可与水蒸汽反应且借此移除。可于低压环境下自蚀刻腔室将排气(exhaustive gas)抽出。
除了水蒸汽,方法100也可于相同的干蚀刻装置内,特别是于相同的干蚀刻腔室内,使用氧等离子体或氩等离子体图案化半导体结构200的盖层216。位于图案化掩模层的开口内的盖层216是通过氧等离子体或氩等离子体予以移除。类似先前所述的,聚合残余物实质上也同样地通过氧等离子体或氩等离子体予以移除。氧等离子体或氩等离子体是于室温下供至半导体结构200。或者,氧等离子体或氩等离子体可于介于约20℃至50℃的温度下供至半导体结构200。
方法100进行至步骤110,于相同的干蚀刻装置内,特别是于相同的干蚀刻腔室内,进行第二干蚀刻步骤以图案化high k介电材料层214。第二干蚀刻步骤调整蚀刻剂及蚀刻环境以有效的移除high k介电材料层。位于图案化掩模的开口内的high k介电材料层实质上是通过第二干蚀刻步骤予以移除。在一实施例中,第二干蚀刻步骤是利用含氟等离子体移除high k介电材料层。在其他实施例中,第二干蚀刻步骤是利用含有氟、氯及惰性气体中的至少一个气体移除high k介电材料层。
方法100进行至步骤112,进行湿蚀刻步骤以移除位于基底和/或金属栅极堆叠的侧壁上的聚合残余物或其他残余物。此湿蚀刻步骤设计用以有效的移除聚合残余物或其他污染物。举例而言,此湿蚀刻步骤使用含有氢氧化铵(ammonium hydroxide;NH4OH)及过氧化氢(peroxide;H2O2)的SC 1溶液。在其他实施例中,此湿蚀刻步骤可使用一含有硫酸(sulfuric acid;H2SO4)及过氧化氢(peroxide;H2O2)的溶液。湿蚀刻步骤可于一湿蚀刻装置内进行。
在此方法中,用以移除金属栅极层的第一干蚀刻步骤、用以移除high k介电材料层的第二干蚀刻步骤、及以水蒸汽或氧/氩等离子体移除盖层的蚀刻步骤整合于相同蚀刻装置,特别是相同蚀刻腔室内进行,因此简化了工艺且缩短周期时间,此外,更降低了制造成本。所述方法利用水蒸汽或氧/氩等离子体施于半导体结构以有效移除例如LaO的盖层及聚合残余物。应了解的是,于此所讨论的实施例包括几种不同的实施例,而并非所有的实施例都具有特别的优点。
虽然未显示出,本发明实施例也可包含其他步骤以形成多个掺杂区域,例如源极及漏极区,或形成例如多重内连线(multilayer interconnection;MLI)的元件。在一实施例中,轻掺杂漏极(lightly doped drain;LDD)区于栅极堆叠形成之后形成。栅极间隙壁(gate spacer)可形成于金属栅极堆叠的侧壁上。接着,源极及漏极区实质上对准于间隙壁的外侧边缘形成。栅间隙壁可具有多层结构,且可包含氧化硅、氮化硅、氮氧化硅或其他介电材料。具有n型掺杂质或p型掺杂质的掺杂源极及漏极区域及LDD区利用例如离子注入的一般掺杂方式形成。用以形成相关的掺杂区域的N型掺杂质可包括磷、砷和/或其他材料。P型掺杂质可包括硼、铟和/或其他材料。
接着形成多重内连线。多重内连线包括垂直的内连线,例如一般的介层窗(via)或接触窗(contact),并包括水平的内连线,例如金属线(metal lines)。可使用包括铜、钨及金属硅化物(silicide)的导电材料形成各种内连线元件。在一实施例中,利用镶嵌法(damascene)形成铜相关的多重内连线结构。在其他实施例中,利用钨于接触洞内形成钨插塞(plug)。
半导体结构可更包含额外的隔离元件以将每个元件互相隔离。隔离元件可包括不同的结构,并可利用不同的制造技术予以形成。举例而言,隔离元件可包括浅沟槽隔离(shallow trench isolation;STI)元件。STI的形成步骤可包括于基底内蚀刻出沟槽,以及以例如氧化硅、氮化硅或氮氧化硅的绝缘材料填充沟槽。所填充的沟槽可具有多层结构,例如具有热氧化衬层并以氮化硅填充沟槽。在一实施例中,STI结构可利用一连续的步骤形成,例如:成长垫氧化物(pad oxide)、以低压化学气相沉积法(LPCVD)形成氮化层、利用光致抗蚀剂及掩模图案化STI开口、于基底内蚀刻出沟槽、选择性的成长热氧化沟槽衬垫层(thermal oxide trench liner)以增进沟槽介面(trench interface)特性、以CVD法形成氧化物以填充沟槽、利用化学机械研磨法(chemicalmechanical planarization;CMP)进行回蚀刻步骤、及利用氮化物剥离法(nitridestripping)法留下STI结构。
半导体结构200仅为可利用方法100中的各种概念的元件中的其中一个例子。半导体结构200及其制造方法100可应用于其他具有high k及金属栅极元件的半导体元件,例如应变半导体基底(strained semiconductor substrate)、异半导体元件(hetero-semiconductor device)、或无应力绝缘结构(stress-freeisolation structure)。
本发明并非限于包括MOS晶体管的半导体结构的应用,而更可延伸至其他具有金属栅极堆叠的集成电路。举例而言,半导体结构200可包括动态随机存取存储器(dynamic random access memory;DRAM)单元、单电子晶体管(single electron transistor;SET)、和/或其他微电子元件(microelectronicdevice)(于此统称为微电子元件)。在其他实施例中,半导体结构200包括鳍式场效应晶体管(FinFET transistor)。当然,本发明的概念也可应用于可取得的其他类型的晶体管,包括单栅极晶体管(single-gate transistor)、双栅极晶体管(double-gate transistor)及其他多栅极晶体管(multiple-gate transistor),且可使用于不同的应用中,包括感测单元(sensor cell)、存储器单元(memorycell)、逻辑单元(logic cell)及其他的应用。
虽然本发明的实施例揭示如上,然其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可做些许更动与润饰。一实施例中,利用本发明的方法形成n型金属氧化半导体场效应晶体管(metal-oxide-semiconductor field-effect-transistor;NMOSFET)。在其他实施例中,于先形成栅极的方法(gate-first process)中利用本发明的方法形成金属栅极堆叠,其中以方法100形成金属栅极堆叠,且其保留于最终的结构中。在其他实施例中,于混成方法(hybrid process)中利用本发明的方法形成金属栅极堆叠,其中以方法100形成第一型金属栅极堆叠(例如NOMOS金属栅极堆叠),且其保留于最终的结构中。所形成的第二型金属栅极堆叠(例如POMOS金属栅极堆叠)视为虚置栅极结构(dummy gate structure),因此能进行源/漏极离子掺杂步骤及退火步骤。接着,移除部分的虚置栅极结构,并以适合的材料再填充(refill)虚置栅极沟槽(dummy gate trench)。举例而言,将PMOS区域内的多晶硅层及金属层移除后,以p金属再填充并更以例如铜的另一金属填充以形成PMOS金属栅极堆叠。
在其他实施例中,半导体基底可包括外延层。举例而言,基底可具有覆盖块半导体(bulk semiconductor)的外延层。再者,可对基底施予应力以增强性能。举例而言,外延层可包括相异于块半导体的半导体材料,例如,以锗化硅(silicon germanium)覆盖块硅(bulk silicon),或者是,硅层覆盖以包含选择性外延成长(SEG)的步骤所形成的块锗化硅(bulk silicon germanium)。再者,基底可包括例如埋藏介电层的绝缘层上覆半导体(semiconductor-on-insulator;SOI)结构。或者是,基底可包括例如埋藏氧化层(buried oxide;BOX)的埋藏介电层,其可通过被称为埋藏氧化层氧注入隔离(separation by implantation ofoxygen;SIMOX)的方法、晶片接合法(wafer bonding)、选择性外延成长法(selective epitaxial growth;SEG)或其他合适的方法所形成。
因此,本发明提供形成半导体元件的金属栅极堆叠的方法。本发明的方法包括在一蚀刻腔室内,通过一图案化掩模用以定义栅极区的开口对一半导体基底进行一第一干蚀刻步骤,以移除位于该半导体基底上的一多晶硅层及金属栅极层;于该蚀刻腔室内提供一水蒸汽至该半导体基底,以移除位于该半导体基底上的一盖层;以及于该蚀刻腔室内对该半导体基底进行一第二干蚀刻步骤,以移除一high k介电材料层。
所述方法还包括在进行该第二干蚀刻步骤后,对该半导体基底进行一湿蚀刻步骤以移除聚合残留物。在一实施例中,该盖层包括氧化镧(Lanthanumoxide;LaO)。该提供水蒸汽的步骤可提供水至该盖层,且蚀刻速率大于约30埃/每分钟(angstrom per minute)。在一实施例中,该半导体元件是一N型金属氧化半导体场效应晶体管(NMOSFET)。该金属栅极层可包括氮化钛(titanium nitride)。该金属栅极层可包括一择自由氮化钽(tantalum nitride)、氮化钼(molybdenum nitride)、及钛铝氮化物(titanium aluminum nitride)所构成的组的导电材料。该提供水蒸汽的步骤可包括提供该半导体基底于一高于约100℃的温度。该图案化硬掩模可包括氮化硅。
本发明也提供形成半导体元件的金属栅极堆叠的另一实施例。所述方法包括在一蚀刻腔室内,通过一图案化掩模用以定义栅极区的开口对一半导体基底进行一第一干蚀刻步骤,以移除位于该半导体基底上的一栅极金属层;于该蚀刻腔室内提供氧等离子体或氩等离子体中的至少一个至该半导体基底,以移除位一盖层;于该蚀刻腔室内对该半导体基底进行一第二干蚀刻步骤,以移除一high k介电材料层;以及对该半导体基底进行一湿蚀刻步骤以移除聚合残留物。
在上述方法的多个实施例中,该盖层可包括氧化镧。该金属栅极层可包括一择自由氮化钽、氮化钼、及钛铝氮化物所构成的组的导电材料。该第一干蚀刻步骤可包括进行该第一干蚀刻步骤以更移除位于该金属栅极层上的一多晶硅层。
本发明还提供形成半导体元件的另一实施例。上述方法包括在一蚀刻腔室内,对一半导体基底进行一第一干蚀刻步骤,以移除一金属栅极层;于该蚀刻腔室内提供水蒸汽、氧等离子体及氩等离子体中的至少一个至该半导体基底,以移除位一盖层;以及于该蚀刻腔室内对该半导体基底进行一第二干蚀刻步骤以移除一high k介电材料层,借此形成一金属栅极堆叠。
上述方法可还包括于进行该第一干蚀刻步骤前,图案化位于该金属栅极层上的一掩模层以定义一图案区域。上述方法可还包括在进行该第二干蚀刻步骤后,于一湿蚀刻装置内对该半导体基底进行一湿蚀刻步骤以移除聚合残余物。盖层可包括氧化镧。该第一干蚀刻步骤可包括对位于该金属栅极层上的一多晶硅层进行该第一干蚀刻步骤。在一实施例中,该金属栅极堆叠为NMOSFET的金属栅极结构。该金属栅极层可包括氮化钛。
虽然本发明已以较佳实施例揭示如上,然其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可做些许更动与润饰,因此本发明的保护范围当视所附的权利要求所界定的范围为准。
Claims (15)
1.一种形成半导体元件的金属栅极堆叠的方法,包括下列步骤:
于一蚀刻腔室内,通过一图案化掩模的定义栅极区的开口对一半导体基底进行一第一干蚀刻步骤,以移除位于该半导体基底上的一多晶硅层及一金属栅极层;
于该蚀刻腔室内提供一水蒸汽至该半导体基底,以移除位于该半导体基底上的一盖层;以及
于该蚀刻腔室内对该半导体基底进行一第二干蚀刻步骤,以移除一高介电常数介电材料层。
2.如权利要求1所述的形成半导体元件的金属栅极堆叠的方法,还包括于进行该第二干蚀刻步骤后,对该半导体基底进行一湿蚀刻步骤以移除一聚合残余物。
3.如权利要求1所述的形成半导体元件的金属栅极堆叠的方法,其中该盖层包括氧化镧。
4.如权利要求1所述的形成半导体元件的金属栅极堆叠的方法,其中该提供水蒸汽的步骤包括提供水至该盖层,且具有大于30埃/每分钟的蚀刻速率。
5.如权利要求1所述的形成半导体元件的金属栅极堆叠的方法,其中该金属栅极层包括氮化钛。
6.如权利要求1所述的形成半导体元件的金属栅极堆叠的方法,其中该金属栅极层包括一择自由氮化钽、氮化钼、及钛铝氮化物所构成的组的导电材料。
7.一种形成半导体元件的金属栅极堆叠的方法,包括下列步骤:
于一蚀刻腔室内,通过一图案化掩模的定义栅极区的开口对一半导体基底进行一第一干蚀刻步骤,以移除位于该半导体基底上的一栅极金属层;
于该蚀刻腔室内提供一氧等离子体及氩等离子体中的至少一个至该半导体基底,以移除一盖层;
于该蚀刻腔室内对该半导体基底进行一第二干蚀刻步骤,以移除一高介电常数介电材料层;以及
对该半导体基底进行一湿蚀刻步骤以移除一聚合残余物。
8.如权利要求7所述的形成半导体元件的金属栅极堆叠的方法,其中该盖层包括氧化镧。
9.如权利要求7所述的形成半导体元件的金属栅极堆叠的方法,其中该栅极金属层包括一择自由氮化钛、氮化钽、氮化钼、及钛铝氮化物所构成的组的导电材料。
10.如权利要求7所述的形成半导体元件的金属栅极堆叠的方法,其中该第一干蚀刻步骤包括进行该第一干蚀刻步骤以更移除位于该栅极金属层上的一多晶硅层。
11.一种形成半导体元件的方法,包括下列步骤:
于一蚀刻腔室内对一半导体基底进行一第一干蚀刻步骤以移除一金属栅极层;
于该蚀刻腔室内提供一水蒸汽、氧等离子体、及氩等离子体中的至少一个至该半导体基底以移除一盖层;以及
于该蚀刻腔室内对该半导体基底进行一第二干蚀刻步骤以移除一高介电常数介电材料层,借此形成一栅极堆叠。
12.如权利要求11所述的形成半导体元件的方法,还包括于该第二干蚀刻步骤后,于一湿蚀刻装置中对该半导体基底进行一湿蚀刻步骤,以移除一聚合残余物。
13.如权利要求11所述的形成半导体元件的方法,其中该盖层包括氧化镧。
14.如权利要求11所述的形成半导体元件的方法,其中该第一干蚀刻步骤包括对位于该金属栅极层上的一多晶硅层进行该第一干蚀刻步骤。
15.如权利要求11所述的形成半导体元件的方法,其中该金属栅极层包括氮化钛。
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