CN101527278A - 通孔制程、半导体元件及形成晶片堆栈的方法 - Google Patents
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Abstract
本发明揭示一种通孔制程、半导体元件及形成晶片堆栈的方法，通孔制程包括以下步骤：提供一半导体基底，包括：一集成电路元件，设于该半导体基底上；一内层介电层，设于该半导体基底上且覆盖该集成电路元件，及一接触插塞，设于该内层介电层中且电性连接该集成电路元件；形成至少一个通孔，该通孔穿过该内层介电层及一部分的该半导体基底；沉积一导电材料层于该内层介电层上并填入该通孔；去除该通孔以外的导电材料层并露出该接触插塞的顶部，其中残留于该通孔的导电材料层形成一通孔插塞；及形成一内连线结构，包括多个金属层，多个金属层形成于多个金属间介电层中，其中该内连线结构的最下层金属层电性连接至该接触插塞露出的部分与该通孔插塞。
Description
技术领域
本发明涉及集成电路(IC)的堆栈，且特别涉及一种应用于晶片(晶圆)级堆栈技术的通孔制程(through via process)、半导体元件及形成晶片堆栈的方法。
背景技术
三度空间(3D)晶片-晶片垂直堆栈技术是通过垂直连通一芯片中堆栈的多层有源IC元件，例如处理器、可编程元件、存储元件等，以减少线路的平均长度，具有降低内连线的阻容延迟(RC delay)与增加系统效能的优点。在单一晶片或晶片-晶片垂直堆栈中形成3D内连线的主要挑战在于通孔的制作，此通孔为晶片提供从一侧至另一侧的高阻抗信号的信号路径。硅通孔(Through Silicon Via；TSV)通常是在通孔中填满导电材料以接触并连接其它的硅通孔或接合层的导体。美国专利第6642081号与第6897125号揭示了在第一金属内连线制程后形成硅通孔的方法。由于蚀刻与设计上的限制，硅通孔的密度通常较小，因而造成连接、接触、与可靠度上潜在的问题。目前的硅通孔技术所面临的另一问题在于散热，而如果设计硅通孔用于散热，这些硅通孔通常会占去一般设计中接点与金属层的区域。“Three-DimensionalIntegrated Circuits and the Future of System-on-Chip Designs，by Robert S.Patti，Proceeding of the IEEE，pp.1214-1224，Vol.94，No.6，June 2006”揭示了一种在接触制程前形成填钨硅通孔(tungsten-filled TSVs)的超接触制程(super-contactprocess)。此超接触制程可能会因为填钨硅通孔的应力而影响到后续接触制程中微影与沉积的准确度。
发明内容
本发明的目的在于提供一种通孔制程，该通孔制程于接触制程之后、第一层内连线制程之前进行。该通孔制程可避免影响接触制程的微影、蚀刻、与沉积步骤的准确度，本发明还提供一种半导体元件，及形成晶片堆栈的方法。
本发明提供一种通孔制程，包括以下步骤：提供一半导体基底，其包括：一集成电路元件，其设于该半导体基底上，一内层介电层，其设于该半导体基底上且覆盖该集成电路元件，以及一接触插塞，其设于该内层介电层中且电性连接该集成电路元件；形成至少一个通孔穿过该内层介电层以及一部分的该半导体基底；沉积一导电材料层于该内层介电层上并填入该通孔；去除该通孔以外的导电材料层并露出该接触插塞的顶部，其中残留于该通孔的导电材料层形成一通孔插塞；以及，形成一内连线结构，其包括多个金属层，所述多个金属层形成于多个金属间介电层中，其中该内连线结构的最下层金属层电性连接至该接触插塞露出的部分与该通孔插塞。
本发明亦提供一种半导体元件，一半导体基底，包括一集成电路元件；一内层介电层，设于该半导体基底上；一接触插塞，设于该内层介电层中且电性连接该集成电路元件；一通孔插塞，穿过该内层介电层以及一部分的该半导体基底，其中该内层介电层、该通孔插塞、及该接触插塞的顶部表面齐平；以及，一内连线结构，包括多个金属层，所述多个金属层形成于多个金属间介电层中，其中该内连线结构的最下层金属层电性连接至该接触插塞与该通孔插塞。
本发明还提供一种形成晶片堆栈的方法，其包括以下步骤：提供一第一晶片，其包括：一第一半导体基底，一第一集成电路元件，该第一集成电路元件设于该第一半导体基底上，及一内层介电层，该内层介电层设于该第一半导体基底上且覆盖该第一集成电路元件；于该内层介电层中依序形成一接触插塞与一通孔插塞，其中该接触插塞电性连接该第一集成电路元件，且该通孔插塞穿过一部分的该第一半导体基底；形成一内连线结构于该内层介电层上，其中该内连线结构分别电性连接至该接触插塞与该通孔插塞；提供一第二晶片；以及，接合该第一晶片与该第二晶片以形成一晶片堆栈。
本发明的有益技术效果在于，相较于现有的通孔制程，本发明实施例的通孔制程可避免影响接触制程的微影、蚀刻、与沉积步骤的准确度，其优点包括：低电阻通孔、高通孔密度、对于排除区域(keep-out zone)的最小需求、内连线路安排的高自由度、以及高合格率等。
为让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下。
附图说明
图1～图10为一系列剖面示意图，用以说明一实施例中半导体装置各阶段的集成电路制程。
其中，附图标记说明如下：
10～半导体基底 12～内层介电层
14～接触插塞 16～图案化光阻层
18～通孔 20～保护层
22～导电材料层 22a～通孔插塞
26～第一层内连线层 28～接合接点
30～绝缘层 40～基底
42～绝缘层 24、44～IMD层
46～接合垫 100、300～晶片
200～IC元件
具体实施方式
本发明的较佳实施例提供一种通孔制程，此通孔制程在一接触制程之后、第一层内连线制程之前进行。在本发明的叙述中，“通孔”一词代表一填充有金属的导孔，其至少穿过部分的半导体基底。当填充有金属的导孔是至少穿过部分含硅的半导体基底时，本发明的通孔制程又可称为“硅通孔制程”。“第一层内连线”一词代表一最下层金属层，其位于接触结构与晶体管上的最下层金属间介电层(Inter-Metal Dielectric；IMD)中。
以下将配合附图详述本发明的实施例，其中同样或类似的元件将尽可能以相同的附图标记表示。在附图中可能夸大实施例的形状与厚度以便清楚表现出本发明的特征。在下文中将特别描述构成本发明装置的元件或与之直接相关的元件。应特别注意的是，未特别显示或描述的元件可以该技术人员所熟知的各种形式存在。此外，当某一层被描述为在另一层(或基底)“上”时，其可代表该层与另一层(或基底)为直接接触，或两者之间另有其它层存在。
图1～图10为一系列剖面示意图，用以说明一实施例中半导体装置各阶段的集成电路制程。请参照图1，其显示晶片100的剖面，包含半导体基底10、IC元件200、覆于基底10上的内层介电层(Inter-Layer Dielectric；ILD)12、以及一接触插塞14，该接触插塞14设于ILD层12中且电性连接至IC元件200。基底10通常为硅，例如：具有磊晶层或无磊晶层的硅基底，或是具有绝缘埋层的绝缘层上覆硅(Silicon-On-insulator；SOI)基底。此外，基底10也可为GaAs基底、GaAsP基底、InP基底、GaAlAs基底、InGaP基底。IC元件200可包含多个独立的电路元件，例如晶体管、二极管、电阻、电容、电感、或是其它以现有半导体制程所形成的有源与无源半导体装置。
ILD层12形成于基底10上，用以隔离IC元件200与后续所形成的内连线结构。ILD层12可为一单层或多层结构。ILD层12可为掺杂或未掺杂的氧化硅层，由热化学气相沉积法或高密度电浆制程所形成，例如：未掺杂硅玻璃、磷掺杂硅玻璃、或硼磷硅玻璃。此外，ILD层12亦可为掺杂或磷掺杂旋涂式玻璃(SOG)、磷掺杂四乙氧基硅酸盐(PTEOS)、或硼磷掺杂四乙氧基硅酸盐(BPTEOS)。以干蚀刻在ILD层12中形成一接触窗，并在接触窗中填入导电材料后即可形成接触插塞14。接触插塞14的材质可为钨、钨合金、铜、或铜合金。
请参照第图2～图4，以例如化学机械研磨法(CMP)将ILD层12平坦化后，形成一图案化光阻层16。以干蚀刻制程形成至少一个通孔18，该通孔18穿过ILD层12且至少延伸进入基底10一预定深度。之后，去除光阻层16。
请参照图5，在晶片100上形成一保护层20，该保护层20顺应性覆盖通孔18的底部与侧壁，以避免任何导电材料进入晶片100的电路的有源区域。保护层20的材质可为氧化硅、氮化硅、或前述的组合等。之后，如图6所示，在保护层20上沉积一导电材料层22并填入通孔18中。导电材料层22可包含一扩散阻障层与一金属层。例如，可将一扩散阻障层顺应性地沉积在通孔18的底部与侧壁，然后再进行金属填充制程，如此可得到良好的导电性并兼具扩散阻障效果。扩散阻障层可包含一耐火材料，包括(但不限于)：TiN、TaN、Ta、Ti、TiSN、W、WN、Cr、Nb、Co、Ni、Pt、Ru、Pd、Au、CoP、CoWP、NiP、NiWP、前述的组合、或其它可抑制铜扩散入ILD层12的材质，其可由物理气相沉积法、化学气相沉积法、原子层沉积法、或电镀法所形成。金属层的材质可包含一低电阻导电材料，包括(但不限于)：铜、铜合金。举例而言，填充铜的制程可包括一金属晶种层的沉积与一铜化学电镀制程。此外，金属层亦可包含其它各种金属，例如钨、铝、金、银等。
请参照图7，以化学机械研磨法或蚀刻方式去除通孔18以外多余的导电材料层22与保护层20，形成通孔插塞22a。通孔插塞22a穿过ILD层12并延伸进入部分基底10。
接着，在晶片100上进行后段(BEOL；back-end-of-line)内连线制程，以形成包含多个内连线层与金属间介电层(IMD)的内连线结构。请参照图8，在IMD层24中形成第一层内连线层26，以电性连接接触插塞14与通孔插塞22a。之后，在第一层内连线层26上制作其它的内连线层与IMD层，为简化附图，在图中并未绘出这些内连线层与IMD层。本发明的实施例使用含铜导电材料来形成内连线层。此处所称的“含铜材料”包含实质上纯的元素铜，含有不可避免的杂质的铜，以及包含少量其它元素的铜合金，例如：Ta、In、Sn、Zn、Mg、Cr、Ti、Ge、Sr、Pt、Mg、Al、Zr等。可使用标准的镶嵌制程来制作铜内连线。虽然此处的实施例是以铜内连线为例进行说明，但本发明亦不排除使用铜以外的金属材料来形成后段内连线。
请参照图9，在绝缘层30中形成接合接点(bonding contacts)28，其中绝缘层30位于一最上层内连线层与最上层IMD层(未显示)之上。绝缘层30可部分去除或蚀刻，使接合接点28稍微突出绝缘层30的上表面。接合接点28可由含铜导电材料所形成。绝缘层30可隔绝IC元件200与其它接合至晶片100的晶片上的任何电路或元件。
请参照图10，其示出了晶片100堆栈并接合至另一晶片300的剖面示意图。晶片300包含一基底40、一绝缘层42、一IMD层44、以及接合垫(bondingpads)46。晶片100与晶片300通过接合接点28与接合垫46互相接合而形成三度空间的堆栈晶片。应注意的是，在晶片100与晶片300中可整合任何数量的其它装置、元件、连接元件等。本发明实施例中所提到或未提到的特定装置并非用以限定本发明的范围。
相较于现有的通孔制程，本发明实施例的通孔制程可避免影响接触制程的微影、蚀刻、与沉积步骤的准确度，其优点包括：低电阻通孔、高通孔密度、对于排除区域(keep-out zone)的最小需求、内连线路安排的高自由度、以及高合格率等。
虽然本发明已以多个较佳实施例披露如上，然而其并非用以限定本发明，任何所属技术领域中具有通常知识的人员，在不脱离本发明的精神和范围内，可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求书所界定的范围为准。
Claims (10)
1.一种通孔制程，包括以下步骤：
提供一半导体基底，其包括：一集成电路元件，其设于该半导体基底上；一内层介电层，其设于该半导体基底上且覆盖该集成电路元件，以及一接触插塞，其设于该内层介电层中且电性连接该集成电路元件；
形成至少一个通孔，该通孔穿过该内层介电层以及一部分的该半导体基底；
沉积一导电材料层于该内层介电层上并填入该通孔；
去除该通孔以外的导电材料层并露出该接触插塞的顶部，其中残留于该通孔的导电材料层形成一通孔插塞；以及
形成一内连线结构，其包括多个金属层，所述多个金属层形成于多个金属间介电层中，其中该内连线结构的最下层金属层电性连接至该接触插塞露出的部分与该通孔插塞。
2.如权利要求1所述的通孔制程，其中该导电材料层包含铜或铜合金，该接触插塞包含钨或钨合金。
3.如权利要求1所述的通孔制程，其中在沉积该导电材料层之前还包括：形成一保护层，该保护层顺应性地覆盖该通孔的底部与侧壁。
4.一种半导体元件，包括：
一半导体基底，包括一集成电路元件；
一内层介电层，设于该半导体基底上；
一接触插塞，设于该内层介电层中且电性连接该集成电路元件；
一通孔插塞，穿过该内层介电层以及一部分的该半导体基底，其中该内层介电层、该通孔插塞、及该接触插塞的顶部表面齐平；以及
一内连线结构，包括多个金属层，所述多个金属层形成于多个金属间介电层中，其中该内连线结构的最下层金属层电性连接至该接触插塞与该通孔插塞。
5.如权利要求4所述的半导体元件，其中该通孔插塞包含铜或铜合金，其中该接触插塞包含钨或钨合金。
6.如权利要求4所述的半导体元件，其中该半导体元件还包括一保护层，该保护层顺应性贴覆于该通孔插塞的底部与侧壁。
7.一种形成晶片堆栈的方法，包括以下步骤：
提供一第一晶片，其包括：一第一半导体基底；一第一集成电路元件，该第一集成电路元件设于该第一半导体基底上；及一内层介电层，该内层介电层设在该第一半导体基底上且覆盖该第一集成电路元件；
依序形成一接触插塞与一通孔插塞于该内层介电层中，其中该接触插塞电性连接该第一集成电路元件，且该通孔插塞穿过一部分的该第一半导体基底；
形成一内连线结构于该内层介电层上，其中该内连线结构分别电性连接至该接触插塞与该通孔插塞；
提供一第二晶片；以及
接合该第一晶片与该第二晶片以形成一晶片堆栈。
8.如权利要求7所述的方法，其中该通孔插塞包含铜或铜合金。
9.如权利要求7所述的方法，其中该接触插塞包含钨或钨合金。
10.如权利要求7所述的方法，其中该方法还包括将一保护层顺应性贴覆于该通孔插塞的底部与侧壁。
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| CN111261604B (zh) * | 2018-11-30 | 2022-09-16 | 南亚科技股份有限公司 | 半导体元件及其制造方法 |
| CN111987071A (zh) * | 2019-05-24 | 2020-11-24 | 南亚科技股份有限公司 | 在导电插塞上具有导电顶盖层的半导体元件及其制备方法 |
| US11778812B2 (en) | 2019-05-24 | 2023-10-03 | Nanya Technology Corporation | Method for forming a semiconductor device with conductive cap layer over conductive plug |
| CN112086399A (zh) * | 2019-06-13 | 2020-12-15 | 芯恩（青岛）集成电路有限公司 | 半导体结构及制备方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20130277844A1 (en) | 2013-10-24 |
| US20090224405A1 (en) | 2009-09-10 |
| CN101527278B (zh) | 2011-06-01 |
| US8486823B2 (en) | 2013-07-16 |
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