CN101490830A - 发射机应答器以及制造发射机应答器的方法 - Google Patents

发射机应答器以及制造发射机应答器的方法 Download PDF

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Publication number
CN101490830A
CN101490830A CNA2007800261457A CN200780026145A CN101490830A CN 101490830 A CN101490830 A CN 101490830A CN A2007800261457 A CNA2007800261457 A CN A2007800261457A CN 200780026145 A CN200780026145 A CN 200780026145A CN 101490830 A CN101490830 A CN 101490830A
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integrated circuit
projection
patterned mask
photoresist layer
substrate
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CN101490830B (zh
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赖因哈德·罗吉
克里斯蒂安·岑茨
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Abstract

在一种制造发射机应答器(1)的方法中制造一种集成电路(2，72，82)。该集成电路(2，72，82)是通过以下方式制造的：将光致抗蚀剂层(11)涂敷在半导体器件(4)的表面(8)上，通过用平版印刷方式使所述光致抗蚀剂层(11)形成图案以使所述光致抗蚀剂层(11)包含至少一个孔(12，13)从而来生成带图案的掩模(14)，以及通过利用所述带图案的掩模(14)将凸块(15，16，75，76)沉积在所述表面(8)上来用凸块(15，16，75，76)填充所述孔(12，13)。最后将具有带图案的掩模(14)的集成电路(2，72，82)附接到包括天线结构(18)的衬底(3)。所述凸块(15，16，75，76)电连接到所述天线结构(18)。

Description

发射机应答器以及制造发射机应答器的方法
技术领域
本发明涉及一种发射机应答器(transponder)以及一种制造发射机应答器的方法。
背景技术
发射机应答器或标签包括集成电路和天线。集成电路被设计为处理用天线捕捉到的信号，并且响应于所捕捉到的信号，产生将通过天线发射出去的应答信号。天线通常由衬底支撑，而通过所谓的倒装片固定工艺将集成电路附接到衬底。
已知的集成电路包括与衬底相对的表面处的触点。这些触点包括连接至凸块的连接焊盘，这些凸块被电连接至天线。当制造发射机应答器时，例如通过利用涂在衬底上的粘结层来将集成电路附接至衬底。随后将集成电路压在具有粘结层的衬底上，其中包括凸块的电路表面面向衬底。由于压力的原因，尤其是凸块和集成电路凸块的周围区域以及凸块压向衬底的区域周围的天线结构会受到严重的应力，这会引起凸块和凸块周围的天线的变形。由于变形的凸块，使得天线与集成电路间的距离会有不同，这导致天线和集成电路的导电层间不同的杂散电容。尤其是当被用作RFID(射频识别)或UHF(超高频)标签时，这些不同的杂散电容会损害发射机应答器的性能。
已公开的美国专利申请2003/0017414 A1公开了一种制造具有焊料凸块、集成底部填充以及单独焊剂涂覆的倒装片的方法。最初，对在其表面上具有连接焊盘且其表面上涂覆有底部填充材料的半导体器件进行处理，以便底部填充材料形成精确地位于连接焊盘上的孔。底部填充材料的主要成分是热塑树脂。因为光烧蚀(photoablation)工艺只需要少量加热，所以采用光烧蚀工艺制成这些孔。然后，用焊料材料填充这些孔以形成电连接至焊盘的焊料凸块。焊料凸块在底部填充材料上略有延伸。
当通过将倒装片压向衬底并加热焊料凸块来将倒装片固定在衬底上时，那么，底部填充的热塑树脂软化甚至融化，从而很容易变形，其会导致不同倒装片的表面与其衬底间的距离不同。这导致了在衬底的导电层和倒装片的导电层之间不同的杂散电容，从而可能导致发射机应答器的故障。
发明内容
本发明的一个目的是提供一种制造发射机应答器的方法，所述发射机应答器包括附接到具有天线结构的衬底上的集成电路，该方法使得发射机应答器的预定杂散电容处在一个相对较小的容差内，其中的杂散电容是由集成电路的导电层和天线结构引起的。
本发明的另一个目的是提供一种发射机应答器，其包括附接到具有天线结构的衬底上的集成电路，该发射机应答器具有处在一个相对较小的容差内的预定杂散电容，其中的杂散电容是由集成电路的导电层和天线结构引起的。
按照本发明通过制造发射机应答器的方法来实现上述目的，所述制造发射机应答器的方法包括以下步骤：
通过以下方式制造集成电路：将光致抗蚀剂层涂敷在半导体器件的表面上，通过用平版印刷方式对所述光致抗蚀剂层形成图案以使所述光致抗蚀剂层包含至少一个孔从而来生成带图案的掩模，以及通过利用所述带图案的掩模将凸块沉积在所述表面上来用凸块填充所述孔；和
将具有所述带图案的掩模的集成电路附接到包括天线结构的衬底，以使所述凸块电连接到所述天线结构。
该发射机应答器包括集成电路和衬底。衬底例如是塑料薄膜，并包含天线结构，该天线结构例如是导电环、单极天线或偶极天线。集成电路还包括带图案的掩模，带图案的掩模是由光致抗蚀剂制成并用作沉积在表面上的至少一个凸块的掩模。
通过先在半导体器件的表面上涂覆光致抗蚀剂层来制造本发明的集成电路。特别地，半导体器件是裸片。从而，采用一个晶片，在将凸块沉积在表面上之后，从晶片分离出每个均包括一个裸片的单个的集成电路，从而可以制造多个集成电路。
光致抗蚀剂层被用作针对利用沉积工艺而沉积在表面上的凸块的带图案的掩模。与焊料凸块相反，由沉积工艺形成的凸块相对容易制造。另外，沉积的凸块具有相对高的电导率，特别是在根据本发明方法的实施例的情况下所沉积的凸块是金质凸块时。
随后将集成电路附接到衬底上。集成电路还包括由光致抗蚀剂材料通过利用光致抗蚀剂层而制成的带图案的掩模。光致抗蚀剂层的优点格外表现在其可被制成为在相对较小的容差内具有预定的厚度。光致抗蚀剂层的另一个优点是，与热塑树脂层相比，尤其是在使用了负抗蚀剂的情况下，光致抗蚀剂层为交叉连接并能够相对较硬。因此所述层在尤其可能包括将集成电路压力接合到衬底上的附接步骤中不太可能变形。结果，由光致抗蚀剂材料制成的带图案的掩模可被制造得具有预定层厚度，该厚度在将集成电路附接到衬底的步骤过程中不会改变。因此，可以实现的是：根据本发明的方法制成的多个发射机应答器在它们的衬底和各个集成电路的半导体器件的表面之间具有实质相同的距离，即处在相对较小的容差内的距离。从而这些发射机应答器具有在一个相对较小的容差范围内的相同的杂散电容，这导致了例如所得发射机应答器的改进了的调谐。
另外，带图案的掩模至少可以部分地作为衬底和集成电路之间的底部填充，至少部分地吸收特别是塑料衬底会面临的热机械应力。而且，在压力接合过程中，不只是凸块受到产生的压力的影响，压力还散布到带图案的掩模上。这对天线结构会产生较小的应力。
表面可以包括至少一个连接焊盘。随后孔可以与连接焊盘匹配或者还可以相对于连接焊盘偏移。为了改善凸块的沉积，还可以用焊瘤(flash)(特别是金质焊瘤)覆盖连接焊盘。如果孔相对于连接焊盘偏移，那么，诸如焊瘤之类的导电结构可以在半导体器件的表面上延伸，以便它位于孔的下面。这样，在焊瘤上沉积凸块，并因此通过焊瘤将凸块连接至连接焊盘。
光致抗蚀剂层可以是多部件层，具有将集成电路附接到衬底的粘合特性。这种多部件层的一个示例是包括紫外线引发剂和热引发剂的基于丙烯酸的光致抗蚀剂。从而，可以采用通过UV辐射在光致抗蚀剂层中生成孔的平版印刷工艺来处理这种多部件层，并对这种多部件层进行部分交叉连接。在最后的装配工艺中，对该层进行热活化、完全固化并进行交叉连接至衬底。在这种情况下，在带图案的掩模与衬底之间不需要其他的粘合剂层。
在附接步骤中将凸块电连接到天线结构。为了保证良好的连接，凸块可以少量地延伸到带图案的掩模上。由于被置于半导体器件的表面上的带图案的掩模的原因，只有延伸到带图案的掩模上的部分在附接步骤中会变形。假设凸块从半导体器件的表面上延伸了20μm并且在将集成电路附接到衬底上时没有使用带图案的掩模，则半导体器件的表面与衬底间由于附接步骤过程中的变形所导致的距离内5％的容差导致了相应杂散电容5％的容差。根据本发明的方法，由于光致抗蚀剂制成的带图案的掩模被置于集成电路上，因此只有在带图案的掩模上延伸的凸块部分会在附接步骤过程中变形。假设凸块在带图案的掩模(厚度为20μm)上延伸的5μm，则在带图案的掩模上延伸的凸块部分的5％的变形部分将导致所得杂散电容小于1％的变化。
除了在带图案的掩模上延伸以外，凸块还与带图案的掩模重叠。这使得凸块与天线结构间的电连接得以改善。
还可以根据本发明通过发射机应答器来实现发明目的，所述发射机应答器包括：
集成电路，其包括半导体器件，该半导体器件包括表面、由涂敷在所述表面上的光致抗蚀剂层制成的带图案的掩模，其中光致抗蚀剂层包括用凸块填充的至少一个孔；以及
具有天线结构的衬底，将具有所述带图案的掩模的集成电路附接到所述衬底，其中所述凸块电连接到所述天线结构。
凸块可以是金质凸块，可以在带图案的掩模上延伸少量距离和/或重叠带图案的掩模。
表面可包括连接焊盘。孔可与连接焊盘匹配或相对于连接焊盘偏移。
光致抗蚀剂层可以是具有粘结特性从而将所述集成电路附接到衬底和/或具有预定厚度的多部件层。
附图说明
下面将通过非限制性示例的方式参考附图所示实施例来详细描述本发明。
图1到图5示出了本发明示例实施例中对包括集成电路的发射机应答器进行制造的步骤；
图6是示出图1到图5的发射机应答器的制造过程的流程图；以及
图7和图8是用于图5的发射机应答器的集成电路的可选实施例。
具体实施方式
图1到图5示出了本发明示例实施例中对包括集成电路的发射机应答器进行制造的步骤。最终的发射机应答器1在图5中表示，其包括集成电路2和具有天线18的衬底3。图6是示出发射机应答器1的制造过程的相关流程图。
为了制造发射机应答器1，例如，采用通常已知技术在晶片上制造如图1所示的半导体器件4。对于示范性实施例，半导体器件4包括用于处理发射机应答器1接收到的信号并用于对接收到的信号进行应答的电路，还包括连接焊盘5、6以及钝化层7。提供了连接至发射机应答器1的天线18的连接焊盘5、6。钝化层7是密封层，防止电路的电性能由于化学反应、腐蚀或包装过程中的处理而降低。对于示范性实施例而言，钝化层7的材料是二氧化硅，形成了半导体器件4的表面8。通过钝化层7的孔9、10可以连接到连接焊盘5、6。
对于示范性实施例而言，半导体器件4还包括焊瘤19，将焊瘤19施加在连接焊盘5、6上作为下述凸块处理的种子层。对于示范性实施例，焊瘤19由金制成，覆盖了孔9、10的侧壁，而且和钝化层7有轻微的重叠。可以通过标准平版印刷工艺或者还可以用烧蚀工艺构成焊瘤19。在不采用无电凸块工艺时，通过导线可以连接焊瘤19，随后在采用锯切、蚀刻或其他合适的工艺将晶片切成小片的切割过程中分离这些导线。
之后，如图2所示，在钝化层7的表面8上沉积光致抗蚀剂层11。对于示范性实施例，光致抗蚀剂层11是利用旋涂工艺沉积在表面8上的，具有18μm的厚度。旋涂是一种使光致抗蚀剂旋涂在晶片上(特别是在表面8上)以产生光致抗蚀剂层11的技术。光致抗蚀剂层11具有背向半导体器件4的表面17。
对于示范性实施例，光致抗蚀剂层11由包括紫外线引发剂和热引发剂的基于丙烯酸的材料制成。该材料不仅允许在使用平版印刷工艺进行的形成图案步骤中使光致抗蚀剂层11形成图案，而且在组装过程中进行加热时还具有粘合特性。
在光致抗蚀剂层11硬化之后，使用平版印刷来使光致抗蚀剂层11形成图案。平版印刷是一种图案转印工艺。当利用了光时，则该工艺被称为“光刻平版印刷”。当图案小到用微米来测量时，那么该工艺被称为“微平版印刷”。
由于图案成形工艺，如图3所示，在光致抗蚀剂层11中形成了匹配并暴露连接焊盘5、6的孔12、13。包括孔12、13的光致抗蚀剂层11形成了带图案的掩模14，而且还使表面17背向半导体器件4，并被用于下一个制造步骤。
如图4所示，下一个制造步骤是在孔12、13中沉积凸块15、16(对于示范性实施例而言，凸块15、16是金质凸块)，以通过公知的沉积工艺形成集成电路2。对于示范性实施例，凸块15、16在带图案的掩模14的表面17上延伸少量距离D。对于示范性实施例，该距离D是5μm。在继续制造发射机应答器1之前，切割晶片以获得针对示范性实施例的单个集成电路2。
之后，如图5所示，集成电路2被压向衬底3。衬底3包括天线18，对于示范性实施例而言，天线18的结构被印刷(例如通过使用导电墨水)在衬底3上。然而也可以使用蚀刻、电镀等方式来制成天线18。
光致抗蚀剂层11或带图案的掩模14的表面17也是集成电路2的表面。包括带图案的掩模14的集成电路2将其表面17压向衬底3，尤其是压向衬底3印刷有天线18的一侧。另外，当进行按压时将集成电路2置于衬底3上以便凸块15、16电连接到天线18的结构上。由于凸块15、16的突出部分以及衬底3上导电结构的氧化层可能裂开，从而进一步降低凸块15、16与衬底3上的导电结构之间的转移电阻。在本文中应当注意本发明的原理也适用于凸块15、16与天线18之间的电容耦合，尽管压力以及由此产生的应力比起将集成电路2附接到衬底3时针对电连接的压力和应力通常要低。对于示例实施例，光致抗蚀剂层11和带图案的掩模14的材料是由包括紫外线引发剂和热引发剂的基于丙烯酸制成的。因此带图案的掩模14只被预固化并可在装配过程中通过热反应来完全固化，从而可将集成电路2附接到衬底3，而无需额外的粘合层。
图6示出了获得本发明的发射机应答器1的步骤。第一步，将光致抗蚀剂层11涂覆到半导体器件4的表面8上。第二步，通过平版印刷工艺产生带图案的掩模14。第三步，将凸块15、16沉积在半导体器件4的连接焊盘5、6上。最后，将半导体器件4附接到衬底3上。
图7示出了可替换实施例集成电路72，该集成电路代替集成电路2用于发射机应答器1。如果没有明确指明，则用相同的参考标记表示集成电路72与集成电路2相对应的组件。
集成电路2与72之间主要的不同在于凸块，其在集成电路72中用参考标记75、76表示。不只是在带图案掩模14的表面17上延伸很小的距离D，凸块75、76还与带图案掩模14的表面17少量重叠。由于凸块75、76增加的面积，所以在装配过程中它们很少变形。因此，可以进一步减小杂散电容的容差。
图8示出了可替换实施例集成电路82，该集成电路代替集成电路2用于发射机应答器1。如果没有明确指明，则用相同的参考标记表示集成电路82与集成电路2相对应的组件。
集成电路2与82之间主要的不同在于集成电路82的凸块15、16相对于连接焊盘5、6偏移。因此，焊瘤19在表面8上延伸到孔12、13从而可将凸块15、16沉积在焊瘤19上。该措施的一个原因是将应力更高的区域从凸块15、16重新布置到集成电路82的边缘区域。由此，在凸块15、16正下方会被损坏的半导体器件4的结构在装配过程中很少受到应力并因此在装配过程之后很少出现故障。另一个原因是可以增大凸块15、16之间的距离，因为在将集成电路82附接到采用并不太先进的技术制成的衬底3时，也就是说衬底3是用并不能允许非常精细的结构的工艺制成的时，芯片变得越来越小会引起麻烦。
最后，应当理解的是，上述实施例是对本发明的说明而不是对本发明的限制，在不脱离所附权利要求所限定的本发明的范围时，本领域技术人员可以设计出很多可替换实施例。在权力要求中，放置在括号中的任何参考标号不应当被解释为对本发明的限制。所用词“包含”、“包括”等并不排除在作为整体的任一权利要求或说明书中没有列出的元件或步骤的存在。元素的单数不排除多个这种元素的复数，反之亦然。在列举了多个装置的装置权利要求中，可以用硬件的一个和相同的硬件项来实现这些装置中的几个。事实是在互相不同的从属权利要求中引用的某些措施并不表示不能结合这些措施来获得优势。

Claims (12)

1.一种制造发射机应答器(1)的方法，包括步骤：
a)通过以下方式制造集成电路(2，72，82)：
将光致抗蚀剂层(11)涂敷在半导体器件(4)的表面(8)上，
通过用平版印刷方式使所述光致抗蚀剂层(11)形成图案以使所述光致抗蚀剂层(11)包含至少一个孔(12，13)，从而生成带图案的掩模(14)，以及
通过利用所述带图案的掩模(14)将凸块(15，16，75，76)沉积在所述表面(8)上来用所述凸块(15，16，75，76)填充所述孔(12，13)；和
b)将具有所述带图案的掩模(14)的所述集成电路(2，72，82)附接到包括天线结构(18)的衬底(3)，以使所述凸块(15，16，75，76)电连接到所述天线结构(18)。
2.根据权利要求1所述的方法，包括在所述表面上沉积金质凸块(15，16，74，75)的步骤。
3.根据权利要求1所述的方法，其中所述表面(8)包括连接焊盘(5，6)，并且所述孔(12，13)与所述连接焊盘(5，6)匹配或相对于所述连接焊盘(5，6)偏移。
4.根据权利要求1所述的方法，包括涂敷具有预定厚度(d)的所述光致抗蚀剂层(11)的步骤。
5.根据权利要求1所述的方法，包括步骤：在将所述集成电路(2，72，82)附接到所述衬底(3)上时将所述集成电路(2，72，82)压在所述衬底(3)上。
6.根据权利要求1所述的方法，其中所述光致抗蚀剂层(11)是具有粘结特性以便将所述集成电路(2，72，82)连接到所述衬底(3)的多部件层。
7.根据权利要求1所述的方法，其中所述凸块(15，16，75，76)在所述带图案的掩模(14)上延伸少量距离(D)并且/或者与所述带图案的掩模(14)重叠。
8.一种发射机应答器，包括：
集成电路(2，72，82)，其包括半导体器件(4)，该半导体器件包括表面(8)、由涂敷在所述表面(8)上的光致抗蚀剂层(11)制成的带图案的掩模(14)，其中所述光致抗蚀剂层(11)包括被凸块(15，16，75，76)填充的至少一个孔(12，13)；以及
具有天线结构(18)的衬底(3)，将具有所述带图案的掩模(14)的所述集成电路(2，72，82)附接到所述衬底(3)，其中所述凸块(15，16，75，76)电连接到所述天线结构(18)。
9.根据权利要求8所述的发射机应答器，其中所述凸块是金质凸块(15，16，75，76)。
10.根据权利要求8所述的发射机应答器，其中所述表面(8)包括连接焊盘(5，6)，并且所述孔(12，13)与所述连接焊盘(5，6)匹配或相对于所述连接焊盘(5，6)偏移。
11.根据权利要求8所述的发射机应答器，其中所述凸块(15，16，75，76)在所述带图案的掩模(14)上延伸少量距离(D)并且/或者与所述带图案的掩模(14)重叠。
12.根据权利要求8所述的发射机应答器，其中所述光致抗蚀剂层(11)是具有粘结特性以便将所述集成电路(2，72，82)连接到所述衬底(3)的多部件层，并且/或者所述光致抗蚀剂层(11)具有预定厚度(d)。
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