CN101490839B - 集成电路、发射机应答器、制造集成电路的方法和制造发射机应答器的方法 - Google Patents

集成电路、发射机应答器、制造集成电路的方法和制造发射机应答器的方法 Download PDF

Info

Publication number
CN101490839B
CN101490839B CN2007800261353A CN200780026135A CN101490839B CN 101490839 B CN101490839 B CN 101490839B CN 2007800261353 A CN2007800261353 A CN 2007800261353A CN 200780026135 A CN200780026135 A CN 200780026135A CN 101490839 B CN101490839 B CN 101490839B
Authority
CN
China
Prior art keywords
protuberance
integrated circuit
transponder
patterned mask
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2007800261353A
Other languages
English (en)
Other versions
CN101490839A (zh
Inventor
赖因哈德·罗吉
克里斯蒂安·岑茨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of CN101490839A publication Critical patent/CN101490839A/zh
Application granted granted Critical
Publication of CN101490839B publication Critical patent/CN101490839B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773Antenna details
    • G06K19/07775Antenna details the antenna being on-chip
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773Antenna details
    • G06K19/07777Antenna details the antenna being of the inductive type
    • G06K19/07779Antenna details the antenna being of the inductive type the inductive antenna being a coil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02333Structure of the redistribution layers being a bump
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30105Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

在制造用于发射机应答器(2,112)的集成电路(1,91,131)的方法中,在半导体器件(3)的第一表面(8)上涂覆光致抗蚀剂层(11)。通过用平版印刷工艺使光致抗蚀剂层(11)形成图案以使光致抗蚀剂层(11)包括至少一个第一通孔(12,13),来产生带图案的掩模(14,94)。带图案的掩模(14,94)包括背向第一表面(8)的第二表面(17)。通过在第一表面(8)上沉积第一隆起(15,16)来用第一隆起(15,16)填充第一通孔(12,13)。在带图案的掩模(14,94)的第二表面(17)上形成导电结构(18,19,98,99,132)。导电结构(18,19,98,99,132)电连接至第一隆起(15,16)。

Description

集成电路、发射机应答器、制造集成电路的方法和制造发射机应答器的方法
技术领域
本发明涉及集成电路、发射机应答器、制造集成电路的方法和制造发射机应答器的方法。
背景技术
发射机应答器或标签包括集成电路和天线。集成电路被设计为处理用天线捕捉到的信号,响应于捕捉到的信号,产生将通过天线发射出去的应答信号。天线通常由衬底支撑,而通过所谓的倒装片固定工艺将集成电路附接到衬底。
已知的集成电路包括面向衬底的表面处的触点。这些触点包括连接至隆起的连接焊盘,这些隆起被电连接至天线。当制造发射机应答器时,例如通过利用涂在衬底上的粘结层来将集成电路附接至衬底。随后将集成电路压在具有粘结层的衬底上,其中包括隆起的电路表面面向衬底。由于压力,集成电路,特别是在集成电路内的连接焊盘以及连接焊盘周围的区域会受到严重的应力,这会引起隆起和/或隆起周围的天线的可能的变形。因此,连接焊盘应当具有相对较大的表面,而且集成电路应当只在连接焊盘周围具有结构,以抵抗结合过程中的压力。
已公开的美国专利申请2002/0001937A1公开了一种用于在其上安装半导体芯片的半导体封装板。所述半导体板包括具有开口来将半导体芯片接受进来的金属基板以及布置在金属基板上的多层布线膜。所述半导体芯片是结合在金属焊盘上的倒装片,所述金属焊盘布置在开口内的多层布线膜上。通过在金属基板的表面上形成抗蚀剂板来制造所述半导体封装板。抗蚀剂板具有要用金属焊盘和金属化薄膜填充的开口。然后,去除抗蚀剂板。接下来,在金属基板上形成由绝缘树脂制成的并包括通孔的带图案的绝缘层。然后,在该绝缘层上形成布线层。布线层电连接至填充了绝缘层中的通孔的导电材料。然后,重复形成绝缘层和布线层的步骤以形成多层布线膜。接下来,在多层布线膜的后表面和金属基板的前表面上形成抗蚀剂。用抗蚀剂作为掩模来对金属基板进行蚀刻,直至暴露出多层布线膜,从而形成了凹槽。然后去除抗蚀剂。
已公开的美国专利申请2003/0017414A1公开了一种制造具有焊料隆起、集成底部填充以及单独焊剂涂覆的倒装片的方法。最初,对在其表面上具有连接焊盘和涂覆到其表面上的底部填充材料的半导体器件进行处理,以便底部填充材料形成精确地位于连接焊盘上的孔。底部填充材料的主要成分是热塑树脂。因为光烧蚀工艺只需要少量加热,所以采用光烧蚀工艺制成这些孔。然后,用焊料材料填充这些孔以形成电连接至焊盘的焊料隆起。焊料隆起在底部填充材料上略有延伸。
当通过将倒装片压向衬底并加热焊料隆起来将倒装片固定在衬底上时,那么,底部填充的热塑树脂软化甚至融化,从而很容易变形,因此,连接焊盘和连接焊盘周围的区域仍然处于相对较高的温度,这将导致发射机应答器不能正常工作。
发明内容
本发明的一个目的是提供一种制造用于发射机应答器的集成电路的方法,所述发射机应答器包括附接到具有天线结构的衬底上的集成电路,还提供一种制造这种发射机应答器的方法,这种方法允许制造集成电路,其中在装配步骤过程中,对连接焊盘和位于到衬底的连接焊盘附近的集成电路区域出现了较小的应力。
本发明的其他目的是提供一种相应的集成电路和相应的发射机应答器。
通过制造用于发射机应答器的集成电路可以实现根据本发明的目的,所述方法包括下列步骤:
在半导体器件的第一表面上涂覆光致抗蚀剂层;
通过平版印刷工艺使光致抗蚀剂层形成图案以使光致抗蚀剂层包括至少一个第一通孔,从而来产生带图案的掩模;所述带图案的掩模包括背向第一表面的第二表面;
通过在第一表面上沉积第一隆起来用第一隆起填充第一通孔;以及
在带图案的掩模的第二表面上形成电连接至第一隆起的导电结构。
通过先在半导体器件的表面上涂覆光致抗蚀剂层来制造本发明的集成电路。特别地,半导体器件是裸片。从而,采用一个晶片,在沉积导电结构之后,从晶片分离出每个均包括一个裸片的单个的集成电路,从而可以制造多个集成电路。
光致抗蚀剂层被用作针对沉积在半导体器件的第一表面上的至少一个第一隆起的带图案的掩模。与焊料隆起相反,由沉积工艺形成的隆起相对容易制造。另外,沉积的隆起具有相对高的电导率,特别是在根据本发明的实施例的情况下所沉积的隆起是金质隆起时。第一表面可以包括至少一个连接焊盘。可以以算一通孔与连接焊盘匹配的方式产生第一通孔。在这种情况下,可以将第一隆起直接沉积在连接焊盘上。为了改善第一隆起的沉积,还可以用焊瘤(特别是金质焊瘤)覆盖连接焊盘。还可以相对于连接焊盘使通孔偏移。那么,诸如焊瘤之类的导电结构可以在半导体器件的第一表面上延伸,以便它位于第一通孔的下面。从而,在焊瘤上沉积第一隆起,并从而通过焊瘤将第一隆起连接至连接焊盘。
然后,在由光致抗蚀剂形成的带图案的掩模上直接形成导电结构。因此,由于带图案的掩模没有被去除,但可以被用作导电结构的重新分配层,产生本发明的集成电路相对简单,从而节省了制造成本。
光致抗蚀剂层的另一个优点是,与由交叉连接树脂制成的热塑层相比,其相对较硬且较少受到在附接本发明的集成电路过程中的变形的影响。这在包括利用在天线结构的衬底上进行压力接合来获得发射机应答器时特别有利。
因此,在这种结合步骤中,带图案的掩模将吸收相对大量的应力,在集成电路中缓解连接焊盘和连接焊盘周围的区域。这允许减小连接焊盘的大小,并减少关于半导体器件内的连接焊盘周围区域的限制。
半导体器件内的天线结构和导电层形成了杂散电容,这种杂散电容会影响发射机应答器的性能,特别是在用作RFID(射频识别)或UHF(超高频)标签时。杂散电容取决于天线结构和集成电路之间的距离。由于可以制造具有预定层厚度的由光致抗蚀剂材料制成的带图案的掩模,这个厚度在将集成电路附接到衬底的步骤中很难改变(如果不是根本无法改变的话),所以产生的发射机应答器具有预定的杂散电容,这使得很容易对发射机应答器进行调谐。
另外,带图案的掩模至少可以部分地作为衬底和集成电路之间的底部填充,至少部分地吸收特别是塑料衬底会面临的热机械应力。而且,在压力接合过程中,不只是第一隆起受到产生的压力的影响,压力还散布到带图案的掩模上。这对天线结构会产生较小的应力。
这种连接结构可以被用来连接至第二隆起。根据本发明方法的一个实施例,第二隆起沉积在带图案的掩模的第二表面上,相对第一通孔有偏移,并接触导电结构。当用来制造发射机应答器时,可以是金质隆起的第二隆起具体地被用来电连接至衬底的天线结构。由于第二隆起相对于通孔有偏移,所以第二隆起相对于第一隆起也有偏移,从而不与集成电路的半导体器件有直接接触。因此,当将集成电路压向衬底来制造发射机应答器时,第二隆起不直接压向半导体器件。由于带图案的掩模也至少部分地吸收了压力,所以连接焊盘和半导体器件受到更少的应力,这允许用于集成电路的更小的连接焊盘,并允许不很苛刻的半导体器件设计。
根据本发明的方法的可替换实施例,在光致抗蚀剂层中形成至少一个第二通孔,用第二隆起填充第二通孔,并且在带图案的掩模的第二表面上形成导电结构来将第一隆起电连接至可以是金质隆起的第二隆起。特别地,如果在集成电路的边缘形成第二通孔,那么,发射机应答器的天线结构可以在它的侧壁上连接至集成电路。在这种情况下,集成电路还可以被正向安装在衬底上。
上文已经提及,集成电路要被用于发射机应答器,除了集成电路之外,所述发射机应答器还包括具有天线结构的衬底,所述天线结构可以被连接至第二隆起。
根据本发明的方法的一个实施例,带图案的掩模上的导电结构是天线。如果这个天线是发射机应答器的主天线,那么,集成电路可以形成一个完整的发射机应答器。可替换地,这个天线可以是要被耦接至发射机应答器的另一个天线的天线。
还可以根据本发明通过集成电路来实现发明目的,所述集成电路包括:半导体器件,其包括第一表面;带图案的掩模,其由涂覆在第一表面上的光致抗蚀剂层制成,其中,光致抗蚀剂层至少具有一个用沉积在第一表面上的第一隆起填充的通孔,其中,带图案的掩模包括背向第一表面的第二表面;以及导电结构,所述导电结构沉积在第二表面上,并电连接至第一隆起。
导电结构可以是天线,以便本发明的集成电路形成了发射机应答器,第一隆起可以是金质隆起。
本发明的集成电路还可以与包括天线结构的衬底组合使用来形成发射机应答器。
本发明的集成电路的一个实施例可以包括至少一个沉积在带图案的掩模的第二表面上的第二隆起,其中,第二隆起相对于第一通孔有偏移,并接触导电结构。包括这个版本的发明的集成电路的发明的发射机应答器可以包括具有天线结构的衬底,其中,所述衬底附接至本发明的集成电路的第二表面,以便天线结构电连接至第二隆起。
在发明的集成电路的另一个实施例中,带图案的掩模具有至少一个用第二隆起填充的第二通孔,第二隆起通过导电结构电连接至第一隆起。包括这个版本的发明的集成电路的发明的发射机应答器可以包括具有天线结构的衬底,其中,所述衬底附接至本发明的集成电路,以便第二表面背向衬底,其中,一个连接将天线结构电连接至第二隆起。
附图说明
参照附图中的实施例,通过非限制性示例,在下文中详细说明了本发明。
图1至图6是图示了制造本发明的集成电路的示范性实施例的步骤;
图7是包括图1至图6的集成电路的发射机应答器;
图8是图示了制造图1至图6的集成电路和图7的发射机应答器的流程图;
图9至图11是图示了制造本发明的集成电路的可替换实施例的步骤;
图12是包括图9至图11的集成电路的可替换发射机应答器;
图13和图14示出了发明的集成电路的另一个示范性实施例。
具体实施方式
图1至图6是图示了制造用于图7所示发射机应答器2的本发明的集成电路1的示范性实施例的步骤。图8是图示了制造集成电路1和发射机应答器2的相关流程图。
为了制造集成电路1,例如,采用通常已知技术在晶片上制造如图1所示的半导体器件3。对于示范性实施例,半导体器件3包括用于处理发射机应答器2接收到的信号并用于对接收到的信号进行应答的电路,还包括连接焊盘5、6以及钝化层7。提供了连接至集成电路1的天线的连接焊盘5、6。钝化层7是密封层,防止电路的电性能由于化学反应、腐蚀或包装过程中的处理而降低。对于示范性实施例而言,钝化层7的材料是氮化硅,形成了半导体器件3的表面8。通过钝化层7的孔9、10可以连接到连接焊盘5、6。
对于示范性实施例而言,半导体器件3还包括焊瘤4,将焊瘤4涂覆在连接焊盘5、6上作为下述隆起处理的种子层。对于示范性实施例,焊瘤4由金制成,覆盖了孔9、10的侧壁,而且和钝化层7有轻微的重叠。可以通过标准平版印刷工艺或者还可以用烧蚀工艺构成焊瘤4。在不采用无电隆起工艺时,通过导线可以连接焊瘤4,随后在采用锯切、蚀刻或其他合适的工艺将晶片切成小片的切割过程中分离这些导线。
之后,如图2所示,在钝化层7的表面8上沉积光致抗蚀剂层11。对于示范性实施例,光致抗蚀剂层11是利用旋涂工艺沉积在表面8上的,具有18μm的厚度。旋涂是一种使光致抗蚀剂旋涂在晶片上(特别是在表面8上)以产生光致抗蚀剂层11的技术。光致抗蚀剂层11具有背向半导体器件3的表面17。
在光致抗蚀剂层11干燥之后,利用平版印刷使光致抗蚀剂层11形成图案。平版印刷是一种图案转印工艺。当利用光时,那么,这种工艺被称为“光刻平版印刷”。当图案小到要用微米测量时,那么这种工艺就被称为微“平版印刷”。
由于图案成形工艺,如图3所示,在光致抗蚀剂层11中形成了匹配和暴露连接焊盘5、6(包括涂覆在链接焊盘5、6上的焊瘤4)的通孔12、13。包括通孔12、13的光致抗蚀剂层11形成了带图案的掩模14,而且还使表面17背向半导体器件3,并被用于下一个制造步骤。
如图4所示,下一个制造步骤是在通孔12、13中沉积隆起15、16。对于示范性实施例而言,隆起15、16是金质隆起,并通过无电沉积工艺被沉积在焊瘤4上的。
之后,如图5所示,在带图案的掩模14的表面17上和在隆起15、16上沉积另外的焊瘤18、19。对于示范性实施例而言,焊瘤18、19由金制成,并且是通过蒸镀或溅射工艺沉积的,并通过消融工艺形成图案。焊瘤18、19是电连接至隆起15、16的导电结构。
对于示范性实施例而言,然后,为了获得集成电路1,在焊瘤18、19上以及在带图案的掩模14的表面17上沉积了另外两个隆起20、21。隆起20、21是由金制成的,并相对于通孔12、13有偏移。对于示范性实施例而言,以在抗蚀剂的显影过程中使光致抗蚀剂11不融化或不被损坏的方式适用于根据采用的抗蚀剂而使用的隆起掩模工艺。
与天线22结合的集成电路1是要被用作图7所示的发射机应答器2。天线22是涂覆在衬底23上的导电结构。在继续制造发射机应答器2之前,切开晶片来获得示范性实施例的单个集成电路1。为了将具有天线22的衬底23附接到集成电路1以便使隆起20、21电连接至天线22,表面17面向天线22附接到的衬底23的一侧来将集成电路1压向衬底23。例如,通过压焊和超声波焊接可以执行这个连接步骤。不过,其他技术也可以用于这个连接步骤。另外,可以在集成电路1的表面17和衬底23之间提供粘结层24。
应当理解的是,光致抗蚀剂层11可以是多部件层,具有将集成电路1附接到衬底23的粘合特性。这种多部件层的一个示例是包括紫外线曝光剂和热引发剂的基于丙烯酸的光致抗蚀剂。从而,可以采用通过UV辐射在光致抗蚀剂层中生成孔12、13的平版印刷工艺来处理这种多部件层,并对这种多部件层进行部分交叉连接。在最后的装配工艺中,使光致抗蚀剂层11进行热活化、完全固化并交叉连接至衬底23。在这种情况下,在带图案的掩模14与衬底23之间不需要其他的粘合剂层。
图8示出了获得发射机应答器2的步骤。第一步,将光致抗蚀剂层11涂覆到半导体器件3的表面8上。第二步,通过平版印刷工艺产生带图案的掩模14,从而获得与连接焊盘5、6匹配关联的通孔12、13。第三步,用隆起15、16填充通孔12、13。第四步,在带图案的掩模14上沉积电连接至隆起15、16的焊瘤18、19。第五步,在带图案的掩模14上沉积隆起20、21,隆起20、21相对于通孔12、13有偏移,并和焊瘤18、19接触。最后,通过将集成电路1附接到包括天线22的衬底23上,获得发射机应答器2。
图9至图11图示了制造集成电路91的可替换实施例。如果没有明确地提及,那么,用相同的标号表示对应于集成电路1的部件的集成电路91的部件。
在烘干光致抗蚀剂层11之后,使光致抗蚀剂层11形成图案来生成在图9中示出的带图案的掩模94。与集成电路1的带图案的掩模14相似,带图案的掩模94包括暴露了焊瘤4的通孔12、13。另外,掩模94包括暴露了部分钝化层7从而暴露了部分表面8的通孔92、93。通孔92、93还位于要制造的集成电路91的边缘。包括通孔12、13、92、93的光致抗蚀剂层11形成了带图案的掩模94,还使表面17背向半导体器件3并用于下一个制造步骤。
如图10所示,下一个制造步骤是在通孔12、13中沉积隆起15、16以及在通孔92、93中沉积隆起95、96。对于示范性实施例而言,隆起15、16、95、96是金质隆起,并采用无电沉积工艺分别沉积在焊瘤4上和钝化层7的表面8上。
之后,如图11所示,在带图案的掩模94的表面17上以及在隆起15、16、95、96上沉积其他的焊瘤98、99。对于示范性实施例而言,焊瘤98、99由金制成,是利用蒸镀或溅射工艺沉积的,并且是通过烧蚀工艺形成图案的。焊瘤98、99是将隆起15电连接至隆起95并将隆起16电连接至隆起96的导电结构。因此,连接焊盘5电连接至隆起95,连接焊盘6电连接至隆起96。
与天线122结合的集成电路91形成了如图12所示的发射机应答器112。天线122是附接到衬底123的导电结构。在继续制造发射机应答器112之前,切开晶片,从而获得示范性实施例的单个集成电路91。
集成电路91具有与表面17相对的表面100。对于示范性实施例而言,用集成电路91的表面100将它附接到衬底123。从而,用焊料隆起125、126将天线122的导电结构连接至隆起95、96。因此,并非用倒装片技术连接天线122,而是将天线122连接至示范性实施例的集成电路91的侧壁101、102。
图13示出了集成电路131的另一个实施例。如果没有明确提及,那么用相同的参考标号表示对应于集成电路1的部件的集成电路131的部件。
集成电路1和131的主要区别在于集成电路131所缺少的焊瘤18、19以及隆起20、21。取代连接至隆起20、21的焊瘤18、19,集成电路131包括沉积在带图案的掩模14的表面17上的导电结构。对于示范性实施例而言,导电结构是连接至隆起15、16的环形天线132。图14示出了包括天线132的集成电路131的表面17的俯视图。
天线132可以是集成电路131的主天线。那么,集成电路131可以形成一个完整的发射机应答器。天线132还可以是要被耦接至图中未示出的另一个天线的耦接天线。那么,当耦接至这个主天线时,集成电路131形成了发射机应答器。
最后,应当理解的是,上述实施例是对本发明的说明而不是对本发明的限制,在不脱离所附权利要求所限定的本发明的范围时,本领域技术人员可以设计出很多可替换实施例。在权力要求中,放置在括号中的任何参考标号不应当被解释为对本发明的限制。所用词“包含”、“包括”等并不排除在作为整体的任一权利要求或说明书中没有列出的元件或步骤的存在。元素的单数不排除多个这种元素的复数,反之亦然。在列举了多个装置的装置权利要求中,可以用硬件的一个和相同的硬件项来实现这些装置中的几个。事实是在互相不同的从属权利要求中引用的某些措施并不表示不能结合这些措施来获得优势。

Claims (6)

1.一种制造用于发射机应答器(2,112)的集成电路(1,91,131)的方法,所述方法包括下列步骤:
在半导体器件(3)的第一表面(8)上涂覆光致抗蚀剂层(11);
通过平版印刷工艺使所述光致抗蚀剂层(11)形成图案以使光致抗蚀剂层(11)包括至少一个第一通孔(12,13),从而产生带图案的掩模(14,94);所述带图案的掩模(14,94)包括背向所述第一表面(8)的第二表面(17);
通过在所述第一表面(8)上沉积第一隆起(15,16),从而用第一隆起(15,16)填充所述第一通孔(12,13);以及
在所述带图案的掩模(14,94)的所述第二表面(17)上形成电连接至所述第一隆起(15,16)的导电结构(18,19,98,99,132);
所述方法还包括:
在所述带图案的掩模(14)的所述第二表面(17)上沉积至少一个第二隆起(20,21);所述第二隆起(20,21)相对于所述第一通孔(12,13)有偏移并接触所述导电结构(18,19),或者
在所述光致抗蚀剂层(11)中产生至少一个第二通孔(92,93),用第二隆起(95,96)填充所述第二通孔(92,93),并在所述带图案的掩模(94)的所述第二表面(17)上形成所述导电结构(98,99),以将所述第一隆起(15,16)电连接至所述第二隆起(95,96)。
2.根据权利要求1所述的方法,其中,所述第一隆起(15,16)是金质隆起,和/或其中,所述导电结构是天线(132)。
3.一种制造发射机应答器(2)的方法,其包括下列步骤:
制造根据权利要求1所述的集成电路(1);以及
如果至少一个第二隆起(20,21)已经沉积在所述第二表面(17)上,通过所述第二表面(17)将所述集成电路(1)附接至包括天线结构(22)的衬底(23),以便所述天线结构(22)电连接至所述第二隆起(20,21),或者如果在所述光致抗蚀剂层(11)中已经产生了至少一个第二通孔(92,93),将所述集成电路(91)附接至包括天线结构(122)的衬底(123),以便所述第二表面(17)背向所述衬底(123);以及
用所述第二隆起(95,96)电连接所述天线结构(122)。
4.一种用于发射机应答器(2,112)的集成电路,其包括:
半导体器件(3),所述半导体器件包括第一表面(8);
带图案的掩模(14,94),所述带图案的掩模由光致抗蚀剂层(11)制成,并被涂覆在所述第一表面(8)上,其中,所述光致抗蚀剂层(11)包括至少一个第一通孔(12,13),所述至少一个第一通孔被沉积在所述第一表面(8)上的第一隆起(15,16)填充;所述带图案的掩模(14,94)包括背向所述第一表面(8)的第二表面(17);以及
导电结构(18,19,98,99,132),所述导电结构沉积在所述第二表面(17)上并被电连接至所述第一隆起(15,16);所述集成电路还包括至少一个沉积在所述带图案的掩模(14)的所述第二表面(17)上的第二隆起(20,21);所述第二隆起(20,21)相对于所述第一通孔(12,13)有偏移并与所述导电结构(18,19)接触,或者所述集成电路还包括所述带图案的掩模(94)中的至少一个用第二隆起(95,96)填充的第二通孔(92,93),所述第二隆起通过所述导电结构(98,99)电连接至所述第一隆起(15,16)。
5.根据权利要求4所述的集成电路,其中,所述第一隆起(15,16)是金质隆起,和/或其中,所述导电结构是天线(132)。
6.一种发射机应答器,其包括:
根据权利要求4所述的集成电路(1);以及
如果所述集成电路包括至少一个沉积在所述第二表面(17)上的第二隆起(20,21),则所述发射机应答器还包括具有天线结构(22)的衬底(23),所述衬底(23)被附接至所述集成电路(1)的所述第二表面(17),以便所述天线结构(22)被电连接至所述第二隆起(20,21),或者
如果所述集成电路包括至少一个所述带图案的掩模(94)中的第二通孔(92,93),则所述发射机应答器还包括衬底(123),所述衬底包括天线结构(122),所述衬底(123)被附接至所述集成电路(91),以便所述第二表面(17)背向所述衬底(123);以及
连接部分(125,126),所述连接部分将所述天线结构(122)与所述第二隆起(95,96)电连接起来。
CN2007800261353A 2006-07-10 2007-07-09 集成电路、发射机应答器、制造集成电路的方法和制造发射机应答器的方法 Active CN101490839B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP06116899.3 2006-07-10
EP06116899 2006-07-10
PCT/IB2007/052692 WO2008007327A2 (en) 2006-07-10 2007-07-09 Integrated circuit, transponder, method of producing an integrated circuit and method of producing a transponder

Publications (2)

Publication Number Publication Date
CN101490839A CN101490839A (zh) 2009-07-22
CN101490839B true CN101490839B (zh) 2011-02-23

Family

ID=38814493

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007800261353A Active CN101490839B (zh) 2006-07-10 2007-07-09 集成电路、发射机应答器、制造集成电路的方法和制造发射机应答器的方法

Country Status (4)

Country Link
US (1) US8844826B2 (zh)
EP (1) EP2041786A2 (zh)
CN (1) CN101490839B (zh)
WO (1) WO2008007327A2 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2949018B1 (fr) * 2009-08-06 2012-04-20 Rfideal Connexion ohmique au moyen de zones de connexion elargies dans un objet electronique portatif
EP2337068A1 (en) * 2009-12-18 2011-06-22 Nxp B.V. Pre-soldered leadless package
US9431369B2 (en) 2012-12-13 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna apparatus and method
US10002266B1 (en) 2014-08-08 2018-06-19 Impinj, Inc. RFID tag clock frequency reduction during tuning
DE102014018393A1 (de) * 2014-10-14 2016-04-14 Infineon Technologies Ag Chipkartenmodul-Anordnung, Chipkarten-Anordnung und Verfahren zum Herstellen einer Chipkarten-Anordnung
TWI621229B (zh) * 2015-04-27 2018-04-11 精材科技股份有限公司 晶片封裝體及其製造方法

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3503124A (en) * 1967-02-08 1970-03-31 Frank M Wanlass Method of making a semiconductor device
US5130275A (en) * 1990-07-02 1992-07-14 Digital Equipment Corp. Post fabrication processing of semiconductor chips
DE4034225C2 (de) * 1990-10-26 1994-01-27 Reinhard Jurisch Datenträger für Identifikationssysteme
US5139880A (en) * 1990-12-18 1992-08-18 Allied-Signal Inc. Photodefinable interlevel dielectrics
JP2887985B2 (ja) * 1991-10-18 1999-05-10 日本電気株式会社 半導体装置及びその製造方法
US5707782A (en) * 1996-03-01 1998-01-13 The Board Of Trustees Of The University Of Illinois Photoimageable, dielectric, crosslinkable copolyesters
US5965933A (en) * 1996-05-28 1999-10-12 Young; William R. Semiconductor packaging apparatus
US6388202B1 (en) * 1997-10-06 2002-05-14 Motorola, Inc. Multi layer printed circuit board
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
EP1048483B1 (en) * 1997-12-22 2007-07-11 Hitachi, Ltd. Card-like semiconductor device
KR100285702B1 (ko) * 1998-09-29 2001-04-02 윤종용 반도체 디램용 콘택 및 그 제조 방법
WO2000019517A1 (fr) 1998-09-30 2000-04-06 Ibiden Co., Ltd. Microplaquette semi-conductrice et procede de fabrication
US6281106B1 (en) * 1999-11-25 2001-08-28 Delphi Technologies, Inc. Method of solder bumping a circuit component
JP2001284499A (ja) 2000-03-09 2001-10-12 Lucent Technol Inc 半導体デバイスとその製造方法
US6841862B2 (en) 2000-06-30 2005-01-11 Nec Corporation Semiconductor package board using a metal base
JP2002026056A (ja) * 2000-07-12 2002-01-25 Sony Corp 半田バンプの形成方法及び半導体装置の製造方法
US6424315B1 (en) * 2000-08-02 2002-07-23 Amkor Technology, Inc. Semiconductor chip having a radio-frequency identification transceiver
TW488052B (en) * 2001-05-16 2002-05-21 Ind Tech Res Inst Manufacture process of bumps of double layers or more
US6734568B2 (en) * 2001-08-29 2004-05-11 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
DE60108793T2 (de) * 2001-10-31 2006-01-19 Sokymat S.A. Integrierter schaltkreis mit optimierten abmessungen für transponder
US6586322B1 (en) * 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
US6696356B2 (en) * 2001-12-31 2004-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate without ribbon residue
US6812040B2 (en) * 2002-03-12 2004-11-02 Freescale Semiconductor, Inc. Method of fabricating a self-aligned via contact for a magnetic memory element
EP1369919A1 (en) 2002-05-24 2003-12-10 Ultratera Corporation Flip chip package
TW200506516A (en) * 2003-04-09 2005-02-16 Rohm & Haas Elect Mat Photoresists and methods for use thereof
CN1291069C (zh) * 2003-05-31 2006-12-20 香港科技大学 微细间距倒装焊凸点电镀制备方法
JP2005093867A (ja) * 2003-09-19 2005-04-07 Seiko Epson Corp 半導体装置及びその製造方法
TWI278084B (en) * 2004-10-19 2007-04-01 Advanced Semiconductor Eng Chip scale package with micro antenna and method for manufacturing the same
JP2006131926A (ja) * 2004-11-02 2006-05-25 Sharp Corp 微細孔に対するメッキ方法、及びこれを用いた金バンプ形成方法と半導体装置の製造方法、並びに半導体装置
US7410884B2 (en) * 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US20070158804A1 (en) 2006-01-10 2007-07-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method of semiconductor device, and RFID tag
US8201746B2 (en) * 2006-01-24 2012-06-19 Agency For Science, Technology And Research On-chip antenna and a method of fabricating the same
TWI295499B (en) * 2006-05-02 2008-04-01 Novatek Microelectronics Corp Chip structure and fabricating process thereof

Also Published As

Publication number Publication date
WO2008007327A3 (en) 2008-03-13
WO2008007327A2 (en) 2008-01-17
US8844826B2 (en) 2014-09-30
CN101490839A (zh) 2009-07-22
US20090283602A1 (en) 2009-11-19
EP2041786A2 (en) 2009-04-01

Similar Documents

Publication Publication Date Title
CN101490830B (zh) 发射机应答器以及制造发射机应答器的方法
CN101490839B (zh) 集成电路、发射机应答器、制造集成电路的方法和制造发射机应答器的方法
US6915566B2 (en) Method of fabricating flexible circuits for integrated circuit interconnections
US6953999B2 (en) High density chip level package for the packaging of integrated circuits and method to manufacture same
US9265161B2 (en) Method of manufacturing an embedded printed circuit board
JP4418833B2 (ja) 回路基板の製造方法
US7341934B2 (en) Method for fabricating conductive bump of circuit board
US20030197285A1 (en) High density substrate for the packaging of integrated circuits
KR101117887B1 (ko) 마이크로전자 워크피스 및 이 워크피스를 이용한 마이크로전자 디바이스 제조 방법
US20090097214A1 (en) Electronic chip embedded circuit board and method of manufacturing the same
KR100896810B1 (ko) 인쇄회로기판 및 그 제조방법
EP3836209B1 (en) Component carrier and method of manufacturing the same
CN112074989B (zh) 一种天线封装结构及其制造方法
US7972903B2 (en) Semiconductor device having wiring line and manufacturing method thereof
CN113035831A (zh) 晶圆级芯片封装结构及其制作方法和电子设备
CN113035832B (zh) 晶圆级芯片封装结构及其制作方法和电子设备
EP3833163A1 (en) Method of manufacturing component carrier and component carrier
US20150103494A1 (en) Printed circuit boards having metal layers and semiconductor packages including the same
KR20070030700A (ko) 전자 부품 내장 기판 및 그 제조 방법
JP5736714B2 (ja) 半導体装置及びその製造方法
CN104425431A (zh) 基板结构、封装结构及其制造方法
JP3874059B2 (ja) 半導体装置の製造方法
CN107611112A (zh) 一种扇出型封装器件
JP3279461B2 (ja) 半導体装置、配線基板およびこれらの製造方法
US20090152720A1 (en) Multilayer chip scale package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant