CN101385133B - 形成具有不对称电介质区域的半导体器件的方法及其结构 - Google Patents

形成具有不对称电介质区域的半导体器件的方法及其结构 Download PDF

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CN101385133B
CN101385133B CN2006800033691A CN200680003369A CN101385133B CN 101385133 B CN101385133 B CN 101385133B CN 2006800033691 A CN2006800033691 A CN 2006800033691A CN 200680003369 A CN200680003369 A CN 200680003369A CN 101385133 B CN101385133 B CN 101385133B
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gate electrode
oxidation
dielectric
semiconductor substrate
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CN101385133A (zh
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L.·马修
V.·R.·克拉冈塔
D.·C.·辛格
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NXP USA Inc
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Freescale Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

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  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN2006800033691A 2005-03-29 2006-02-01 形成具有不对称电介质区域的半导体器件的方法及其结构 Active CN101385133B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/092,289 2005-03-29
US11/092,289 US7282426B2 (en) 2005-03-29 2005-03-29 Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof
PCT/US2006/003528 WO2006104562A2 (en) 2005-03-29 2006-02-01 Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof

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CN101385133A CN101385133A (zh) 2009-03-11
CN101385133B true CN101385133B (zh) 2010-12-08

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US (2) US7282426B2 (enExample)
JP (1) JP5049955B2 (enExample)
CN (1) CN101385133B (enExample)
TW (1) TWI425576B (enExample)
WO (1) WO2006104562A2 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6921691B1 (en) * 2004-03-18 2005-07-26 Infineon Technologies Ag Transistor with dopant-bearing metal in source and drain
US8178902B2 (en) * 2004-06-17 2012-05-15 Infineon Technologies Ag CMOS transistor with dual high-k gate dielectric and method of manufacture thereof
US8399934B2 (en) * 2004-12-20 2013-03-19 Infineon Technologies Ag Transistor device
US7344934B2 (en) 2004-12-06 2008-03-18 Infineon Technologies Ag CMOS transistor and method of manufacture thereof
US7160781B2 (en) * 2005-03-21 2007-01-09 Infineon Technologies Ag Transistor device and methods of manufacture thereof
US7361538B2 (en) * 2005-04-14 2008-04-22 Infineon Technologies Ag Transistors and methods of manufacture thereof
US8188551B2 (en) * 2005-09-30 2012-05-29 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US20070052037A1 (en) * 2005-09-02 2007-03-08 Hongfa Luan Semiconductor devices and methods of manufacture thereof
US20070052036A1 (en) * 2005-09-02 2007-03-08 Hongfa Luan Transistors and methods of manufacture thereof
US7462538B2 (en) * 2005-11-15 2008-12-09 Infineon Technologies Ag Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials
US7510943B2 (en) * 2005-12-16 2009-03-31 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US20080050898A1 (en) * 2006-08-23 2008-02-28 Hongfa Luan Semiconductor devices and methods of manufacture thereof
US8999786B1 (en) 2007-03-20 2015-04-07 Marvell International Ltd. Reducing source contact to gate spacing to decrease transistor pitch
KR100950473B1 (ko) * 2007-12-28 2010-03-31 주식회사 하이닉스반도체 균일한 두께의 게이트스페이서막을 갖는 반도체소자의제조방법
KR100997290B1 (ko) * 2008-07-25 2010-11-29 주식회사 동부하이텍 반도체 소자 및 반도체 소자의 제조 방법
WO2011112574A1 (en) * 2010-03-08 2011-09-15 Mears Technologies, Inc Semiconductor device including a superlattice and dopant diffusion retarding implants and related methods
US9397217B2 (en) * 2012-12-28 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of non-planar semiconductor device
CN107039522B (zh) * 2016-02-04 2019-12-31 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
WO2018182627A1 (en) * 2017-03-30 2018-10-04 Intel Corporation Transistors including asymmetric gate spacers

Citations (4)

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US6127248A (en) * 1998-02-27 2000-10-03 Hyundai Electronics Industries Co., Ltd. Fabrication method for semiconductor device
US6352885B1 (en) * 2000-05-25 2002-03-05 Advanced Micro Devices, Inc. Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same
CN1520613A (zh) * 2001-05-26 2004-08-11 Ħ��������˾ 半导体装置和形成半导体装置的方法
US6806584B2 (en) * 2002-10-21 2004-10-19 International Business Machines Corporation Semiconductor device structure including multiple fets having different spacer widths

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JPH04246862A (ja) * 1991-02-01 1992-09-02 Mitsubishi Electric Corp 半導体集積回路及び半導体集積回路製造方法
JPH06151451A (ja) * 1992-11-09 1994-05-31 Oki Electric Ind Co Ltd 半導体装置の製造方法
KR0136932B1 (ko) * 1994-07-30 1998-04-24 문정환 반도체 소자 및 그의 제조방법
JP2003133549A (ja) * 2001-10-29 2003-05-09 Nec Corp Ｍｏｓｆｅｔ及びその製造方法
US6544848B1 (en) * 2002-08-20 2003-04-08 Chartered Semiconductor Manufacturing Ltd. Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers
US6746924B1 (en) * 2003-02-27 2004-06-08 International Business Machines Corporation Method of forming asymmetric extension mosfet using a drain side spacer
US20060022264A1 (en) * 2004-07-30 2006-02-02 Leo Mathew Method of making a double gate semiconductor device with self-aligned gates and structure thereof

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US6127248A (en) * 1998-02-27 2000-10-03 Hyundai Electronics Industries Co., Ltd. Fabrication method for semiconductor device
US6352885B1 (en) * 2000-05-25 2002-03-05 Advanced Micro Devices, Inc. Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same
CN1520613A (zh) * 2001-05-26 2004-08-11 Ħ��������˾ 半导体装置和形成半导体装置的方法
US6806584B2 (en) * 2002-10-21 2004-10-19 International Business Machines Corporation Semiconductor device structure including multiple fets having different spacer widths

Non-Patent Citations (1)

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Also Published As

Publication number Publication date
US7282426B2 (en) 2007-10-16
JP2009501432A (ja) 2009-01-15
TW200711005A (en) 2007-03-16
JP5049955B2 (ja) 2012-10-17
CN101385133A (zh) 2009-03-11
WO2006104562A2 (en) 2006-10-05
US20060223335A1 (en) 2006-10-05
US20080173957A1 (en) 2008-07-24
WO2006104562A3 (en) 2008-01-10
TWI425576B (zh) 2014-02-01

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