WO2018182627A1

WO2018182627A1 - Transistors including asymmetric gate spacers

Info

Publication number: WO2018182627A1
Application number: PCT/US2017/025070
Authority: WO
Inventors: Chen-Guan LEE; Walid M. Hafez; Jui-Yen Lin; Han-Ping Chen; Joodong Park
Original assignee: Intel Corporation
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2018-10-04

Abstract

Techniques are disclosed for forming transistors including asymmetric gate spacers, where the gate spacers for a given gate structure are asymmetric with respect to, at least, their horizontal widths or thicknesses. Employing relatively thinner and thicker gate spacers for a given gate stack can enable a relative decrease in gate-drain overlap capacitance without sacrificing gate-source overlap. Such a reduction of the gate-drain overlap capacitance can improve the switching speed and bandwidth of transistor-based circuits (e.g., of common-source amplifier circuits). The techniques can achieve an intentional tilted, slanted, and/or curved gate stack profile on only one side of the gate stack, while maintaining the standard straight and vertical profile on the other side of the gate stack, where the profile differences between the sides of the gate stack can be used to form relatively different gate spacer thicknesses, as will be apparent in light of this disclosure.

Description

TRANSISTORS INCLUDING ASYMMETRIC GATE SPACERS

BACKGROUND

Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon (Si), germanium (Ge), and gallium arsenide (GaAS). A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain. In instances where the charge carriers are electrons, the FET is referred to as an n-channel device, and in instances where the charge carriers are holes, the FET is referred to as a p-channel device. Some FETs have a fourth terminal called the body or substrate, which can be used to bias the transistor. In addition, metal-oxide-semiconductor FETs (MOSFETs) include a gate dielectric between the gate and the channel. Further, MOSFETs generally include side- wall spacers, which are also referred to simply as spacers, on either side of the gate that helps electrically isolate the gate from adjacent features. MOSFETs may also be known, more generally, as metal-insulator-semiconductor FETs (MISFETs) or insulated-gate FETs (IGFETs). Complementary MOS (CMOS) structures use a combination of p-channel MOSFET (p-MOS) and n-channel MOSFET (n-MOS) to implement logic gates and other digital circuits.

A FinFET is a MOSFET transistor built around a thin strip of semiconductor material

(generally referred to as a fin). The conductive channel of the FinFET device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top surface of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor. Other types of FinFET configurations are also available, such as so-called double-gate FinFETs, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top surface of the fin). A nanowire transistor (sometimes referred to as a gate-all-around (GAA) or nanoribbon transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires are used for the channel region and the gate material generally surrounds each nanowire. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a method of forming an integrated circuit (IC) including one or more transistors that include asymmetric gate spacers, in accordance with some embodiments of the present disclosure.

Figures 2A-D illustrate example IC structures that are formed when carrying out optional box 102 of the method of Figure 1, in accordance with some embodiments. Figure 2C is a blown-out portion of Figure 2C illustrating alternative recess and replace processing to form a replacement material fin, in accordance with some embodiments. Figure 2D' is a blown-out portion of Figure 2D illustrating the replacement fin from Figure 2C after the shallow trench isolation (STI) material has been recessed, in accordance with some embodiments.

Figures 3A-L illustrate example IC structures that are formed when carrying out boxes 104-124 of the method of Figure 1, in accordance with some embodiments.

Figure 4 illustrates an example transistor structure including the asymmetric gate spacers from rectangular dashed portion A-A in Figure 3L, formed when carrying out boxes 126-130 of method 100 of Figure 1, in accordance with some embodiments.

Figure 4' illustrates the example transistor structure of Figure 4 with a curved thinner gate spacer (as compared to the slanted thinner gate spacer in the structure of Figure 4), formed in accordance with some embodiments.

Figure 5 illustrates an example IC structure illustrating various different non-planar transistors including asymmetric gate spacers, in accordance with some embodiments.

Figure 6 illustrates a computing system implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. Further still, some of the features in the drawings may include a patterned and/or shaded fill, which is primarily provided to assist in visually differentiating the different features. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

A major factor that determines the speed and bandwidth of some transistor-based circuits or amplifiers is the transistor gate-drain overlap capacitance. Generally, for common-source amplifiers, it is desired to decrease the gate-drain overlap capacitance in such transistor-based circuits to reduce the resistive-capacitive (RC) penalty and increase the overall operating/switching speed. Although there are techniques available to mitigate this effect, such techniques consume additional area and/or power to achieve mitigation of the gate-drain overlap capacitance. For instance, in a standard common-source amplifier, the Miller effect causes the gate-drain overlap capacitance to be multiplied by the gain, resulting in a significant RC penalty and lower circuit speed. A technique used to eliminate the Miller effect is to employ a cascade circuit topology. However, such a cascade circuit topology requires additional area, as it requires an additional transistor plus biasing circuitry for the additional transistor, thereby requiring increased IC area. The additional transistor in the cascade circuit topology also consumes voltage headroom, so a higher positive supply voltage (Vdd or Vcc) is generally needed. Thus, while a cascade circuit topology can mitigate gate-drain overlap capacitance, it does so at the undesired cost of increased IC area and power consumption. Another techniques used to mitigate the effect of gate-drain overlap capacitance for transistor-based amplifiers is to uniformly increase the thickness of gate spacers to increase the distance between the gate and the drain, thereby reducing the related gate-drain overlap. However, such a technique also increases the distance between the gate and the source, thereby reducing the gate-source overlap, which undesirably reduces the drive current of the transistor. In addition, by uniformly increasing the thickness of the gate spacers for a given cross-sectional area, there is a decrease in gate length (the distance between the source and drain), which undesirably increases gate resistance and leads to an increase in the overall RC penalty.

Thus, and in accordance with numerous embodiments of the present disclosure, techniques are provided for forming transistors including asymmetric gate spacers, where the gate spacers for a given gate structure are asymmetric with respect to, at least, their horizontal widths or thicknesses. During initial gate stack formation using a pitch doubling approach (whether the initial gate stack is a dummy gate stack or the final gate stack), the gate length critical dimension is generally defined by the backbone spacer. In some embodiments, by using compound spacer materials with relatively different etch rates during hardmask and gate electrode (e.g., dummy poly-silicon) etch, the techniques described herein can achieve an intentional tilted gate stack profile on only one side of the gate stack, while maintaining the standard straight profile on the other side of the gate stack. In some such embodiments, the profile difference between the sides of the gate stack can be used to form relatively different gate spacer thicknesses between the gate spacers on either side of a given gate stack. As previously described, increased gate-drain overlap undesirably results in an increased RC penalty and also results in decreased circuit speeds. As was also previously described, decreased source-drain overlap undesirably results in a reduction of the transistor drive current and also results in increased gate resistance (due to the decreased gate length), thereby incurring an RC penalty. Thus, the techniques described herein can be used to achieve a relatively thinner gate spacer on the source side of a given gate stack and a relatively thicker gate spacer on the drain side of the given gate stack, to reduce the gate- drain overlap without sacrificing the gate-source overlap for a given transistor, thereby improving overall transistor performance.

In some embodiments, the techniques include using pitch doubling processing to define the gate length (also referred to as the gate critical dimension), including a method to form the asymmetric gate spacers. In some such embodiments, the method includes blanket depositing the gate stack layers (whether they be the dummy gate stack layers or the final gate stack layers) and blanket depositing hardmask material on the gate stack layers. The method continues with patterning a backbone layer (such as amorphous silicon) on the hardmask layer and patterning it into backbone spacers. The method continues with depositing a first sacrificial spacer material on top of the structure and spacerizing the first sacrificial spacer material (e.g., via dry etch processing). The method continues with depositing a second sacrificial spacer material, which has lower selectivity to the hardmask/gate stack etching than the first sacrificial spacer material, and then spacerizing the second sacrificial spacer material (e.g., via dry etch processing). The method continues with removing the backbone layer via selective etch processing to remove the backbone material relative to the exposed materials (e.g., the exposed hardmask, first sacrificial spacer, and second sacrificial spacer materials). As can be understood based on this disclosure, after the backbone layer has been removed, a given remaining structure on the hardmask layer includes the first sacrificial spacer material and the second sacrificial spacer material directly adjacent a single side of the first sacrificial spacer material, which defines the gate length for each transistor device subsequently formed therefrom.

The method continues with dry etch processing to etch the hardmask and gate stack layers relative to the first sacrificial spacer material. Recall that the second sacrificial spacer material has lower selectivity to such dry etch processing as compared to the first sacrificial spacer material, such that the second sacrificial spacer material will be consumed relatively faster than the first sacrificial spacer material (where, in some cases, that first sacrificial spacer material may not be significantly removed at all) during that dry etch processing (due to its relatively low etch selectivity), such that the slowly receding second sacrificial spacer material results in a slanted or curved profile (at least in part) on the side of the gate stack structure formed where the second spacer material was originally present. Such a slanted or curved profile on only one side of the gate stack enables the formation of a relatively thinner gate spacer on that side of the gate stack, as will be apparent in light of this disclosure. On the other side of the gate stack structure formed, the gate stack was protected by the first sacrificial spacer material, such that the sidewall profile is formed in a substantially straight and vertical manner. The first sacrificial spacer material can then be removed to allow for the gate spacer material to be deposited and spacerized (e.g., via dry etch processing), resulting in a relatively thinner gate spacer on the side of the gate stack having a slanted profile (the source side) and a relatively thicker gate spacer on the side of the gate stack having a substantially straight and vertical profile (the drain side).

The relatively thinner gate spacer is achieved based on the spacer etch (e.g., dry etch) processing being directional such that it consumes the gate spacer material in a vertical direction and not (or not significantly) in a horizontal direction, in accordance with some embodiments. Thus, the slanted or curved profile of the gate spacer material formed on the slanted or curved side of the gate stack results in that slanted or curved gate spacer material being more susceptible to removal during the directional spacer etch processing, compared to the gate spacer material on the substantially vertical sidewall of the gate stack, which only is etched from the top down, such that only the gate spacer material above that substantially vertical gate spacer is significantly removed. In other words, because there is little to no horizontal component of the spacer etch processing, such processing substantially retains the full thickness of the vertical gate spacer material, which is referred to herein as the relatively thicker gate spacer, while the gate spacer material on the slanted or curved surface is thinned down as it is exposed to more of the top- down etching, resulting in a relatively thinner gate spacer. In other embodiments, additional or alternative processing may be utilized to achieve relatively thinner and thicker gate spacers for a given gate stack, thereby achieving asymmetric gate spacers for a given gate stack, as will be apparent in light of this disclosure. Note that although the techniques are primarily described herein as forming the relatively thicker gate spacer near the drain side to reduce gate -drain overlap capacitance, in some embodiments, it may be desired to form the relatively thicker gate spacer near the source side. Therefore, the present disclosure is not intended to be specifically limited to forming the relatively thicker gate spacer near the drain side unless otherwise stated.

In some embodiments, transistors including substantially symmetric gate spacers (and thus, not including the asymmetric gate spacers described herein) may be monolithically formed on the same integrated circuit (IC) as transistors formed that include asymmetric gate spacers. In some such embodiments, the symmetric gate spacer transistors may be formed simultaneously with the asymmetric gate spacers. For instance, such symmetric gate spacers may be achieved by only forming the second sacrificial spacer material on areas used to form asymmetric gate spacer transistors, such that the slanted or curved profile achieved by employing the second sacrificial spacer material as described herein does not occur, in accordance with some embodiments. In other embodiments, the second sacrificial spacer material may be formed over the entirety of a target area and then removed from one or more regions where transistors including substantially symmetric gate spacers are desired. For instance, the second sacrificial spacer material may be removed from those regions before or after the second sacrificial spacer material is spacerized via masking off the regions where the second sacrificial spacer material is desired to be retained, for example. Numerous variations on the methodology and techniques will be apparent in light of this disclosure.

In some embodiments, the gate spacers in a given asymmetric gate spacer set may include thicknesses (e.g., between the gate stack and the corresponding nearby S/D region and/or S/D contact) or widths (e.g., dimension in a shared horizontal plane) in the range of 1-200 nm (or in a subrange of 1-10, 1-25, 1-50, 1-100, 2-10, 2-25, 2-50, 2-100, 2-200, 5-10, 5-25, 5-50, 5-100, 5- 200, 10-25, 10-50, 10-100, 10-200, 25-50, 25-100, 25-200, 50-100, 50-200, or 100-200 nm), or any other suitable value or range as can be understood based on this disclosure. Note that when thicknesses and widths of the gate spacers are described herein, such thicknesses and widths may be with reference to the maximum thicknesses/widths, average thicknesses/widths, thicknesses/widths in a given horizontal plane, thicknesses/widths between two IC features, and/or any other suitable reference for the thicknesses/widths as can be understood based on this disclosure. Also note that the thickness of a given gate spacer is not intended to be confused with the vertical height of that given gate spacer, which is referred to herein as its height. In some embodiments, the relatively thicker gate spacer (e.g., near the drain side) in a given asymmetric gate spacer set may have a thickness or horizontal width that is greater than the relatively thinner gate spacer (e.g., near the source side) by 1-50 nm (or in a subrange of 1-2, 1-5, 1-10, 1-25, 2-5, 2-10, 2-25, 2-50, 5-10, 5-25, 5-50, 10-25, 10-50, or 25-50 nm), or any other suitable value or range as can be understood based on this disclosure. In some embodiments, the relatively thicker gate spacer in a given asymmetric gate spacer set may have a thickness or horizontal width that is greater than the relatively thinner gate spacer by at least 1 , 2, 3, 4, 5, 10, 15, 20, 25, or 50 nm, or any other suitable threshold value as can be understood based on this disclosure. In some embodiments, the ratio of the thickness or horizontal width of the relatively thicker gate spacer to the thickness or horizontal width of the corresponding relatively thinner gate spacer (e.g., the ratio of the maximum widths or the ratio of the widths in a given horizontal plane) may be in the range of 1.1-3 and/or may be at least 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.25, 2.5, 2.75, 3, or any other suitable value or threshold value as can be understood based on this disclosure. Numerous relative relationships between the thicker and thinner gate spacers of a given asymmetric gate spacer set will be apparent in light of this disclosure.

In some embodiments, a given thinner gate spacer in an asymmetric gate spacer set may include a slanted or curved profile, such as a shape resembling a forward slash (e.g., /), a backward slash (e.g., \), a J-like shape (or an otherwise arc-like shape that is concave relative to the gate stack), a backward J-like shape, an arc-like shape that is convex relative to the gate stack, or any other suitable shape as will be apparent in light of this disclosure. In embodiments where a given thinner gate spacer is slanted (e.g., where it resembles a forward or backward slash), it may be sloped away from exactly vertical (e.g., as defined by the main plane of the substrate/bulk wafer being a horizontal plane and/or as defined by the gate stack being, at least, vertically above the channel) by 2-30 degrees (or an angle in a subrange of 2-5, 2-10, 2-15, 2-20, 2-25, 5-10, 5-15, 5-20, 5-25, 5-30, 10-15, 10-20, 10-25, 10-30, 15-20, 15-25, 15-30, 20-25, 20- 30, or 25-30 degrees), or any other suitable value or range as can be understood based on this disclosure. In some embodiments, a given slanted thinner gate spacer may be sloped away from exactly vertical by at least 2, 5, 10, 15, 20, 25, or 30 degrees, or at least any other suitable threshold degree value as can be understood based on this disclosure. For instance, if exactly vertical is considered 90 degrees and a given slanted thinner gate spacer is sloped away from exactly vertical by at least 10 degrees, than the slope of that gate spacer would be less than 80 degrees or greater than 100 degrees, depending on which direction the slanted spacer slopes away from exactly vertical.

In some embodiments, the profile of a given thinner gate spacer may be based on the profile of the side of the gate stack on which it is formed, where the profile of that side of the gate stack may be based on the second sacrificial spacer material and the selective etch conditions used to remove that second sacrificial spacer material (e.g., during the selective etch processing used to form the individual gate stack structures from the gate stack layers). In some embodiments, the slope of a slanted thinner gate spacer affects its final thickness, because a slanted thinner gate spacer with relatively greater slope away from exactly vertical would be more susceptible to having material removed from what will ultimately be the thinner gate spacer during the directional spacer etch processing used to form the asymmetric gate spacers, and vice versa, where a slanted thinner gate spacer with relatively less slope away from exactly vertical would be less susceptible to having material removed from what will ultimately be the thinner gate spacer during the directional spacer etch processing used to form the asymmetric gate spacers. Thus, in some such embodiments, adjusting the slope influences the final thickness of that slanted thinner gate spacer.

Note that, as used herein, the expression "X includes at least one of A and B" refers to an X that may include, for example, just A only, just B only, or both A and B. To this end, an X that includes at least one of A and B is not to be understood as an X that requires each of A and B, unless expressly so stated. For instance, the expression "X includes A and B" refers to an X that expressly includes both A and B. Moreover, this is true for any number of items greater than two, where "at least one of those items is included in X. For example, as used herein, the expression "X includes at least one of A, B, and C" refers to an X that may include just A only, just B only, just C only, only A and B (and not C), only A and C (and not B), only B and C (and not A), or each of A, B, and C. This is true even if any of A, B, or C happens to include multiple types or variations. To this end, an X that includes at least one of A, B, and C is not to be understood as an X that requires each of A, B, and C, unless expressly so stated. For instance, the expression "X includes A, B, and C" refers to an X that expressly includes each of A, B, and C.

As can be understood based on this disclosure, the techniques can be implemented for transistors including group IV semiconductor material, group III-V semiconductor material, and/or any other suitable semiconductor material. The use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and so forth. The use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and so forth. Note that group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, and group V may also be known as the nitrogen family or IUPAC group 15, for example. For instance, in some embodiments, the techniques can be used to benefit transistors including channel material that includes at least one of silicon (Si), germanium (Ge), tin (Sn), indium (In), gallium (Ga), arsenic (As), phosphorous (P), and aluminum (Al), to provide some examples.

In some embodiments, the techniques described herein can be used to benefit n-channel devices (e.g., n-MOS) and/or p-channel devices (e.g., p-MOS). Further, in some embodiments, the techniques described herein can be used to benefit MOSFET devices, tunnel FET (TFET) devices, Fermi filter FET (FFFET) devices, and/or any other suitable devices as will be apparent in light of this disclosure. Further still, in some embodiments, the techniques described herein can be used to form complementary transistor circuits (such as CMOS circuits), where the techniques can be used to benefit one or more of the included n-channel and p-channel transistors making up the CMOS circuit. Further yet, in some embodiments, the techniques described herein can be used to benefit a multitude of transistor configurations, such as planar and non-planar configurations, where the non-planar configurations may include finned or FinFET configurations (e.g., dual-gate or tri-gate), gate-all-around (GAA) configurations (e.g., nanowire or nanoribbon), or some combination thereof (e.g., beaded-fin configurations), to provide a few examples. In some embodiments, the techniques may be used to benefit one or more transistors included in a source amplifier circuit. Therefore, the techniques for forming transistors employing non-selectively deposited S/D material can benefit a multitude of transistor devices and circuits, as will be apparent in light of this disclosure.

Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction ( BD or BED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate an integrated circuit (IC) including at least one transistor that includes asymmetric gate spacers, where the gate spacers are asymmetric with respect to at least one of dimensions (e.g., based on their relative horizontal widths or thicknesses as described herein) and shape (e.g., where one is substantially vertical and straight while the other is slanted and/or curved, at least in part). For instance, such asymmetric gate spacers can be detected by observing a cross-sectional view along the channel of the transistor via electron microscopy (e.g., SEM/TEM) in structures employing the techniques described herein. In some embodiments, the techniques and structures described herein may be detected based on the benefits derived therefrom, such as the relatively increased performance derived from the relative decrease in gate-drain overlap (and thus the decrease in the related capacitance) and/or the relative increase in gate-source overlap, for example. Further, in some embodiments, the techniques described herein may enable forming enhanced performance transistor devices with sub-50 nm gate lengths (or gate lengths below some other suitable threshold as will be apparent in light of this disclosure), which can also be detected and measured. Numerous configurations and variations will be apparent in light of this disclosure.

Architecture and Methodology

Figure 1 illustrates method 100 of forming an integrated circuit (IC) including one or more transistors that include asymmetric gate spacers, in accordance with some embodiments of the present disclosure. Figures 2A-D illustrate example IC structures that are formed when carrying out optional box 102 of method 100 of Figure 1, in accordance with some embodiments. Figures 3A-L illustrate example IC structures that are formed when carrying out boxes 104-124 of method 100 of Figure 1, in accordance with some embodiments. Figure 4 illustrates an example transistor structure including the asymmetric gate spacers from rectangular dashed portion A-A in Figure 3L, formed when carrying out boxes 126-130 of method 100 of Figure 1, in accordance with some embodiments. Figure 4' illustrates the example transistor structure of Figure 4 with a curved thinner gate spacer (as compared to the slanted thinner gate spacer in the structure of Figure 4), formed in accordance with some embodiments. Figure 5 illustrates an example IC structure illustrating various different non-planar transistors including asymmetric gate spacers, in accordance with some embodiments. Note that method 100 includes a primary path that illustrates a gate last transistor fabrication process flow (e.g., a replacement gate or replacement metal gate (RMG) process flow), which is utilized in some embodiments. However, in other embodiments, a gate first process flow may be used, as will be described herein (and which is illustrated with the alternative gate first flow 100' indicator in Figure 1). Numerous variations and configurations will be apparent in light of this disclosure.

A multitude of different transistor devices can benefit from the techniques described herein, which includes, but is not limited to, various field-effect transistors (FETs), such as metal-oxide-semiconductor FETs (MOSFETs), tunnel FETs (TFETs), and Fermi filter FETs (FFFETs), to name a few examples. For example, the techniques may be used to benefit an n- channel MOSFET (n-MOS) device, which may include a source-channel-drain doping scheme of n-p-n or n-i-n, where 'n' indicates n-type doped semiconductor material, 'p' indicates p-type doped semiconductor material, and indicates intrinsic/undoped semiconductor material (which may also include nominally undoped semiconductor material, including dopant concentrations of less than 1E16 atoms per cubic centimeter (cm), for example), in accordance with some embodiments. In another example, the techniques may be used to benefit a p-channel MOSFET (p-MOS) device, which may include a source-channel-drain doping scheme of p-n-p or p-i-p, in accordance with some embodiments. In yet another example, the techniques may be used to benefit a TFET device, which may include a source-channel-drain doping scheme of p-i-n or n-i- p, in accordance with some embodiments. In still another example, the techniques may be used to benefit one or both of the S/D regions of a FFFET device, which may include a source - channel-drain doping scheme of np-i-p (or np-n-p) or pn-i-n (or pn-p-n), in accordance with some embodiments.

In addition, in some embodiments, the techniques may be used to benefit transistors including a multitude of configurations, such as planar and/or non-planar configurations, where the non-planar configurations may include finned or FinFET configurations (e.g., dual-gate or tri-gate), gate-all-around (GAA) configurations (e.g., nanowire or nanoribbon), or some combination thereof (e.g., a beaded-fin configurations), to provide a few examples. For instance, Figure 5 illustrates an example IC structure including transistors having finned and nanowire configurations, as will be described in more detail below. Further, the techniques may be used to benefit complementary transistor circuits, such as CMOS circuits, where the techniques may be used to benefit one or more of the included n-channel and/or p-channel transistors making up the CMOS circuit. Other example transistor devices that can benefit from the techniques described herein include few to single electron quantum transistor devices, in accordance with some embodiments. Further still, any such devices may employ semiconductor materials that are three-dimensional crystals as well as two dimensional crystals or nanotubes, for example. Further yet, the transistor-based device may be a source amplifier used In some embodiments, the In some embodiments, the techniques may be used to benefit devices of varying scales, such as IC devices having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).

Method 100 of Figure 1 includes optionally patterning 102 a substrate or channel material layer into fins and forming shallow trench isolation (STI) material between the fins to form the example resulting structure of Figure 2D, in accordance with some embodiments. Note that such processing 102 is optional, because it need not be performed for planar transistor configurations, in accordance with some embodiments. However, in embodiments where box 102 is performed, the processing includes patterning hardmask on a substrate or channel material layer, such as patterning hardmask 210 on substrate 200 to form the example resulting structure of Figure 2 A, in accordance with some embodiments. In some embodiments, hardmask 210 may be deposited or otherwise formed on substrate 200 using any suitable techniques as will be apparent in light of this disclosure. For example, hardmask 210 may be blanket deposited or otherwise grown on substrate 200 using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), spin-on processing, and/or any other suitable process. In some instances, the top surface of substrate 200 on which hardmask 210 is to be deposited may be treated (e.g., via chemical treatment, thermal treatment, etc.) prior to deposition of the hardmask 210 material. After being blanket formed on substrate 200, hardmask 210 may then be patterned using any suitable techniques, such as one or more lithography and etch processes, for example. Hardmask 210 may include any suitable material, such as oxide material, nitride material, dielectric material, and/or any other electrical insulator material, for example. Specific oxide and nitride materials may include silicon dioxide, titanium oxide, hafnium oxide, aluminum oxide, silicon nitride, and titanium nitride, just to name a few examples. In some cases, the material of hardmask 210 may be selected based on the material of substrate 200, for example.

Substrate 200, in some embodiments, may include: a bulk substrate including group IV semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and/or group III-V material and/or any other suitable semiconductor material(s) as will be apparent in light of this disclosure; an X on insulator (XOI) structure where X is one of the aforementioned semiconductor materials (e.g., group IV and/or group III-V semiconductor material) and the insulator material is an oxide material or some other dielectric/electric insulator material; or some other suitable multilayer structure where the top layer includes one of the aforementioned semiconductor materials (e.g., group IV and/or group III-V semiconductor material). Recall that the use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and so forth. Also recall that the use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and so forth. Note that group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, and group V may also be known as the nitrogen family or IUPAC group 15, for example. In some embodiments, substrate 200 may be doped with any suitable n-type and/or p-type dopant. For instance, in the case, of a Si substrate, the Si may be p-type doped using a suitable acceptor (e.g., boron) or n-type doped using a suitable donor (e.g., phosphorous, arsenic), to provide some example cases. However, in some embodiments, substrate 200 may be undoped/intrinsic or relatively minimally doped (such as including a dopant concentration of less than 1E16 atoms per cubic centimeter (cm)), for example. In some embodiments, substrate 200 may include a surface crystalline orientation described by a Miller index of (100), (110), or (111), or its equivalents, as will be apparent in light of this disclosure. Although substrate 200, in this example embodiment, is shown as having a thickness (dimension in the Y-axis direction) similar to other layers shown in subsequent structures for ease of illustration, in some instances, substrate 200 may be relatively much thicker than the other layers, such as having a thickness in the range of 50 to 950 microns, for example, or any other suitable thickness as will be apparent in light of this disclosure. In some embodiments, substrate 200 may be used for one or more other IC devices, such as various diodes (e.g., light-emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC devices, depending on the end use or target application. Accordingly, in some embodiments, the structures described herein may be included in a system-on-chip (SoC) application, as will be apparent in light of this disclosure.

Optional processing 102 of method 100 continues with performing shallow trench recess (STR) etch to form fins 202 from substrate 200, thereby forming the resulting example structure shown in Figure 2B, in accordance with some embodiments. In some embodiments, the STR etch used to form trenches 215 and fins 202 may include any suitable techniques, such as various masking processes and wet and/or dry etching processes, for example. In some cases, the STR etch may be performed in- situ/without air break, while in other cases, STR etch may be performed ex-situ, for example. This is generally true for all etch processing described herein. Trenches 215 may be formed with varying widths (dimension in the X-axis direction) and depths (dimension in the Y-axis direction) as can be understood based on this disclosure. For example, multiple hardmask patterning and STR etching processes may be performed to achieve varying depths in the trenches 215 between fins 202. Fins 202 may be formed to have varying widths Fw (dimension in the X-axis direction) and/or heights Fh (dimension in the Y-axis direction). Note that although hardmask structures 210 are still present in the example structure of Figure 2B, in some cases, that need not be the case, as they may have been consumed during the STR etch, for example.

In some embodiments, the fin widths Fw (dimension in the horizontal or X-axis direction) may be in the range of 2-400 nm (or in a subrange of 2-10, 2-20, 2-50, 2-100, 2-200, 4-10, 4-20, 4-50, 4-100, 4-200, 4-400, 10-20, 10-50, 10-100, 10-200, 10-400, 50-100, 50-200, 50-400, or 100-400 nm), for example, or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the fin heights Fh (dimension in the vertical or Y-axis direction) may be in the range of 4-800 nm (or in a subrange of 4-10, 4-20, 4-50, 4-100, 4-200, 4-400, 10-20, 10-50, 10-100, 10-200, 10-400, 10-800, 50-100, 50-200, 50-400, 50-800, 100-400, 100-800, or 400-800 nm), for example, or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the fin heights Fh may be at least 25, 50, 75, 100, 125, 150, 175, 200, 300, 400, or 500, 600, 700, or 800 nm tall, or greater than any other suitable threshold height as will be apparent in light of this disclosure. In some embodiments, the height to width ratio of the fins (Fh:Fw) may be greater than 1 , such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, or 10, or greater than any other suitable threshold ratio, as will be apparent in light of this disclosure. Note that the trenches 215 and fins 202 are each shown as having essentially the same sizes and shapes in this example structure for ease of illustration; however, the present disclosure is not intended to be so limited. For example, in some embodiments, the fins 202 may be formed to have varying heights Fh, varying widths Fw, varying starting points (or varying starting heights), varying shapes, and/or any other suitable variations as will be apparent in light of this disclosure. Moreover, trenches 215 may be formed to have varying depths, varying widths, varying starting points (or varying starting depths), varying shapes, and/or any other suitable variations as will be apparent in light of this disclosure. Further note that although four fins 202 are shown in the example structure of Figure 2B for ease of illustration, any number of fins may be formed, such as one, two, three, five, ten, hundreds, thousands, millions, billions, and so forth, as can be understood based on this disclosure.

Optional processing 102 of method 100 continues with depositing shallow trench isolation (STI) material 220 and planarizing/polishing the structure to form the example resulting structure of Figure 2C, in accordance with some embodiments. In some embodiments, deposition 106 of STI material 220 may include any suitable deposition techniques, such as those described herein (e.g., CVD, ALD, PVD), or any other suitable deposition process. In some embodiments, STI material 220 (which may be referred to as an STI layer) may include any suitable electrical insulator material, such as one or more dielectric, oxide (e.g., silicon dioxide), and/or nitride (e.g., silicon nitride) materials. In some embodiments, the material of STI layer 220 may be selected based on the material of substrate 200. For instance, in the case of a Si substrate, the STI material may be selected from silicon dioxide or silicon nitride, to provide some examples. In some embodiments, the planarizing and/or polishing process(es) performed after forming STI material 220 may include any suitable techniques, such as chemical-mechanical planarization/polishing (CMP) processes, for example.

In embodiments where the fins are to be removed and replaced with replacement semiconductor material (e.g., to be used in the channel region of one or more transistor devices), the structure of Figure 2C enables such processing. For example, continuing from the structure of Figure 2C, fins 202 may be recessed or removed using selective etch processing (e.g., for a given etchant, the semiconductor material of fins 202 is removed selective to the insulator material of STI layer 220) to form fin-shaped trenches between STI material 220 in which replacement semiconductor material can be deposited/grown (e.g., using any suitable techniques, such as CVD, metal-organic CVD (MOCVD), ALD, molecular beam epitaxy (MBE), PVD). For instance, Figure 2C is a blown-out portion of Figure 2C illustrating alternative recess and replace processing to form a replacement material fin, in accordance with some embodiments. In Figure 2C, replacement fin 202' was formed, and the replacement fin 202' (and generally, any replacement fin formed) may include any suitable semiconductor material (e.g., group IV and/or III-V semiconductor material). For instance, replacement fins including SiGe or Ge may be formed by removing native Si fins during such processing and replacing them with the SiGe or Ge material, to provide some examples. In addition, replacement fin 202' may include any suitable n-type or p-type dopant. In some embodiments, replacement material fins, such as replacement fin 202' of Figure 2C may be formed using alternative processing. For instance, in some embodiments, replacement material fins may be formed by blanket-growing the replacement material on the substrate (e.g., using epitaxial deposition processing) and then patterning the replacement material into replacement material fins, to provide an example alternative. Such an example alternative process may also include forming STI material between the replacement material fins to form a structure similar to that shown in Figure 2D', for instance. Note that replacement fin 202' is illustrated with patterning/shading to merely assist with visually identifying that feature; however, the patterning/shading is not intended to limit the present disclosure in any manner.

Note that only one fin is shown being replaced in the example embodiment of Figure 2C; however, the present disclosure is not intended to be so limited. In some embodiments, all of the native fins 202 may be replaced or only a subset may be replaced (e.g., such that some replacement fins are available for subsequent processing and some native fins 202 remain for subsequent processing). Further, in some embodiments, the recess and replace process may be performed as many times as desired to form as many subsets of replacement fins as desired by masking off the areas not to be processes for each replacement fin subset processing. In some such embodiments, a first subset of replacement fins may be formed for n-channel transistors (e.g., where the first replacement material is selected to increase electron mobility) and a second subset of replacement fins may be formed for p-channel transistors (e.g., where the second replacement material is selected to increase hole mobility). Further still, in some embodiments, a multilayer replacement fin may be formed to enable the subsequent formation of nanowires or nanoribbons in the channel region of one or more transistors, where some of the layers in the multilayer replacement fin are sacrificial and intended to be removed via selective etching (e.g., during replacement gate processing), which will be described in more detail herein. Further note that the recess process used to form replacement fin 202' included recessing native fin 202 (i.e., native to substrate 200) to a depth as shown, such that a portion of that native fin 202 remains, which is referred to as sub-fin portion 203 (indicated in Figure 2C). However, in other embodiments, the recess process may completely remove a given native fin 202 or recess the given native fin 202 to a different depth (e.g., a different point in the vertical or Y-axis direction).

In embodiments employing an aspect ratio trapping (ART) integration scheme, fins 202 may be formed to have particular height to width ratios such that if they are later removed or recessed (e.g., to form replacement fins 202' in Figure 2C), the resulting fin-shaped trenches formed allow for defects in the replacement material deposited to terminate on a side surface as the material grows vertically, such as non-cry stalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects, if such an ART scheme is used. As can be understood in some such embodiments, the channel region material need not be native to substrate 200 (as will be described in more detail with reference to Figure 5). In some such embodiments employing an ART scheme, the fins may be formed to have particular height to width ratios (e.g., at least 2-5) such that when they are later recessed and/or removed, the resulting fin trenches formed allow for defects in the replacement material deposited to terminate on a side surface as the material grows vertically, such as non- crystalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects.

Generally, in a trench fill integration scheme, the fins may be formed to have particular height to width ratios (e.g., at least 2-5) such that when they are later removed or recessed, the resulting trenches formed allow the replacement material deposited to grow vertically from the native substrate bottom and be confined by non-crystalline/dielectric sidewalls. The material used to fill these trenches may be sufficiently lattice matched to the substrate (or to a buffer layer used between the substrate and replacement material) such that effectively no relaxation or threading misfit dislocation formation occurs (e.g., the misfit dislocations occur at levels below 1E5 dislocations per square cm). For instance, this lattice match condition is true for native Si fins and trench fill of SiGe replacement material having Ge concentration (by atomic percentage) of less than 45% and fin heights Fh of less than 50 nm, to provide an example. Alternatively, using the Si substrate example (where the native Si fins are recessed to form trenches), a replacement material trench fill of Ge, SiGe with Ge concentration of at least 80%, or GaAs can be performed such that the dislocations form right at the native/replacement material interface and again effectively no threading misfit dislocation formation occurs at the top surface of the replacement material fin (e.g., the misfit dislocations occur at levels below 1E5 dislocations per square cm).

Optional processing 102 of method 100 continues with recessing the STI material 220 to cause at least a portion 204 of fins 202 to exude from the STI plane, thereby forming the resulting example structure shown in Figure 2D, in accordance with some embodiments. In some embodiments, recessing 112 may be performed using any suitable techniques, such as using one or more wet and/or dry etch processes that allow the STI material 220 to be selectively recessed relative to the material of fin 202, and/or any other suitable processing as will be apparent in light of this disclosure. As can be understood based on this disclosure, fin portions 204 may be used in the active channel region of one or more transistors, such that fin portions 204 (the portions of fins 202 above the top plane of STI layer 220) may be referred to as active fin portions herein, for example. Moreover, the remaining portions of fins 202 below the top plane of STI layer 220 are indicated as portions 203, where such portions may be referred to as sub-fin or sub-channel portions, for example.

As shown in Figure 2D, the portions 204 of fins 202 exuding above the top plane of STI layer 220 have an active fin height indicated as Fah, which may be in the range of 4-800 nm (e.g., in the subrange of 4-10, 4-20, 4-50, 4-100, 4-200, 4-400, 10-20, 10-50, 10-100, 10-200, 10- 400, 10-800, 50-100, 50-200, 50-400, 50-800, 100-400, 100-800, or 400-800 nm), for example, or any other suitable value or range, as will be apparent in light of this disclosure. In some embodiments, the active fin heights Fah may be at least 25, 50, 75, 100, 125, 150, 175, 200, 300, 400, 500, 600, 700, or 800 nm tall, or greater than any other suitable threshold height as will be apparent in light of this disclosure. In addition, Figure 2D' is a blown-out portion of Figure 2D illustrating the replacement fin 202' from Figure 2C after the STI material has been recessed, in accordance with some embodiments. Note that in other embodiments, replacement fins 202' may also be formed by blanket depositing the replacement material and forming the replacement material into fins, followed by STI processing, as can be understood based on this disclosure. Also note that in embodiments employing planar transistor configurations, recess process 108 need not be performed, as the transistor may be formed using the top surface of fin 202 from Figure 2C.

Method 100 of Figure 1 continues with forming 104 the dummy (or final) gate stack layers 232/234 above the substrate 200 and forming 106 hardmask layer 236 on the dummy gate stack layers, thereby forming the resulting example structure of Figure 3 A, in accordance with some embodiments. Note that Figures 3A-L illustrate forming a gate stack including asymmetric spacers and for ease of illustration, that gate stack is formed above and on substrate 200. However, in other embodiments, the gate stack may be formed above and on the structure of Figure 2D, where substrate 200 may instead be a cross-sectional view along one of fins 204, for example. Further note that in still other embodiments, the gate stack may be formed above and on the structure of Figure 2D', where substrate 200 may instead by a cross-sectional view along replacement fin 202', for example. As can be understood based on this disclosure, in such embodiments where the gate stack is formed on a finned structure, the gate stack may wrap around three sides of that finned structure to form a transistor including a tri-gate configuration. Variations such as forming nanowire configuration transistors, where the gate stack wraps around each nanowire will be described in more detail herein. Therefore, the techniques described with respect to Figures 3A-L may be performed for planar or non-planar transistor configurations. Regardless, in any such embodiments, the gate stack including asymmetric spacers is formed above substrate 200, as can be understood based on this disclosure.

Recall that method 100 is primarily described herein in the context of a gate last transistor fabrication process flow, where the processing includes forming a dummy gate stack, performing the S/D processing, and then forming the final gate stack after the S/D regions have been processed. However, in other embodiments, a gate first transistor fabrication process flow may be employed, where forming 104 the gate stack layers includes forming the layers of the final gate stack, such that they are not later removed and replaced (in contrast to gate last or replacement gate process flows). In such embodiments case, process 128 (performing final gate stack processing) would not be performed, as the final gate stack layers would be instead formed at box 104. Thus, process 128 is optional in some embodiments (such as those employing the gate first process flow). This is reflected with the alternative location for box 128 in Figure 1, which is shown as the optional gate first flow 100', where performing 128 the final gate stack processing would not occur at its shown location, as the final gate stack layers would be formed during process 104 instead. However, the description of method 100 will continue using a gate last process flow, to allow for such a flow (which generally includes additional processing) to be adequately described. As can be understood based on this disclosure, the dummy gate stack (and gate spacers) help define the channel region and source/drain (S/D) regions for a given transistor, where the channel region is below the dummy gate stack (as it will be located below the final gate stack), and the S/D regions are on either side of and adjacent to the channel region.

Continuing with forming 104 the dummy gate stack, such a dummy gate stack (where employed) may include dummy gate dielectric 232 and dummy gate electrode 234, where such features are formed in this example embodiment by depositing them as layers as shown in Figure 3A. Dummy gate dielectric 232 (e.g., dummy oxide material) and dummy gate electrode 234 (e.g., dummy poly-silicon material) may be used for a replacement gate process, as can be understood based on this disclosure. In some embodiments, dummy gate dielectric 232 may be formed to have any suitable thickness (dimension in the vertical or Y-axis direction), such as a thickness in the range of 1-50 nm or greater, for example. In some embodiments, dummy gate electrode 234 may be formed to have any suitable thickness (dimension in the vertical or Y-axis direction), such as a thickness in the range of 10-500 nm or greater, for example. The dummy gate stack layers 232/234 may be formed using any suitable techniques, such as blanket depositing the layers in one or more target areas above substrate 200 using any suitable processes (e.g., CVD, PVD, ALD). In some embodiments, additional or alternative layers may be formed in the dummy gate stack, and thus, the dummy gate stack is not intended to be limited specifically to the two layers 232 and 234 shown in Figure 3A, unless otherwise stated. Note that in some embodiments, as previously described, the techniques described herein need not include forming a dummy gate stack, such that a final gate stack may be formed in the first instance. Regardless, with either a gate last or a gate first process flow, the end gate structure will include the final gate stack which is described in more detail below, as will be apparent in light of this disclosure.

Hardmask 236 is formed 106 on the dummy gate stack layers as is also shown in the example embodiment of Figure 3 A. For example, hardmask 236 may be blanket deposited or otherwise grown on dummy gate electrode 234 using any suitable processing (e.g., CVD, ALD, PVD, spin-on processing). Hardmask 236 may include any suitable material, such as oxide material, nitride material, dielectric material, and/or any other electrical insulator material, for example. Specific oxide and nitride materials may include silicon dioxide, titanium oxide, hafnium oxide, aluminum oxide, silicon nitride, and titanium nitride, just to name a few examples. In some embodiments, hardmask layer 236 may be formed to have any suitable thickness (dimension in the vertical or Y-axis direction), such as a thickness in the range of 5- 200 nm (e.g., 25-100 nm) or greater, for example.

Method 100 of Figure 1 continues with patterning 108 backbone structures 240 on hardmask layer 236 to form the example resulting structure of Figure 3B, in accordance with some embodiments. In some embodiments, patterning 108 may include depositing a layer of backbone 240 material (e.g., via CVD, PVD, ALD, spin-on processing) and then using one or more lithography and etch processes to form the backbone structures 240 shown in Figure 3B. In some embodiments, backbone structures 240 may include any suitable material, such as polycrystalline or amorphous semiconductor material (e.g., amorphous silicon), to provide some examples. In some embodiments, backbone structures 240 may be formed to have any suitable thickness (dimension in the vertical or Y-axis direction), such as a thickness in the range of 5- 500 nm (e.g., 50-150 nm) or greater, for example.

Method 100 of Figure 1 continues with depositing and spacerizing 110 first sacrificial spacer material 241 to form the example resulting structure of Figure 3D, in accordance with some embodiments. In some embodiments, depositing the first sacrificial spacer material 241 can be performed using any suitable techniques (e.g., CVD, PVD, ALD, spin-on processing) to form the example structure of Figure 3C. Note that in this example embodiment, the deposition results in a conformal formation of the first sacrificial spacer material 241 layer, where such a conformal formation or growth tracks the topology of the exposed surfaces of the structure on which it is formed (e.g., of the structure of Figure 3B). After depositing the first sacrificial spacer material 241, it can then be spacerized or turned into spacer structures (generally, structures that are adjacent to one or more sides of an already formed feature), thereby forming the resulting structure of Figure 3D, for example. In some embodiments, the spacerize processing may include any suitable etch techniques, such as one or more dry etches, where such dry etch processing generally etches directionally or anisotropically, for example. However, one or more wet etch processes may alternatively or additionally be used, and in such cases, the wet etch processes may or may not be directional/anisotropic (e.g., they could be isotropic to etch from all angles, if so desired). In this example embodiment, anisotropic dry etch processing was performed to remove the first sacrificial spacer material 241 in a top-down approach, such that the vertically thinner portions of the material can be completely (or almost completely) removed while retaining the vertically thicker portions on either side of backbone structures 241, as shown in Figure 3D. In some embodiments, first sacrificial spacer material 241 may include any suitable material, such as oxide material (e.g., silicon dioxide), nitride material (e.g., silicon nitride), dielectric material, and/or any other electrical insulator material, for example. In some embodiments, the first sacrificial spacer material structures 241 of Figure 3D may be formed to have any suitable height (dimension in the vertical or Y-axis direction), such as a height in the range of 5-500 nm (e.g., 15-100 nm) or greater, for example.

Method 100 of Figure 1 continues with depositing 112 second sacrificial spacer material

242 to form the example resulting structure of Figure 3E, in accordance with some embodiments. In some embodiments, depositing the second sacrificial spacer material 242 can be performed using any suitable techniques (e.g., CVD, PVD, ALD, spin-on processing) to form the example structure of Figure 3E. Note that in this example embodiment, the deposition results in a conformal formation of the second sacrificial spacer material 242 layer, where such a conformal formation or growth tracks the topology of the exposed surfaces of the structure on which it is formed (e.g., of the structure of Figure 3D). In some embodiments, second sacrificial spacer material 242 may include any suitable material, such as oxide material (e.g., silicon dioxide), nitride material (e.g., silicon nitride), dielectric material, and/or any other electrical insulator material, for example.

In some embodiments, second sacrificial spacer material 242 may be selected such that it can be selectively etched relative to the material of first sacrificial spacer material 241, such as being able to etch the second sacrificial spacer material 242 at a relatively faster rate than the first sacrificial spacer material 241 for a given etchant (e.g., at least 1.1, 1.2, 1.3, 1.4, 1.5, 2, 3, 4, 5, 10, 50, or 100 times faster) or being able to etch the second sacrificial spacer material 242 without significantly removing the first sacrificial spacer material 241 for a given etchant. For instance, first sacrificial spacer material 241 may be selected to be silicon dioxide and second sacrificial spacer material 242 may be selected to be silicon nitride, as silicon nitride can be selectively etched relative to silicon dioxide using a given etchant, as is known in the art, to provide an example combination of materials. In another example embodiment, first sacrificial spacer material 241 and second sacrificial spacer material 242 may both include silicon dioxide, but the silicon dioxide of second sacrificial spacer material 242 may be formed to affect its selectivity during the etching of the hardmask 236 and gate stack 232/234 layers, such as by adjusting the oxygen, carbon, and/or hydrogen component during the deposition of the silicon dioxide included in the second sacrificial spacer material 242 and/or by adjusting the precursor as is known in the art to affect the selectivity. In addition, the second sacrificial spacer material 242 may be selected/formed to have lower selectivity to etch processing used to remove the material of hardmask layer 236 and dummy gate stack layers 232/234 to form a slanted or curved profile for such features 232/234/236, as will be described in more detail below. Also note that the processing will be shown continuing from the structure of Figure 3E for both a symmetric gate spacer scheme 301 and an asymmetric gate spacer scheme 302, to illustrate techniques for simultaneously and monolithically forming transistors including symmetric gate spacers and asymmetric gate spacers. However, in other embodiments, transistors including symmetric gate spacers may be monolithically co-integrated with transistors including asymmetric gate spacers (formed using the techniques described herein) without simultaneously forming such transistors including symmetric gate spacers. Also, in still other embodiments, transistors including symmetric gate spacers need not be monolithically co- integrated at all with transistors including asymmetric gate spacers as described herein, such that a single IC may only include transistors including asymmetric gate spacers. Recall that a symmetric gate spacer set on either side of a given gate stack includes substantially similar relative thicknesses or horizontal widths, whereas an asymmetric gate spacer set on either side of a given gate stack includes a relatively wider spacer and a relatively narrower spacer, with respect to horizontal width.

Method 100 of Figure 1 continues with optionally removing 114 the second sacrificial spacer material 241 where desired, such as over areas where substantially symmetric gate spacer sets are to be formed, thereby forming the resulting structure of Figure 3F, in accordance with some embodiments. Process 114 is optional, because substantially symmetric gate spacers need not be formed using the techniques described herein (and as described in the preceding paragraph). However, in embodiments where substantially symmetric gate spacer sets are to be monolithically and simultaneously formed with asymmetric gate spacer sets, the techniques can either include process 114, only forming the second sacrificial spacer material 241 in the first instance in areas where asymmetric gate spacer sets are to be formed, or removal of the second sacrificial spacer material 241 after spacerizing the second sacrificial spacer material 241 into spacer structures (such as those shown in Figure 3G). Continuing with this example embodiment, the second sacrificial spacer material 242 may be removed via any suitable techniques, such as masking off the areas to be kept and etching (e.g., via wet and/or dry etch processing) the second sacrificial spacer material 241 from the areas where it is desired to be removed, for example. For instance, in the example structure of Figure 3F, the second sacrificial spacer material 242 was removed from the left side of the structure (indicated as symmetric gate spacer scheme 301) and retained on the right side of the structure (indicated as asymmetric gate spacer scheme 302).

Method 100 of Figure 1 continues with spacerizing 116 second sacrificial spacer material 241 to form the example resulting structure of Figure 3G, in accordance with some embodiments. In some such embodiments, the spacerize processing 116 may include any suitable etch techniques, such as one or more dry etches, where such dry etch processing generally etches directionally or anisotropically, for example. However, one or more wet etch processes may alternatively or additionally be used, and in such cases, the wet etch processes may or may not be directional/anisotropic (e.g., they could be isotropic to etch from all angles, if so desired). In this example embodiment, anisotropic dry etch processing was performed to remove the second sacrificial spacer material 242 in a top-down approach, such that the vertically thinner portions of the material can be completely (or almost completely) removed while retaining the vertically thicker portions on either side of the right backbone structure 241, and on the outside of those related first sacrificial spacer structures 241, as shown in Figure 3G. In some embodiments, the second sacrificial spacer material structures 242 of Figure 3G may be formed to have any suitable height (dimension in the vertical or Y-axis direction), such as a height in the range of 5-500 nm (e.g., 15-100 nm) or greater, for example. Note that the difference between the left side of the structure in Figure 3G that is being used to form substantially symmetric gate spacer sets 301 and the right side of the structure in Figure 3G that is being used to form substantially asymmetric gate spacer sets 302 is the presence of second sacrificial spacer material structures 242 being present in the latter and not the former, as those second sacrificial spacer material structures 242 are used to form the asymmetric gate spacer sets, as will be apparent in light of this disclosure.

Method 100 of Figure 1 continues with selectively etching 118 the backbone structures 240 to remove them, thereby forming the example resulting structure of Figure 3H, in accordance with some embodiments. In some such embodiments, the selective etch processing 118 may include any suitable techniques, such as one or more wet and/or dry etch processes, where the material of backbone structures 240 is removed relatively faster than and/or without significantly removing other exposed material. For instance, such selective etch processing may include a given etchant that removes the material of backbone structures 240, which may be, e.g., amorphous silicon, relatively faster than (or without even significantly removing) the exposed insulator material of hardmask layer 236, first sacrificial spacer material 241, and second sacrificial spacer material 242. Note that the final gate length for each gate structure is defined by the total horizontal thickness or width (dimension in the Z-axis direction) of each remaining corresponding separated spacer structure (whether it be the two spacer structures on the left that only include first sacrificial spacer material 241 or the two spacer structures on the right that include both first and second sacrificial spacer material 241 and 242), as will be apparent in light of this disclosure. Also note that four different gate structures will be formed from the four separated spacer structures shown in Figure 3H.

Method 100 of Figure 1 continues with selectively etching 120 the hardmask layer 236, dummy gate stack layers 232/234, and second sacrificial spacer material structures 242 (e.g., selective relative to the first sacrificial spacer material structures 241) to form the example resulting structure of Figure 31, in accordance with some embodiments. In some such embodiments, the selective etch processing 120 may include any suitable techniques, such as one or more wet and/or dry etch processes, where, for a given etchant, the material of hardmask layer 236 and dummy gate stack layers 232/234 is removed at least at a first rate, the second sacrificial spacer material structures 242 are removed at a second rate, and the first sacrificial spacer material structures 241 are removed at a third rate (or not significantly removed at all), such that the first rate is faster than the second rate and the second rate is faster than the third rate. In other words, the second sacrificial spacer material 242 will be consumed slower relative to the consumption of the material of hardmask layer 236 and dummy gate stack layers 232/234 (and the first sacrificial spacer material 241 is consumed slower or not at all relative to all of the aforementioned material features). The slowly receding second sacrificial spacer material 242 during selective etch processing 120 results in the slanted profile of the dummy gate stack 232/234 and hardmask 236 layers as shown in Figure 31 below the locations where second sacrificial spacer material 242 was present. Otherwise, a substantially or exactly vertical profile is formed on the sides of each gate stack below second sacrificial spacer material 242 was not present to cause such a slanted profile. For instance looking at the gate stack structure that is second from the right, the left side of that gate stack structure includes a slanted profile 238 as it had second sacrificial spacer material 242 above it prior to selective etch processing 120, which resulted in the formation of that slanted profile 238 on only one side of the gate stack, with the other side including a substantially vertical and straight profile 239 as shown (due to the second sacrificial spacer material 242 not being present above the side including vertical profile 239). As will be apparent in light of this disclosure, the different sidewall profiles (such as 238 versus 239) enables the formation of a given asymmetric gate spacer set.

Method 100 of Figure 1 continues with selectively etching 122 the first sacrificial spacer material structures 241 to remove them, thereby forming the example resulting structure of Figure 3 J, in accordance with some embodiments. In some such embodiments, the selective etch processing 118 may include any suitable techniques, such as one or more wet and/or dry etch processes, where the material of first sacrificial spacer material structures 241 is removed relatively faster than and/or without significantly removing other exposed material. For instance, such selective etch processing may include a given etchant that removes the material of first sacrificial spacer material structures 241, which may be, e.g., silicon dioxide, relatively faster than (or without even significantly removing) the exposed material of hardmask layer 236, dummy gate layers 232/234, and substrate 200.

Method 100 of Figure 1 continues with depositing and spacerizing 124 the gate spacer material 250 to form the example resulting structure of Figure 3L, in accordance with some embodiments. In some embodiments, depositing the gate spacer material 250 can be performed using any suitable techniques (e.g., CVD, PVD, ALD, spin-on processing) to form the example structure of Figure 3K. Note that in this example embodiment, the deposition results in a conformal formation of the gate spacer material 250 layer, where such a conformal formation or growth tracks the topology of the exposed surfaces of the structure on which it is formed (e.g., of the structure of Figure 3J). After depositing the gate spacer material 250, it can then be spacerized or turned into gate spacer structures, thereby forming the resulting structure of Figure 3L, for example. In some embodiments, the spacerize processing may include any suitable etch techniques, such as one or more dry etches, where such dry etch processing generally etches directionally or anisotropically, for example. However, one or more wet etch processes may alternatively or additionally be used, and in such cases, the wet etch processes may or may not be directional/anisotropic (e.g., they could be isotropic to etch from all angles, if so desired).

In this example embodiment, anisotropic dry etch processing was performed to remove the gate spacer material 250 in a top-down approach, such that the gate spacer material 250 may be completely (or almost completely) removed from horizontal surfaces but retained on vertical surfaces. Thus, for the vertical surfaces, such as the vertical sidewall 239 indicated in Figure 31, the gate spacer material 250 may completely (or almost completely) remain after the spacerize etch processing, such as is shown in Figure 3L, where the thicker gate spacer structures 252 are indicated. For the surface of the slanted sidewall 238 of the right-most two gate structures, the gate spacer material 250 is retained, but it is also remove in part by the spacerize etch processing as the slanted profile exposes the gate spacer material 250 to the top-down etching, thereby forming relatively thinner gate spacer structures 251 as shown (relatively thinner than thicker gate spacer structures 252). In some embodiments, gate spacer material 250 may include any suitable material, such as oxide material (e.g., silicon dioxide), nitride material (e.g., silicon nitride), dielectric material, and/or any other electrical insulator material, for example.

As shown in Figure 3L, the width (dimension in the horizontal or Z-axis direction) of thicker gate spacer 252 is indicated as W2, which may also be expressed as the thickness of thicker gate spacer 252 between the gate stack and the corresponding drain contact (e.g., as shown in Figure 4). As is also shown in Figure 3L, the width (dimension in the horizontal or Z- axis direction) of thinner gate spacer 251 is indicated as Wl, which may also be expressed as the thickness of thinner gate spacer 251 between the gate stack and the corresponding source contact

(e.g., as shown in Figure 4). Note that widths W2 and Wl as used herein may refer to at least one of the maximum width(s) of the corresponding structure, the average width(s) of the corresponding structure, and the width(s) in a given horizontal plane, for example. For instance, in some cases, the maximum and average width of a given spacer structure may be the same, as it may have the same width throughout the entire structure, for example.

In some embodiments, W2 and Wl may be in the range of 1-200 nm (or in a subrange of 1-10, 1-25, 1-50, 1-100, 2-10, 2-25, 2-50, 2-100, 2-200, 5-10, 5-25, 5-50, 5-100, 5-200, 10-25, 10-50, 10-100, 10-200, 25-50, 25-100, 25-200, 50-100, 50-200, or 100-200 nm), or any other suitable value or range as can be understood based on this disclosure. In some embodiments, for a given asymmetric gate spacer set (including a relatively thicker gate spacer 252 and a relatively thinner gate spacer 251), W2 may be greater than Wl by 1-50 nm (or by a subrange of 1-2, 1-5, 1-10, 1-25, 2-5, 2-10, 2-25, 2-50, 5-10, 5-25, 5-50, 10-25, 10-50, or 25-50 nm), or any other suitable value or range as can be understood based on this disclosure. In some embodiments, for a given asymmetric gate spacer set, W2 may be greater than Wl by at least 1, 2, 3, 4, 5, 10, 15, 20, 25, or 50 nm, or any other suitable threshold value as can be understood based on this disclosure. In some embodiments, for a given asymmetric gate spacer set, the ratio of W2 to Wl (W2:W1) may be in the range of 1.1-3 (or in a subrange of 1.1-1.5, 1.1-2, 1.1-2.5, 1.2-1.5, 1.2-2, 1.2-2.5, 1.2-3, 1.5-2, 1.5-2.5, 1.5-3, 2-2.5, 2-3, or 2.5-3), or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, for a given asymmetric gate spacer set, the ratio of W2 to Wl (W2:W1) may be at least 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.25, 2.5, 2.75, 3, or any other suitable value or threshold value as can be understood based on this disclosure. Numerous relative relationships between the thicker gate spacer 252 and thinner gate spacer 251 of a given asymmetric gate spacer set will be apparent in light of this disclosure.

In some embodiments, a given thinner gate spacer 251 in an asymmetric gate spacer set may include a slanted or curved profile for at least a portion of the given gate spacer, such as a shape resembling a forward slash (e.g., /), a backward slash (e.g., \), a J-like shape (or an otherwise arc-like shape that is concave relative to the gate stack), a backward J-like shape, an arc-like shape that is convex relative to the gate stack, or any other suitable shape as will be apparent in light of this disclosure. For instance, the shape of thinner gate spacers 251 in Figure 3L (one of which is also shown in Figure 4) is slanted and resembles a slash (/ or \), whereas the shape of thinner gate spacer 25 Γ in Figure 4' is a curved and resembles a J-like shape. Note that the entirety of thinner gate spacer 251 is shown as slanted in Figures 3L and 4, however, the present disclosure is not intended to be so limited. In some embodiments, a given thinner gate spacer may include a combination of curved portions and (substantially) straight slanted portions, and may even include some (substantially) straight vertical portions (such as toward the top of the given thinner gate spacer). Thus, in some such embodiments, at least a portion of the thinner gate spacer may be referred to as slanted or substantially slanted, for example, and in some such embodiments, only a portion of the thinner gate spacer may be slanted (where the other portions may be vertically straight, such as being parallel with the thicker gate spacer).

In embodiments where a given thinner gate spacer 251 is slanted, at least a portion of the gate spacer may be sloped away from exactly vertical (e.g., as defined by the Y-axis in the figures, as defined by the main plane of the substrate being a horizontal plane such that a vertical line can be derived therefrom, and/or as defined by the gate stack being, at least, vertically above the channel) by 2-30 degrees (or an angle in a subrange of 2-5, 2-10, 2-15, 2-20, 2-25, 5-10, 5- 15, 5-20, 5-25, 5-30, 10-15, 10-20, 10-25, 10-30, 15-20, 15-25, 15-30, 20-25, 20-30, or 25-30 degrees), or any other suitable value or range as can be understood based on this disclosure. In some embodiments, at least a portion of a given slanted thinner gate spacer 251 may be sloped away from exactly vertical by at least 2, 5, 10, 15, 20, 25, or 30 degrees, or at least any other suitable threshold degree value as can be understood based on this disclosure. For instance, if exactly vertical is considered 90 degrees and a given slanted thinner gate spacer is sloped away from exactly vertical by at least 10 degrees, than the slope of that gate spacer would be less than 80 degrees or greater than 100 degrees, depending on which direction the slanted spacer slopes away from exactly vertical. Figure 3L illustrates this situation, as angle D is approximately 100 degrees, such that the corresponding thinner gate spacer 251 is sloped approximately 10 degrees from exactly vertical, while the other thinner gate spacer 251 (on the right-most gate stack) has an angle (as measured on the left side of that spacer) of approximately 80 degrees, which is also approximately 10 degrees from exactly vertical. In some embodiments, the aforementioned values, ranges, and thresholds for at least a portion of a slanted thinner gate spacer may be relative to a plane defined by the thicker gate spacer, for example.

In some embodiments, the profile of a given thinner gate spacer 251 may be based on the profile of the side of the gate stack on which it is formed (such as profile 238 shown in Figure 31), where the profile of that side of the gate stack may be based on the second sacrificial spacer material and the selective etch conditions used to remove that second sacrificial spacer material (e.g., during the selective etch processing used to form the individual gate stack structures from the gate stack layers, as previously described). Note that although the entirety of profile 238 is slanted, only a portion of the profile of that sidewall of the gate stack may be slanted in some embodiments, as can be understood based on this disclosure. The profile may also or alternatively be curved, at least in part (e.g., as shown in Figure 4' and described herein), such that there need not be any substantially straight slanted portions, in some embodiments. In addition, in some embodiments, a portion of the profile may be vertically straight and thus parallel (for that portion) to the profile 239 of the other sidewall of the gate stack.

In some embodiments, the slope of a slanted thinner gate spacer affects its final thickness, because a slanted thinner gate spacer with relatively greater slope away from exactly vertical would be more susceptible to having material removed from what will ultimately be the thinner gate spacer during the directional spacer etch processing used to form the asymmetric gate spacers, and vice versa, where a slanted thinner gate spacer with relatively less slope away from exactly vertical would be less susceptible to having material removed from what will ultimately be the thinner gate spacer during the directional spacer etch processing used to form the asymmetric gate spacers. Thus, in some such embodiments, adjusting the conditions related to a given second sacrificial spacer material structure 242 (e.g., the horizontal width of the structure, the etch selectivity of the structure, the selective etch conditions used to remove the structure) can impact the slope of the slanted sidewall of an underlying gate stack formed by the presence of the second sacrificial spacer material structure, which ultimately can influence the final thickness of the slanted gate spacer formed on that slanted sidewall. In such a manner, the techniques can achieve thicker and thinner gate spacers (relative to each other) from a single shared discrete layer (e.g., gate spacer material layer 250). Note that the gate side-wall spacers (such as gate spacers 251 and 252), referred to generally herein as gate spacers (or simply, spacers), can help determine the channel length and can also help with replacement gate processes, as will be apparent in light of this disclosure. Also note that gate spacers 251 and 252 are shown with shading in some of the figures merely for ease of their visual identification.

Method 100 of Figure 1 continues with performing 126 source and drain (S/D) region processing, optionally performing 128 gate stack processing, and performing 130 S/D contact processing to form one or more transistors, in accordance with some embodiments. For instance, Figure 4 illustrates the gate structure including asymmetric gate spacers in box A-A from Figure 3L, after the aforementioned processing has been performed, in accordance with some embodiments. In addition, Figure 5 illustrates the gate structure from Figure 4 including asymmetric gate spacers in the context of multiple non-planar transistor configurations, in accordance with some embodiments. All previous relevant description with respect to similarly numbered features is equally applicable to the structures of Figures 4 and 5. Performing 126 S/D processing, in this example embodiment, resulted in the formation of source region 261 and drain region 262 in Figures 4 and 5, where both regions may be referred to generally as S/D regions 261/262 herein for ease of description. In some embodiments, S/D processing 126 may include any suitable techniques, such as removing material of substrate 200 (or fins 204 or fins 202', where employed) in the S/D regions (regions adjacent to the dummy gate stack and spacers, which is ultimately regions adjacent the channel region) and replacing them with final S/D regions 261/262 by selectively depositing the final S/D material as desired. In embodiments where fins 204 or replacement fins 202' (from Figures 2D and 2D', respectively) are removed to expose sub-fin portions 230, the S/D regions may be selectively grown from the top surface of those semiconductor material sub-fin portions 230. Further, in some embodiments, depositing the final S/D material 261/262 may include any suitable techniques, such as one or more of the depositions processes described herein (e.g., CVD, ALD, PVD, MBE), and/or any other suitable processes as will be apparent in light of this disclosure.

In some embodiments, a given S/D region 261/262 may include any suitable semiconductor material as will be apparent in light of this disclosure, such as monocrystalline (or single-crystal) group IV and/or group III-V semiconductor material. For instance, a given S/D region 261/262 may include one of monocrystalline Si, SiGe, Ge, GaAs, InGaAs, AlGaAs, AlAs, InP, and so forth. In general, a given S/D region 261/262 may include at least one of silicon (Si), germanium (Ge), tin (Sn), indium (In), gallium (Ga), arsenic (As), phosphorous (P), and aluminum (Al), to provide some examples. In some embodiments, a given S/D region 261/262 may include n-type and/or p-type dopant (such as in one of the schemes described herein). Where present, the dopant may be included in a concentration in the range of 1E17 to 5E22 atoms per cubic cm or greater, for example. In some embodiments, a given S/D region 261/262 may include grading (e.g., increasing and/or decreasing) of the concentration of one or more materials within the feature, such as the grading of a semiconductor material component concentration and/or the grading of the dopant concentration, for example. For instance, in some such embodiments, the dopant concentration included in a given S/D region 261/262 may be graded such that it is lower near the corresponding channel region and higher near the corresponding S/D contact, which may be achieved using any suitable processing, such as tuning the amount of dopant in the reactant flow (e.g., during an in-situ doping scheme). In some embodiments, a given S/D region 261/262 may include a multilayer structure that includes at least two compositionally different material layers. In some embodiments, a given S/D region may be raised such that it extends higher than a corresponding channel region. In some embodiments, a given S/D region may be formed in a cladding scheme, where the final S/D material is formed on and over original material in the given S/D region (such as material native to the substrate or replacement material previously formed in the region). For instance, the second-right-most transistor structure shown in Figure 5 includes such a cladding scheme where the final S/D material 261 was formed on native fin 204 as shown. Numerous different S/D configurations and variations will be apparent in light of this disclosure.

Continuing with optionally performing 128 the final gate stack processing, such optional processing 128 was performed to form the resulting final gate stack shown in Figure 4, which includes final gate dielectric 282 and final gate electrode 284, in this example embodiment. Performing 128 the final gate stack processing may be optional as the final gate stack layers may be initially formed during process 104 (as indicated by alternative optional gate first flow 100'), such that the replacement gate process about to be described does not occur. However, in this example embodiment, the final gate stack is formed using a gate last flow (also called a replacement gate or replacement metal gate (RMG) process). Regardless of whether gate first or gate last processing is employed, the final gate stack can include gate dielectric 282 and gate electrode 284 as shown in Figure 4 and described herein.

Performing 128 the final gate stack processing, in this example embodiment, first included depositing interlayer dielectric (ILD) layer 270 after the S/D regions 261/262 were processed, followed by planarization and/or polish processing (e.g., CMP) to reveal hardmask layer 236 and ultimately gain access to the dummy gate stack (which included dummy gate dielectric 232 and dummy gate electrode 234). Note that ILD layer 270 is shown as transparent in the example structure of Figure 5 to allow for the underlying features to be seen; however, the present disclosure is not intended to be so limited. Also note that ILD layer 270 may include a multilayer structure, even though it is illustrated as a single layer. Further note that in some cases, ILD layer 270 and STI material 220 may not include a distinct interface as shown in Figure 5, particularly where, e.g., the ILD layer 270 and STI material 220 include the same dielectric material. In some embodiments, the ILD layer 270 may include any suitable electrical insulator, dielectric, oxide (e.g., silicon dioxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure.

The final gate stack processing, in this example embodiment, continued with removing hardmask layer 236 and the dummy gate stack (including dummy gate electrode 234 and dummy gate dielectric 232) to allow for the final gate stack to be formed. Note that when the dummy gate is removed, the channel region of the transistor (such as channel region 205 in Figure 4) is exposed to allow for any desired processing. Such processing of a given transistor channel region may include various different techniques, such as removing and replacing the channel region with replacement material, doping the channel region as desired, forming the fin into one or more nanowires (or nanoribbons) for a gate-all-around (GAA) transistor configuration, cleaning/polishing the channel region, and/or any other suitable processing as will be apparent in light of this disclosure. For instance, in an example embodiment, finned channel region 206 in Figure 5 (which is the channel region of the second-right-most of the four original finned structures from Figure 2D) is shown as including material native to substrate 200 (e.g., in such an embodiment, channel region 206 may just be a portion of original native fin 204 that may or may not have been subsequently processed), in accordance with some embodiments. Further, in another example embodiment, finned channel region 206' in Figure 5 (which is the channel region of the second-left-most of the four original finned structures from Figure 2D) is shown as including replacement material that is not native to substrate 200 (e.g., in such an embodiment, channel region 206' may just be a portion of original replacement fin 202' that may or may not have been subsequently processed). Further still, in another example embodiment, finned channel region 207 in Figure 5 (which is the channel region of the left-most of the four original finned structures from Figure 2D) may include a different replacement material that may have been formed by removing the material in the channel region while that channel region is exposed during replacement gate processing, for example.

In addition, nanowire channel region 208 is illustrated in Figure 5 (which is the channel region of the right-most of the four original finned structures), which may have been a portion of replacement fin 202' (as previously described, where replacement fin 202' includes a multilayer structure including sacrificial material to be removed and form the one or more nanowires), for example, or it may have been processed in any suitable manner. For instance, nanowire channel region 208 may have been formed after the dummy gate was removed and the channel regions of the fins were exposed, by converting the finned structure at that location into the nanowires 208 shown using any suitable techniques, for example. For instance, the original finned channel region may have included a multilayer structure, where one or more of the layers were sacrificial, such that they were able to be selectively etched to remove those sacrificial layers and release the nanowires 208. As shown in Figure 5, nanowire channel region 208 includes 2 nanowires (or nanoribbons) in this example case. However, a nanowire (or nanoribbon or GAA) transistor formed using the techniques disclosed herein may include any number of nanowires (or nanoribbons) such as 1, 3, 4, 5, 6, 7, 8, 9, 10, or more, depending on the desired configuration. As can be understood based on this disclosure, the channel region is generally at least below the gate stack, in the example embodiments provided herein. For instance, in the case of a finned transistor configuration, the channel region may be below and between the gate stack, as the stack is formed on three sides as is known in the art. However, if the transistor device were inverted and bonded to what will be the final IC substrate, then the channel region of that transistor may be above the gate structure. Therefore, in general, the gate structure and channel region may include a proximate relationship, where the gate structure is near the channel region such that it can exert control over the channel region in some manner (e.g., in an electrical manner), in accordance with some embodiments. Further, in the case of a nanowire (or nanoribbon or GAA) transistor configuration, the gate stack may completely surround each nanowire/nanoribbon in the channel region (or at least substantially surround each nanowire, such as surrounding at least 70, 80, or 90% of each nanowire). In some embodiments, a nanowire or nanoribbon may be considered fin-shaped where the gate stack wraps around each fin-shaped nanowire or nanoribbon in a GAA transistor configuration. Further still, in the case of a planar transistor configuration (which may be the case in Figure 4, where the channel region is indicated as 205, however, Figure 4 may also be illustrating a finned transistor configuration where the cross-sectional view is taken along the fin), the gate stack may simply be above the channel region. In some embodiments, a given channel region may include any suitable material as will be apparent in light of this disclosure, such as monocrystalline (or single-crystal) group IV and/or group III-V semiconductor material. For instance, a given channel region may include monocrystalline Si, SiGe, Ge, GaAs, InGaAs, AlGaAs, AlAs, InP, and so forth. In general, a given channel region may include at least one of silicon (Si), germanium (Ge), tin (Sn), indium (In), gallium (Ga), arsenic (As), phosphorous (P), and aluminum (Al), to provide some examples. In some embodiments, a given channel region may be doped (e.g., with any suitable n-type and/or p-type dopant) or intrinsic/undoped (or nominally undoped, including dopant concentrations of less than 1E16 atoms per cubic cm, for example), depending on the particular configuration.

Note that S/D regions 261/262 are adjacent to either side of a corresponding channel region, as can be seen in Figures 4 and 5, for example. More specifically, the S/D regions 261/262 are directly adjacent to a corresponding channel region, such that there are no intervening layers between either of the S/D regions and the channel region, in the example embodiments. However, the present disclosure is not intended to be so limited. Also note that the configuration/geometry of a transistor formed using the techniques described herein may primarily be described based on the shape/configuration of the respective channel region of that transistor, for example. For instance, a nanowire (or nanoribbon or GAA) transistor may be referred to as such because it includes one or more nanowires (or nanoribbons) in the channel region of that transistor. However, the transistor type (e.g., MOSFET, TFET, FFFET, or other suitable type) may be described based on the doping and/or operating scheme of the source, channel, and drain regions, and thus those respective regions may be used to determine the type or classification of a given transistor, for example. For instance, MOSFET and TFET transistors may be structurally very similar (or the same), but they operate differently and include different doping schemes (e.g., source-drain doping schemes for MOSFET of p-p or n-n versus p-n or n-p for TFET). Also note that although all of the S/D regions 261/262 are indicated as including the same final material, the present disclosure is not intended to be so limited, and in embodiments where the channel regions include different semiconductor material and/or doping schemes (such as is shown in Figure 5, for illustrative purposes), the S/D regions 261/262 corresponding to those different channel regions may also include different semiconductor material and/or doping schemes. Further note that the shapes and sizes of the S/D regions 261/262 differ between the structure of Figure 4 and Figure 5, and more generally, the shapes and sizes of other features differ, as numerous different shapes and sizes are achievable for the S/D regions 261/262 and the other features of the structures.

Continuing with performing 128 final gate stack processing, after the dummy gate has been removed and any desired channel region processing has been performed, the final gate stack can then be formed, in accordance with some embodiments. In this example embodiment, the final gate stack includes gate dielectric 282 and gate electrode 284, as shown in Figures 4 and 5. The gate dielectric 282 may include, for example, any suitable oxide (such as silicon dioxide), high-k gate dielectric material, and/or any other suitable material as will be apparent in light of this disclosure. Examples of high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon dioxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon dioxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. In some embodiments, an annealing process may be carried out on the gate dielectric 282 to improve its quality when high- k material is used. The gate electrode 284 may include a wide range of materials, such as poly- silicon (polycrystalline silicon) or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), or tantalum nitride (TaN), for example. In some embodiments, gate dielectric 282 and/or gate electrode 284 may include a multilayer structure of two or more material layers, for example. In some embodiments, gate dielectric 282 and/or gate electrode 284 may include grading (e.g., increasing and/or decreasing) of the content/concentration of one or more materials in at least a portion of the feature(s). Additional layers may be present in the final gate stack, in some embodiments, such as one or more work function layers or other suitable layers, for example. Note that although gate dielectric 282 is only shown below gate electrode 284 in the example embodiment of Figures 4 and 5, in other embodiments, the gate dielectric 282 may also be present on one or both sides of gate electrode 284, such that the gate dielectric 282 may also be between the gate electrode 284 and a given spacer (e.g., gate dielectric 282 may be between gate electrode 284 and thinner gate spacer 251 and/or between gate electrode 284 and thicker gate spacer 252), for instance. Numerous different gate stack configurations will be apparent in light of this disclosure.

Performing 130 the S/D contact processing, in this example embodiment, resulted in the formation of source contact 291 and drain contact 292 as shown in Figures 4 and 5. In some embodiments, S/D contact processing 130 may first include forming contact trenches above the S/D regions 261/262 in which the contacts 291/292 can be formed. In some such embodiments, the contact trenches may be formed using any suitable techniques, such as performing one or more wet and/or dry etch processes to remove portions of ILD layer 270 and to gain access physical access to the S/D regions 261/262, and/or any other suitable processing as will be apparent in light of this disclosure. Such etch processing may be referred to herein as the S/D contact trench etch processing, or simply, the contact trench etch processing. Further, in some such embodiments, the ILD material 270 may first be patterned such that areas that are not to be removed via the contact trench etch processing are masked off, for example.

The S/D contact processing 130 continues with forming S/D contact structures 291/292 above and in electrical contact with respective S/D regions 261/262, in accordance with some embodiments. Note that the contacts 291/292 are also shown as being in physical contact with the respective S/D regions 261/262, however, the present disclosure need not be so limited (e.g., where one or more intervening contact resistance reducing layers are present, for example). In some embodiments, S/D contact structures 291/292 may be formed using any suitable techniques, such as depositing metal or metal alloy (or other suitable electrically conductive material) in the previously formed contact trenches. In some embodiments, S/D contact structure formation may include silicidation, germanidation, III-V-idation, and/or annealing processes, for example. In some embodiments, a given S/D contact 291/292 may include aluminum or tungsten, although any suitable conductive metal or alloy can be used, such as silver, nickel - platinum, or nickel-aluminum, for example. In some embodiments, a given S/D contact 291/292 may include a resistance reducing metal and a contact plug metal, or just a contact plug, for instance. Example contact resistance reducing metals include, for instance, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys. Example contact plug metals include, for instance, aluminum, copper, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy may be used. In some embodiments, additional layers may be present in the S/D contact regions, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired. In general, in some embodiments, a given S/D contact 291/292 may include a multilayer structure including at least two material layers. Further, in some embodiments, a given S/D contact 291/292 may include grading (e.g., increasing and/or decreasing) of the concentration of one or more materials within the structure.

In some embodiments, the length of gate electrode 284 (e.g., the dimension between spacers 251 and 252 in the Z-axis direction), which is indicated as Lg in Figure 4, may be any suitable length as will be apparent in light of this disclosure. For instance, in some embodiments, the gate length may be in the range of 3-100 nm or greater (or in a subrange of 3- 10, 3-20, 3-30, 3-50, 5-10, 5-20, 5-30, 5-50, 5-100, 10-20, 10-30, 10-50, 10-100, 20-30, 20-50, 20-100, or 50-100 nm), or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the gate length Lg may be less than a given threshold, such as less than 100, 50, 45, 40, 35, 30, 25, 20, 15, 10, 8, or 5 nm, or less than some other suitable threshold as will be apparent in light of this disclosure. In some embodiments, the techniques enable maintaining a desired device performance when scaling to such low thresholds, such as sub-50, sub-40, sub-30, or sub-20 nm thresholds, as can be understood based on this disclosure. In some embodiments, the gate length Lg is the same as or approximates the effective channel length (e.g., the length of the effective channel of channel region 205 in Figure 4).

In some embodiments, the techniques described herein can reduce the physical gate-drain overlap (and thereby reduce the gate-drain overlap capacitance) by employing the relatively thicker gate spacer 252 on the drain region 262 side of the gate stack, such as is shown in Figure 4, to benefit transistor performance (particularly for a source amplifier circuit). Further, in some such embodiments, the gate-drain overlap reduction can be achieved without sacrificing gate- source overlap, which is desirable because increasing gate-source overlap generally increases the drive current of the transistor. Moreover, in some such embodiments, the techniques may improve gate-source overlap by employing relatively thinner gate spacer 251 over standard processing techniques, thereby further increasing device performance. As previously described, the gate length Lg is shown in Figure 4, where the length is measured near the channel region (such as channel region 205). Thus, because the gate stack is sloped or curved with the relatively longer (or wider, in the horizontal or Z-axis direction) portion of the gate stack at the bottom or base, the techniques need not cause an increase in gate resistance for a given cross-sectional area, and can even improve gate resistance when compared to standard gate spacer thickening techniques (e.g., where the gate spacer is thickened uniformly on both sides of the gate stack). In some embodiments, a given gate stack including asymmetric gate spacers as described herein may include a ratio of the length (or width, in the horizontal or Z-axis direction) of a base portion to a top portion of that given gate stack of at least 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.5, 3, 4, 5, or greater, for example. In some embodiments, a given gate stack including asymmetric gate spacers as described herein may include a base portion that is longer (or wider, in the horizontal or Z-axis direction) than a top portion of that given gate stack by at least 1 -50 nm or greater, for example. Note that although source region 261 extends under thinner gate spacer 251 and drain region 262 does not extend under thicker gate spacer 252 in the example embodiment of Figure 4, the present disclosure is not intended to be so limited unless otherwise stated.

Method 100 of Figure 1 continues with completing 132 integrated circuit (IC) processing as desired, in accordance with some embodiments. Such additional processing to complete the IC may include back-end or back-end-of-line (BEOL) processing to form one or more metallization layers and/or to interconnect the transistor devices formed during front-end or front-end-of-line (FEOL) processing, for example. Any other suitable processing may be performed, as will be apparent in light of this disclosure. Note that the processes 102-132 of method 100 are shown in a particular order for ease of description. However, one or more of the processes 102-132 may be performed in a different order or may not be performed at all. For example, box 102 is an optional process that need not be performed when fabricating planar transistor configurations. Further, box 128 is an optional process that need not be performed in embodiments employing a gate first process flow, for example (as a dummy gate may not be employed and the final gate stack materials may instead be formed at box 104). Numerous variations on method 100 and the techniques described herein will be apparent in light of this disclosure.

Recall that the techniques may be used to form a multitude of different transistor types and configurations. For instance, the techniques and IC structures described herein may be used for different transistor configurations as can be understood based on this disclosure. For example, the structure of Figure 2C may continue to the structure of 2D, where a finned configuration is desired, or processing may continue to the structure of Figure 2C where replacement fin 202' includes a multilayer structure including sacrificial material to be subsequently removed to form a transistor having a nanowire or gate-all-around configuration, or processing may continue such that the STI material 220 is not recessed to form transistors including planar configurations where the top of fins 202 are used. In addition, the structures of Figures 3A-L, 4, and 4' may be cross-sectional views of a finned configuration where the cross-section is along a fin, such that substrate 200 in those structures is instead a fin that may or may not be native to the actual substrate (e.g., it may be the cross-section of a native fin, such as native material fin 204, or a non-native replacement material fin, such as replacement material fin 202'). Numerous variations and configurations will be apparent in light of the present disclosure.

Example System

Figure 6 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set -top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit (IC) including at least one transistor, the IC including: a channel region; a gate structure at least above the channel region; a source region adjacent the channel region; a drain region adjacent the channel region; a first gate spacer adjacent a first side of the gate structure, the first side of the gate structure closer to the source region than to the drain region, wherein the first gate spacer includes insulator material; and a second gate spacer adjacent a second side of the gate structure, the second side of the gate structure closer to the drain region than to the source region, wherein the second gate spacer includes insulator material; wherein in a given horizontal plane passing through both the first and second gate spacers, the second gate spacer is at least 1 nanometer (nm) wider than the first gate spacer.

Example 2 includes the subject matter of Example 1, wherein the second gate spacer is at least 1.2 times wider in the given horizontal plane than the first gate spacer.

Example 3 includes the subject matter of Example 1 or 2, wherein the second gate spacer is at least 1.5 times wider in the given horizontal plane than first gate spacer.

Example 4 includes the subject matter of any of Examples 1-3, wherein the second gate spacer is at least 5 nm wider in the given horizontal plane than the first gate spacer.

Example 5 includes the subject matter of any of Examples 1-4, wherein at least a portion of the first gate spacer includes one of a slanted and curved profile.

Example 6 includes the subject matter of any of Examples 1-5, wherein the first and second gate spacers include the same insulator material.

Example 7 includes the subject matter of any of Examples 1-6, wherein the second gate spacer defines a plane and at least a portion of the first gate spacer is slanted at least 5 degrees from the plane defined by the second gate spacer.

Example 8 includes the subject matter of any of Examples 1-7, wherein a base portion of the gate structure is wider between the first and second gate spacers than a top portion. Example 9 includes the subject matter of Example 8, wherein the base portion of the gate structure is at least 5 nm wider between the first and second gate spacers than the top portion.

Example 10 includes the subject matter of any of Examples 1-9, wherein the insulator material included in the first and second gate spacers is at least one of silicon dioxide and silicon nitride.

Example 11 includes the subject matter of any of Examples 1-10, further including: another channel region, wherein the drain region is between the channel region and the other channel region; another gate structure at least above the other channel region; and a third gate spacer adjacent a side of the other gate structure, the side of the other gate structure closer to the drain region than to another source region, the given horizontal plane passing through the third gate spacer; wherein the third gate spacer is at least 1 nm wider in the given horizontal plane than the first gate spacer.

Example 12 includes the subject matter of Example 11, wherein the third gate spacer is approximately the same width in the given horizontal plane as the second gate spacer, such that the widths of the second and third gate spacers in the given horizontal plane are within 0.5 nm of each other.

Example 13 includes the subject matter of any of Examples 1-12, further including another gate structure including other gate spacers on either side of the other gate structure, the given horizontal plane passing through both of the other gate spacers, wherein each of the other gate spacers have approximately the same widths in the given horizontal plane, such that the widths of the other gate spacers in the given horizontal plane are within 0.5 nm of each other.

Example 14 includes the subject matter of any of Examples 1-13, wherein the at least one transistor includes at least one of the following configurations: planar, finned, finned field-effect transistor (FinFET), double-gate, tri-gate, nanowire, nanoribbon, and gate-all-around (GAA).

Example 15 includes the subject matter of any of Examples 1-14, wherein the at least one transistor is one of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a tunnel field-effect transistor (TFET).

Example 16 includes the subject matter of any of Examples 1-15, wherein the at least one transistor is an n-channel transistor or a p-channel transistor.

Example 17 is a computing system including the subject matter of any of Examples 1-16.

Example 18 is an integrated circuit (IC) including at least one transistor, the IC including: a channel region including monocrystalline semiconductor material; a gate structure at least above the channel region; a source region adjacent the channel region, the source region including monocrystalline semiconductor material; a source contact above the source region and in electrical contact with the source region, the source contact including metal material; a drain region adjacent the channel region, the drain region including monocrystalline semiconductor material; a drain contact above the drain region and in electrical contact with the drain region, the drain contact including metal material; a first gate spacer between the gate structure and the source contact, the first gate spacer including insulator material and having a maximum thickness between the gate structure and the source contact; and a second gate spacer between the gate structure and the drain contact, the second gate spacer including insulator material and having a maximum thickness between the gate structure and the drain contact; wherein the maximum thickness of the second gate spacer is at least 1 nm greater than the maximum thickness of the first gate spacer.

Example 19 includes the subject matter of Example 18, wherein the maximum thickness of the second gate spacer is at least 1.3 times as thick as the maximum thickness of the first gate spacer.

Example 20 includes the subject matter of Example 18 or 19, wherein the maximum thickness of the second gate spacer is at least 3 nm greater than the maximum thickness of the first gate spacer.

Example 21 includes the subject matter of any of Examples 18-20, wherein at least a portion of the first gate spacer includes one of a slanted and curved profile.

Example 22 includes the subject matter of any of Examples 18-21, wherein the first and second gate spacers include the same insulator material.

Example 23 includes the subject matter of any of Examples 18-22, further including additional insulator material between the first gate spacer and the source contact, the additional insulator material different from the insulator material included in the first gate spacer.

Example 24 includes the subject matter of any of Examples 18-23, wherein the second gate spacer defines a plane and at least a portion of the first gate spacer is slanted at least 10 degrees from the plane defined by the second gate spacer.

Example 25 includes the subject matter of any of Examples 18-24, wherein a base portion of the gate structure is wider between the first and second gate spacers than a top portion.

Example 26 includes the subject matter of Example 25, wherein the base portion of the gate structure is at least 5 nm wider between the first and second gate spacers than the top portion. Example 27 includes the subject matter of any of Examples 18-26, wherein the insulator material included in the first and second gate spacers is at least one of silicon dioxide and silicon nitride.

Example 28 includes the subject matter of any of Examples 18-27, further including: another channel region, wherein the drain region is between the channel region and the other channel region; another gate structure at least above the other channel region; and a third gate spacer adjacent a side of the other gate structure, the side of the other gate structure closer to the drain region than to another source region, the third gate spacer having a maximum thickness between the other gate structure and the drain contact; wherein the maximum thickness of the third gate spacer is greater than the maximum thickness of the first gate spacer.

Example 29 includes the subject matter of Example 28, wherein the maximum thickness of the third gate spacer is approximately the same as the maximum thickness of the second gate spacer.

Example 30 includes the subject matter of any of Examples 18-29, further including another gate structure including other gate spacers on either side of the other gate structure, the other gate spacers each having approximately the same width in a given horizontal plane passing through the other gate spacers, such that the widths of the other gate spacers in the given horizontal plane are within 0.5 nm of each other.

Example 31 includes the subject matter of any of Examples 18-30, wherein the at least one transistor includes at least one of the following configurations: planar, finned, finned field-effect transistor (FinFET), double-gate, tri-gate, nanowire, nanoribbon, and gate-all-around (GAA).

Example 32 includes the subject matter of any of Examples 18-31, wherein the at least one transistor is one of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a tunnel field-effect transistor (TFET).

Example 33 includes the subject matter of any of Examples 18-32, wherein the at least one transistor is an n-channel transistor or a p-channel transistor.

Example 34 is a mobile computing system including the subject matter of any of Examples 18-33.

Example 35 is a method of forming an integrated circuit (IC) including at least one transistor, the method including: forming a gate structure at least above a channel region, wherein the channel region is adjacent a source region and the channel region is also adjacent a drain region; forming a first gate spacer adjacent a first side of the gate structure, the first side of the gate structure closer to the source region than to the drain region, wherein the first gate spacer includes insulator material; and forming a second gate spacer adjacent a second side of the gate structure, the second side of the gate structure closer to the drain region than to the source region, wherein the second gate spacer includes insulator material; wherein in a given horizontal plane passing through both the first and second gate spacers, the second gate spacer is at least 1 nanometer (nm) wider than the first gate spacer.

Example 36 includes the subject matter of Example 35, wherein forming the first and second gate spacers includes depositing the insulator material included in both the first and second gate spacers and performing dry etch processing to remove the insulator material from surfaces other than the first and second sides of the gate structure.

Example 37 includes the subject matter of Example 36, wherein the first side of the gate structure includes a profile that is at least partially slanted or curved, such that the dry etch removes the insulator material from the first side of the gate structure relatively faster than it removes material from the second side of the gate structure.

Example 38 includes the subject matter of Example 37, wherein the second side of the gate structure defines a plane and at least a portion of the first side of the gate structure is slanted at least 5 degrees from the plane defined by the second side of the gate structure.

Example 39 includes the subject matter of any of Examples 35-38, further including forming first and second structures above the gate structure, the first structure above the first side of the gate structure and the second structure above the second side of the gate structure, wherein, for a given etch process, the first structure is consumed at a first rate and the second structure is consumed at a second rate slower than the first rate.

Example 40 includes the subject matter of any of Examples 35-39, wherein the first and second gate spacers are formed simultaneously.

Example 41 includes the subject matter of any of Examples 35-40, further including forming another gate structure including other gate spacers on either side of the other gate structure, the given horizontal plane passing through both of the other gate spacers, wherein each of the other gate spacers have approximately the same width in the given horizontal plane as the second gate spacer, such that the widths of each of the other gate spacers in the given horizontal plane are within 0.5 nm of the width of the second gate spacer in the given horizontal plane, and wherein the other gate spacers include the insulator material included in the second gate spacer.

Example 42 includes the subject matter of any of Examples 35-41, wherein at least a portion of the first gate spacer includes one of a slanted and curved profile. Example 43 includes the subject matter of any of Examples 35-42, wherein the second gate spacer defines a plane and at least a portion of the first gate spacer is slanted at least 5 degrees from the plane defined by the second gate spacer.

Example 44 includes the subject matter of any of Examples 35-43, wherein the gate structure is formed using gate last processing that employs a dummy gate structure.

Example 45 includes the subject matter of Example 44, further including converting the channel region to one or more nanowires after removing the dummy gate structure.

Example 46 includes the subject matter of any of Examples 35-43, wherein the gate structure is formed using gate first processing.

Example 47 includes the subject matter of any of Examples 35-46, further including forming a source contact above the source region and forming a drain contact above the drain region, wherein the source and drain contacts each include metal material.

Example 48 includes the subject matter of any of Examples 35-47, wherein the at least one transistor includes at least one of the following configurations: planar, finned, finned field-effect transistor (FinFET), double-gate, tri-gate, nanowire, nanoribbon, and gate-all-around (GAA).

Example 49 includes the subject matter of any of Examples 35-48, wherein the at least one transistor is one of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a tunnel field-effect transistor (TFET).

Example 50 includes the subject matter of any of Examples 35-49, wherein the at least one transistor is an n-channel transistor or a p-channel transistor.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. An integrated circuit (IC) including at least one transistor, the IC comprising: a channel region;

a gate structure at least above the channel region;

a source region adjacent the channel region;

a drain region adjacent the channel region;

a first gate spacer adjacent a first side of the gate structure, the first side of the gate structure closer to the source region than to the drain region, wherein the first gate spacer includes insulator material; and

a second gate spacer adjacent a second side of the gate structure, the second side of the gate structure closer to the drain region than to the source region, wherein the second gate spacer includes insulator material;

wherein in a given horizontal plane passing through both the first and second gate spacers, the second gate spacer is at least 1 nanometer (nm) wider than the first gate spacer.

2. The IC of claim 1, wherein the second gate spacer is at least 1.2 times wider in the given horizontal plane than the first gate spacer.

3. The IC of claim 1, wherein the second gate spacer is at least 1.5 times wider in the given horizontal plane than first gate spacer.

4. The IC of claim 1, wherein the second gate spacer is at least 5 nm wider in the given horizontal plane than the first gate spacer.

5. The IC of claim 1, wherein at least a portion of the first gate spacer includes one of a slanted and curved profile.

6. The IC of claim 1, wherein the first and second gate spacers include the same insulator material.

7. The IC of claim 1, wherein the second gate spacer defines a plane and at least a portion of the first gate spacer is slanted at least 5 degrees from the plane defined by the second gate spacer.

8. The IC of claim 1, wherein a base portion of the gate structure is wider between the first and second gate spacers than a top portion.

9. The IC of claim 8, wherein the base portion of the gate structure is at least 5 nm wider between the first and second gate spacers than the top portion.

10. The IC of claim 1, wherein the insulator material included in the first and second gate spacers is at least one of silicon dioxide and silicon nitride.

11. The IC of claim 1, further comprising:

another channel region, wherein the drain region is between the channel region and the other channel region;

another gate structure at least above the other channel region; and

a third gate spacer adjacent a side of the other gate structure, the side of the other gate structure closer to the drain region than to another source region, the given horizontal plane passing through the third gate spacer;

wherein the third gate spacer is at least 1 nm wider in the given horizontal plane than the first gate spacer.

12. The IC of claim 11, wherein the third gate spacer is approximately the same width in the given horizontal plane as the second gate spacer, such that the widths of the second and third gate spacers in the given horizontal plane are within 0.5 nm of each other.

13. The IC of claim 1, further comprising another gate structure including other gate spacers on either side of the other gate structure, the given horizontal plane passing through both of the other gate spacers, wherein each of the other gate spacers have approximately the same widths in the given horizontal plane, such that the widths of the other gate spacers in the given horizontal plane are within 0.5 nm of each other.

14. The IC of claim 1, wherein the at least one transistor includes at least one of the following configurations: planar, finned, finned field-effect transistor (FinFET), double-gate, tri- gate, nanowire, nanoribbon, and gate-all-around (GAA).

15. The IC of claim 1, wherein the at least one transistor is one of a metal-oxide- semiconductor field-effect transistor (MOSFET) and a tunnel field-effect transistor (TFET).

16. The IC of claim 1, wherein the at least one transistor is an n-channel transistor or a p-channel transistor.

17. A computing system comprising the IC of any of claims 1-16.

18. An integrated circuit (IC) including at least one transistor, the IC comprising: a channel region including monocrystalline semiconductor material;

a gate structure at least above the channel region;

a source region adjacent the channel region, the source region including monocrystalline semiconductor material;

a source contact above the source region and in electrical contact with the source region, the source contact including metal material;

a drain region adjacent the channel region, the drain region including monocrystalline semiconductor material;

a drain contact above the drain region and in electrical contact with the drain region, the drain contact including metal material;

a first gate spacer between the gate structure and the source contact, the first gate spacer including insulator material and having a maximum thickness between the gate structure and the source contact; and

a second gate spacer between the gate structure and the drain contact, the second gate spacer including insulator material and having a maximum thickness between the gate structure and the drain contact;

wherein the maximum thickness of the second gate spacer is at least 1 nm greater than the maximum thickness of the first gate spacer.

19. The IC of claim 18, wherein the maximum thickness of the second gate spacer is at least 1.3 times as thick as the maximum thickness of the first gate spacer.

20. The IC of claim 18, wherein at least a portion of the first gate spacer includes one of a slanted and curved profile.

21. The IC of any of claims 18-20, wherein the first and second gate spacers include the same insulator material.

22. A method of forming an integrated circuit (IC) including at least one transistor, the method comprising:

forming a gate structure at least above a channel region, wherein the channel region is adjacent a source region and the channel region is also adjacent a drain region; forming a first gate spacer adjacent a first side of the gate structure, the first side of the gate structure closer to the source region than to the drain region, wherein the first gate spacer includes insulator material; and

forming a second gate spacer adjacent a second side of the gate structure, the second side of the gate structure closer to the drain region than to the source region, wherein the second gate spacer includes insulator material;

23. The method of claim 22, wherein forming the first and second gate spacers includes depositing the insulator material included in both the first and second gate spacers and performing dry etch processing to remove the insulator material from surfaces other than the first and second sides of the gate structure.

24. The method of claim 22, wherein the first side of the gate structure includes a profile that is at least partially slanted or curved, such that the dry etch removes the insulator material from the first side of the gate structure relatively faster than it removes material from the second side of the gate structure.

25. The method of any of claims 22-24, wherein the first and second gate spacers are formed simultaneously.