CN101379591A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101379591A
CN101379591A CNA2007800049088A CN200780004908A CN101379591A CN 101379591 A CN101379591 A CN 101379591A CN A2007800049088 A CNA2007800049088 A CN A2007800049088A CN 200780004908 A CN200780004908 A CN 200780004908A CN 101379591 A CN101379591 A CN 101379591A
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resistor
protective layer
layer
metallization structure
substrate
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CN101379591B (zh
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约安齐姆·斯坦奇
赖纳·霍夫曼
迈克·伯纳斯
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Vlsi Technology Co Ltd
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Koninklijke Philips Electronics NV
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Abstract

半导体器件(100)包括至少一个半导体元件(20)、包括第一(31)和第二引线(32)并且在电阻上延伸的金属化结构。电绝缘保护层(36)位于电阻(35)上，限定在实质上与电阻图形相同的图形中，并且具有可达到至少等于将要沉积其上的钝化层(37)的沉积温度的温度的温度稳定性，以覆盖金属化结构。电阻(35)和保护层(36)都均匀地沉积在金属化结构和任何下面的衬底上。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件，所述半导体器件包括：具有至少一个半导体元件的半导体衬底、薄膜电阻器、包括第一和第二线的金属化结构，根据需要的电阻图形，电阻在引线之间和之上延伸，以及覆盖金属化结构和电阻器的钝化层，而使金属化结构中的键合焊盘暴露。
本发明还涉及制造这种半导体器件的方法，所述方法包括以下步骤：
在半导体衬底中限定至少一个半导体元件；
使用绝缘层覆盖衬底；
在绝缘层上设置金属化结构，并且在通过绝缘层的通孔中延伸以接触至少一个半导体元件，所述结构包括相互绝缘的第一和第二引线，和至少一个键合焊盘；
在金属化结构和衬底上应用薄膜电阻层；
根据所需电阻图形，借助光致抗蚀剂材料图形化电阻层，使得所述电阻器形成金属化结构的第一和第二引线之间的连接；以及
设置钝化层，所述钝化层使金属化结构中的至少一个键合焊盘暴露。
技术背景
专利申请WO-A2005/024914中公开了这种器件和这种方法。该申请公开了电阻部分地位于金属化的顶端的设置，使得可以免除刻蚀通孔的设置。由此，制造方法变得更为经济，并且获得的电阻表现出小的扩展，因为电阻层上不存在刻蚀。电阻由包含例如氮化钛、钛钨或氮化钛钨的材料构成。
已知的器件的不利之处在于，测试仅能在制造完成之后进行。如果结果不佳，则很可能测试的器件和同批制造的器件都将不能满足器件设定的规范，即位于某种裕度之外。即使已知的电阻与具有顶部接触的电阻相比具有小的扩展，仍然存在器件不符合规范的巨大风险。特别是对于具有相对较低电阻值的器件，即其中电阻图形具有相对小的面积。
发明内容
因此，本发明的一个目的是提供一种开始段落中提及的类型的改进的方法和改进的器件，其中可以较早地检测出生产时的缺陷。
与该器件相关的目的通过下述实现：即器件包括位于电阻器和钝化层之间的电绝缘保护层，该保护层具有均匀的厚度，并且限定在实质上与电阻器图形相同的图形中，并且具有可达到至少等于钝化层的沉积温度的温度稳定性。
与该方法相关的目的通过下述得到，即在图形化之前，将电绝缘的保护层应用到薄膜电阻器上，该保护层具有均匀的厚度，并且可达到至少等于钝化层的沉积温度的温度稳定性，在随后的一个单独步骤中图形化电阻器层和保护层。
令人惊讶地可以发现：如果保护层位于电阻器的顶部，电阻的电阻值变得对任何在电阻层刻蚀后实施的处理都不敏感。这意味着在电阻器的图形化后，电阻值不再改变。结果是可在钝化层设置前实施检查电阻值的测试。为了获得此效果，需要具有均匀厚度和足够的温度稳定性的保护层。
适用于电阻层的材料包括，例如，钛钨、氮化钛钨、氮化钽、镍铬合金和硅铬。使用这些材料，可应用从20Ω/□到1kΩ/□的全谱电阻器值。
适用于钝化层的材料包括氮化硅、氮氧化硅、氧化硅、聚酰亚胺和苯并环丁烯(benzocyclobutene)，但存在最合适的是采用等离子增强型化学气相沉积(PECVD)沉积的氮化硅、氮氧化物或氧化物。这种技术允许设置保形层，即在具有均匀厚度形貌的表面上沉积的层。
适用于保护层的材料具体为无机材料，但不排除诸如聚酰亚胺、聚对二甲苯(parylene)、苯并环丁烯(benzocyclobutene)之类的有机材料。保护层的材料在结构上与电阻层和钝化层类似是非常合适的。希望与电阻层类似，以实现在单个步骤中采用单种刻蚀剂的刻蚀，使得两个层的刻蚀行为类似。希望与钝化层类似，以获得适当的粘合性。
最适用于保护层的为诸如氮化硅、氧化硅和氮氧化硅之类的材料。其中这些材料比诸如氧化钛之类的替代材料更优的是，可适当地从包括相对于半导体衬底实质上不等于零度的角度的表面移除这些材料。例如，这些表面为金属化结构中金属引线的侧表面。由于工艺最好不采用化学机械抛光或平整层平整，所述角度并非精确地已知，并且可能随半导体衬底变化。采用替代材料这可导致甚至更大的问题。
用于保护层的适当沉积方法为化学气相沉积，更优地为PECVD。尽管可使用物理气相沉积，但花费昂贵，低压化学气相沉积不允许用于铝金属化；需要的温度可能损坏金属化结构。如果下面的结构不平整，旋涂或任意其它湿法化学沉积技术也不适用。
最适当地，保护层的厚度为20-200nm。其中，上限由电阻值允许的扩展确定。下限由工艺条件设定。
最适当地，电阻具有小于100Ω的值。由于规范以相对偏差限定，与较大的电阻相比，较小的电阻值更早达到允许的限制。
较优地，在配置保护层之后，使用各向同性干法刻蚀工艺限定电阻值。此刻蚀工艺导致电阻层的高度可重复的形状。与更常用的各向异性干法刻蚀相比，各向同性干法刻蚀的益处为可刻蚀非平整结构。各向同性干法刻蚀比各向同性湿法刻蚀更为优选的，因为后者提供较差的可重复效果。刻蚀溶液的冲洗的污染导致电阻值的不可接受的偏差。仅已经完成的电阻层的刻蚀就会将这种污染提供给后续批次中电阻层的刻蚀。
在较优实施例中，电阻器为滤波器的一部分。例如，适当的滤波器为诸如低通滤波器之类的带通滤波器或通带滤波器。滤波器的设计在原理上众所周知，可使用诸如RC和RCL滤波器之类的不同滤波器类型。例如，适当的拓扑结构是π滤波器或修正的T滤波器，其中将电容器连接到信号线和地之间。反相连接的二极管可作为替代，因为通常二极管的电容足以获得需要的电容。这种电容值可在70-80pF的数量级，但也可在10-20pF的数量级。
半导体元件适当地是防止静电放电(ESD)的保护元件。在这种情况下，将半导体元件耦合在具有输入和输出的信号线和地之间。电阻器为信号线的一部分。
更具体地和较优地，本发明的保护元件提供防止高放电脉冲的保护，而在由所述器件保护的集成电路中实现的ESD保护电路将吸收较低电压的放电脉冲。根据接触的人体模型(方法MIL883E-3015.7)，常规地，集成电路具有2kV的放电保护，并且较优地，器件中的保护元件为至少为8kV的接触(根据IEC61000-4-2，4级)。
有益地，衬底包括导电衬底区域、第一导电率类型的第一区域、邻接衬底表面并且具有与限定结的第一区域的界面的第二导电类型的第二区域，其中衬底还包括在第一区域内从所述结到衬底区域延伸的第三导电区域。
在此实施例中，保护元件为与衬底中的导电掩埋区相连的二极管。作为保护元件，二极管具有良好的性能。特别较优地为齐纳(Zener)二极管。由于导电掩埋区在电荷到达ESD二极管处的情况下能容易地阻止电流，它非常适用于ESD目的。然后，电流通过焊接球流入地。该掩埋区的益处是它组成了距离第一表面较短距离的地平面，因此在金属化结构中提供传输引线特性的互连。
最适当地，半导体衬底的顶部上的绝缘层在低温工艺中形成。例如，它是在化学气相沉积工艺中沉积的氧化物或氮化物，或通过衬底的湿化学氧化形成的氧化物层。然而，它不是诸如常规地应用在半导体衬底上的热氧化物，所述热氧化在限定衬底区域后的热氧化物应用将导致通过衬底的电荷载流子扩散。
本发明不仅涉及制造半导体器件的方法及由此所得的半导体器件。本发明还涉及包括半导体衬底和多个半导体器件的中间产品。这种中间产品通常称为“晶片”。
根据本发明，包括电阻器和具有与电阻实质上相同图形的保护层，所述电阻器在彼此电绝缘的第一和第二金属化引线之间和顶部延伸。中间产品适用于还未沉积的钝化层的沉积。
根据本发明的又一方面，在钝化层的沉积之前，测试至少一些这种中间产品的器件。
通过观察在钝化层的沉积和/或任何进一步封装工艺期间，电阻值不再变化，实现这种中间产品的测试。
显然地，测试和工艺控制是最为重要的，特别是当每个晶片上的器件的数量巨大时。例如，这是在当本发明的器件是所谓的半分立产品或集成分立产品时的情况。通常，这种器件包括少于十个半导体元件和数量相当或更少的电阻器。常规地，在分立器件的区域，测试单独的器件，然后分类，从而分辨不同质量级别。销售不同级别的器件以用于不同目的。然而，由于将电阻器合并到半分类产品中，这种不同级别的限定不再可能；电阻值和集成器件的设计有效地限定了器件的用途。结果，工艺控制的要求更为严格。由于在中间产品阶段的测试，能较早地检测需要的工艺的偏差。可以在器件本身上、中间产品上可用的测试结构上进行测试和/或借助额外的特殊设计测试晶片，以测试诸如沉积步骤或图形化步骤之类的某个步骤的质量。
附图说明
参考附图，进一步说明本发明的这些和其它方面。
图1示出了本发明器件的截面概略图。
具体实施方式
附图并非按比例绘制，并且不同图中的相同的参考数字表示器件的相同部分。它是纯粹的图示性的，并非按比例绘制，并且非意味着限定本发明的范围。
图1概略地示出了半导体器件100的截面图，其中半导体元件为二极管，并且用作防止ESD放电的保护元件。器件100包括具有金属化结构的第一边21。金属化结构包括内部键合焊盘27、28、29和第一引线31及第二引线32。将键合焊盘27-29连接到其上应用有焊接球43的接触焊盘38、39、49。
在此实例中，接触焊盘38作为器件100的输入，并且接触焊盘39作为器件100的输出。接触焊盘49允许额外的接地连接。电阻器35耦合到金属化结构30的第一和第二引线31、32之间。电阻器位于绝缘层24的顶部，所述绝缘层24也作为用于金属化结构的衬底。保护层36设置在电阻器层35的顶部，并且具有实质上与电阻器35相同的图形。在这种情况下，电阻35具有100Ω的值，并且在此实例中由TiWN层构造。其厚度在10-150nm的数量级。在此实例中，保护层36包括氮化硅，并且通过相增强型化学气相沉积(phase enhanced chemical vapordeposition)来沉积。它的厚度为数量级50-200nm。
本发明的器件中的保护元件20是反方向上的齐纳(Zener)二极管。齐纳二极管20包括的第一区域22和第二区域23，所述第一区域22和第二区域23掺杂相反类型，举例来说，n型和p型的杂质。第二区域23为环形，并且位于相距第一区域的一定距离。第一区域22为n型掺杂，并且较优地，具有低于10Ω/□的高导电率。其中掺杂p型的掩埋区26连接到衬底中的高导电性和p型高掺杂区域25。区域25作为内部地。其通过掩埋区27连接到地焊盘48。作为保护元件的这种二极管20的尺寸和选择与掩埋区26的组合允许它作为用于非常高(举例来说，8kV或更高)的ESD脉冲的保护元件。除了具有掩埋区26的这种二极管20以外，其它二极管可限定在不具有这种掩埋区26的相同工艺中。作为替代，双极型晶体管可用作保护元件。
钝化层37限定在金属化结构和保护层36的顶部。钝化层37具有在0.5-2.0μm数量级的厚度。其包括至少部分地暴露下面的键合焊盘48、28、29的孔。器件100在其接触焊盘48、28、29上设置向下突出的金属41，其用于在单个工艺步骤中设置的第一和第二接触焊盘28、29和地焊盘48。例如，向下突出金属41包括具有镍金顶部层42的铝层。例如，可应用已知成分的Sn-Ag-Cu焊接球。例如，适当的直径在200-500微米的范围。这提供了一种芯片尺寸封装，其中器件100可直接装配到印刷电路板，而不需任何其它载体。然而，不排除诸如引线框之类的其它封装。在那种情况，可在向下突出的金属41上应用引线键合，以可代替焊接球43。
在又一实施例中，向下突出的金属41包括Ni，并且顶部层42为诸如Ti层之类的Ni保护层。例如，向下突出的金属41为大约1微米厚，而顶部层42具有大约0.1微米厚。顶部层42确保在借助光致抗蚀剂进行的任何光刻图形化步骤期间，Ni层不被氧化。在此步骤中，可图形化向下突出的金属41，从而包括钝化层37的顶部上的任何连线。在制造完成后，镍保护层42将至少移除部分以暴露向下突出金属41的镍。镍形成用于焊接的适当的粘合材料。
根据本发明，将电阻器层根据所需图形光刻构造到电阻器中，例如使用刻蚀掩模，并且仅在电绝缘保护层沉积之后进行。对于电阻器的稳定性，刻蚀掩模变得有问题；具体地，它的移除有问题。已表现出：需要用于移除刻蚀图形设置的光致抗蚀剂材料的干法刻蚀和湿法刻蚀处理影响没有任何保护的电阻值。
由于本发明的结构，其中电阻器连接到其底边上的金属化引线，不需要移除或图形化电绝缘保护层。
由于其中沉积保护层的较小的厚度，允许使用各向同性方法，特别是使用各向同性干法刻蚀同时刻蚀保护层和电阻层。考虑到缺少结构的平整性，需要这种各向同性干法刻蚀。
不排除集成电路装配到本发明的器件100的第一边21，从而形成一功能实体。使用较小尺寸的焊接球将它们耦合到器件100，焊接球43在图中所示出。

Claims (11)

1、一种半导体器件，所述器件：包括具有至少一个半导体元件的半导体衬底，和薄膜电阻器，以及包括第一和第二引线的金属化结构，根据所需电阻器图形，所述电阻器在所述引线之间和所述引线上延伸，以及钝化层覆盖金属化结构和电阻器，而使金属化结构中的键合焊盘暴露，其中电绝缘保护层位于电阻器和钝化层之间，所述保护层具有均匀的厚度并且限定在与电阻器图形实质上相同的图形并且具有可达到至少等于钝化层的沉积温度的温度的温度稳定性的图形中。
2、根据权利要求1所述的半导体器件，其中所述电阻器是滤波器的一部分。
3、根据权利要求1或2所述的半导体器件，其中所述电阻器具有小于100Ω/□的电阻值。
4、根据权利要求1所述的半导体器件，其中所述保护层包括无机材料，并且均匀地沉积。
5、根据权利要求1或2所述的半导体器件，其中所述半导体元件是防止静电放电的保护元件，并且耦合在输入和输出之间的信号线与地之间，而所述电阻器限定在信号线中。
6、根据权利要求5所述的半导体器件，其中所述衬底包括导电衬底区域、第一导电类型的第一区域、邻接衬底表面并且具有与限定结的第一区域的界面的第二导电类型的第二区域，其中衬底还包括在第一区域内从所述结到衬底区域延伸的第三导电区域。
7、一种制造配置有半导体衬底的半导体器件的制造方法，包括以下步骤：
限定半导体衬底中的至少一个半导体元件；
使用绝缘层覆盖所述衬底；
在绝缘层上设置金属化结构，并且在通过绝缘层的通孔中延伸以接触所述至少一个半导体元件，所述结构包括相互绝缘的第一和第二引线，和至少一个键合焊盘；
在金属化结构和衬底上应用薄膜电阻器层；
在薄膜电阻器上应用电绝缘保护层，所述保护层具有可达到至少等于钝化层的沉积温度的温度稳定性；
根据所需电阻器图形，借助光致抗蚀材料图形化电阻层，使得所述电阻器形成金属化结构的第一和第二引线之间的连接；并且
设置钝化层，使得金属化结构中的至少一个键合焊盘暴露。
8、根据权利要求7所述的方法，其中使用各向同性干法刻蚀执行电阻器层和保护层的图形化。
9、根据权利要求7所述的方法，其中在足够低到防止限定在衬底区域中的电荷载流子扩散的温度下，使用沉积技术以应用绝缘层。
10、根据权利要求7所述的方法和根据权利要求1所述的器件，其中所述保护层具有与钝化层的界面。
11、一种中间产品，包括半导体衬底和多个器件结构，每个所述结构都包括至少一个半导体元件、薄膜电阻器和包括第一和第二引线的金属化结构，根据所需电阻器图形，所述电阻器在所述引线之间和所述引线之上延伸，其中电绝缘保护层位于电阻器的顶部，所述保护层限定在实质上与电阻图形相同的图形中，并且具有可达到至少等于钝化层的沉积温度的温度稳定性，或沉积在器件结构的顶部。
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CN103378096B (zh) * 2012-04-19 2016-08-03 台湾积体电路制造股份有限公司 半导体器件及其形成方法

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ATE480006T1 (de) 2010-09-15
EP1984939A1 (en) 2008-10-29
EP1984939B1 (en) 2010-09-01
JP2009533836A (ja) 2009-09-17
US20110062553A1 (en) 2011-03-17

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