TWI331788B - Chip structure and method for fabricating the same - Google Patents

Description

1331788

MEG 04-014TW-R IX. Description of the Invention: [Technical Field] The present invention relates to a wafer structure and a method, and more particularly to a method for fabricating a wafer structure which can simplify a process step and corresponding thereto The wafer' structure. - [Prior Art] The method of improving the semiconductor device is to reduce the geometry of the integrated circuit by the above results: the above result can reduce the cost per die, and at the same time improve the performance of some aspects of the semiconductor device. . Connecting the integrated circuit to other circuits • or the metal connection between the integrated circuit and the system components (metal is relatively important, and as the integrated circuit is more miniaturized, the on-plane effect is also increased. When the parasitic capacitance and resistance of the metal interconnects increase, it will mean a decrease in the performance of the wafer. Tenth, the most value • concern is the voltage drop (v〇ltage dr〇p) between the powerbuses and the ground bus (gr〇und buses) and the resistance and capacitance delay of the critical signal path. (RC delay). In order to reduce the resistance, if a wide metal wire is used, the parasitic capacitance of these metal lines will rise. In order to solve this problem, a low-resistance metal such as copper is used as a wire, and a dielectric material having a low dielectric constant (1 〇 w_k) is used between the signal lines. From the point of view of 1C connection metal history, sputtered aluminum has become the mainstream of 1C joint metal materials since the 1960s. The thin film aluminum covers the entire wafer by subtractive plating, followed by a yellow lithography process and a dry or wet etch process. • The aluminum metal is patterned. In terms of cost and sputtering stress considerations, it is difficult and costly to fabricate aluminum metal line technology with thicknesses greater than 2 μηη. Around 1995, '°amascene' became another metal that could be used for IC connections. In the case of copper (Damascene) copper, after the insulating layer is patterned, a copper layer can be formed by electroplating and the copper layer outside the opening of the insulating layer can be removed by chemical mechanical polishing (CMP) to connect the copper metal The wire is formed in the opening of the insulating layer. Thick gold on the whole wafer 1331788

MEG 04-014TW-R genus causes large stresses' and the thickness of damascene is usually determined by the thickness of the insulating layer. Therefore, the insulating layer is generally CVD oxide, which cannot be provided due to stress and cost considerations. The thick thickness, that is to say the formation of a copper metal wire having a thickness exceeding 2 μm, is technically difficult and expensive. U.S. Patent No. 5,212,403 (Nakanishi) discloses a method of forming a line-connected line in which internal and external line connections are formed in a line-to-route substrate on the wafer and the design of the logic line depends on the line connection. The length of the line. U.S. Patent No. 5,501,006 (Gehman, Jr. et al.) discloses a structure having an insulating layer between an integrated circuit and a wiring substrate, and by means of a pin which is dispersed, the connection between the contacts of the wafer and the substrate can be made. Electrical connection. U.S. Patent No. 5,755,907 (Jacobs) discloses an integrated semiconductor structure that allows a manufacturer to form a thin film multilayer circuit on a support substrate or a wafer to integrate circuitry external to the wafer. . • U.S. Patent No. 5,106,461 (Volfsonetal) discloses a multilayer wiring structure which is formed by a TAB structure and using a dielectric layer of a polyimide and a metal layer alternately laminated on a wafer. . U.S. Patent No. 5,635/767 (Wenzel et al.) discloses a method of reducing the resistance of a resistor and capacitor by providing a PBGA structure that separates multiple layers of metal. U.S. Patent No. 5,686,764 (Fulcher) discloses a flip-chip substrate which can be reduced in resistance and capacitance by separating the power supply line from the input and output leads. Silicon Processing for the VLSI Era (Vol. • 2, PP. 214_217, Lattice Press, Sunset Beach, CA c. 1990) by Stanley Wolf discusses the use of linoleamide as an intermetallic dielectric material in the 1980s. However, since polyamines have many disadvantages, polyamidoguanidine has not been used for this purpose since then. SUMMARY OF THE INVENTION 6 1331788

MEG 04-014TW-R = The purpose of this is 0 (10) is to improve the performance of the touch circuit. The other purpose of the defeat-Dubu II is to reduce the number of connections and adjacent circuits or electricity. The power supply busbars of several pieces are caused by the line impedance. 〆^流排^抗本发卿再—The purpose is to reduce the power supply of the high-removal component. I want to reduce the low-nature components and find the gold. The purpose of the invention is to Reduce the impedance and load of the connection line of the low power supply K. The second purpose of the present invention is to reduce the RC delay constant of the high signal path. (4) Electric tower team) A few pieces of the person, the hair _ _ _ _ is the application of the small size of the 1C component. The object of the present invention is to promote and enhance the low-voltage transduction metal. Another object of the present invention is to promote and enhance the low-capacitance conductive metal. It is by providing a high-performance 1C component by increasing the input/round count. Furthermore, another object of the present invention is to simplify the wafer by reducing the need for a new distribution of 1/〇 wafers. Further, another object of the present invention is to promote the connection of a high-performance Ic component fish ground bus. A source or a further object of the present invention is to promote high-performance 1C components and timing eight-cloth network. (clock distribution networks) connection. Further, another object of the present invention is to provide a clean room by using a less expensive process or by using a clean room requiring less stringent cleanliness. Reduced Busy: 7 1331788 MEG 04-014TW-R for cost, and all of the above are compared with submicron (sulMnicr〇n) manufacturing requirements. Furthermore, another object of the present invention is to drive and stimulate systemized wafers ( :ystein-〇n-chiP The design of this is because this month can provide a simple and low-cost line hunting to connect long-distance functional circuits. ^, this hair _ _ - the purpose is to operate the winding software on the computer w < required Lianlin Road secret automatically wraps A over a predetermined length of connecting line 0. The present invention can form a thick polymer dielectric layer of - or multiple layers and a layer or a thick and wide metal The circuit is on the protective layer of the finished wafer. The thick dielectric layer is polyweisamine or phenylcyclobutene (BCB), which is more than 3 microns thick. Thick and ^^^ is electro- or electroplated Thick dielectric layer and thick and wide metal-level signal path, power/ground bus, power/ground level (cIockdistributionnetworks) > ^ for key signal transmission or for redistributing input/output pads Electricity: In addition, the present invention provides a tmarn-like complement structure for a high performance integrated circuit. Touching the bottom of Weibao Caixian County:: The thin metal structure consists of a thin metal interconnect that is connected to the semi-conductor and has a protective layer formed thereon. Protect the indoor ear rain from the connection of fine metal interconnects. The top metal gentleman configuration ^ is accompanied by a two-port/storm path to the fine metal interconnect, and the top metal joint is connected to the fine metal interconnect. By the top metal knot 忒 = the product value is, for example, much smaller than the thin core under the protective layer

8 ~丄/88

MEG 04-014TW-R= The above and other objects, features and advantages of the present invention will become more apparent and understood. Uncovering the integrated circuit structure, in which the reconfigurable connection metal layer and the polymerization-on the protective layer of the conventional IC, the reconfigurable connection metal layer uses a wide and thick ^ ^ ^ line, so the _ low resistance capacitance delay. Alternatively, the metal circuitry on the protective layer may be connected to a separate, electrically conductive, point-exposed connection that is exposed outside of the opening of the protective layer. Alternatively, an inductive 7G device, a capacitive element or a resistive element can be formed by using a thick metal layer on the protective layer. Please refer to ® la to record the semiconductor crystal of the present invention. The semiconductor soil bottom 1 is, for example, a germanium substrate, a germanium substrate or a gallium arsenide substrate, and is doped with a pentavalent or triple= ion such as a _ sub or a _ sub-substrate to form a plurality of electronic components on the surface of the substrate 1, such as As shown in the component layer 2 in the figure, the electronic components are, for example, 'oxygen, semiconductor, transistor, multi-yellow resistive element, and capacitive element with polycrystalline dream as electrode (p〇ly-t〇-p〇ly capadt) 〇r) and so on. The busy layer 3 on the component layer 2 is occupied by the inter-depositive_consideration_ dielectric layer. In general, the inter-metal thin film dielectric layer material includes an oxide containing a stone, such as a chemical phase sink, an oxidized oxide, a chemical vapor deposited TE〇s oxide, or a spin-formed glass (SOG). ), fluorinated glass (FSG) and chemical vapor phase formed by high-density plasma, especially === lion (four) is a combination of thin layers, such as _〇 micron to 1〇, _ Between microns. The thin film circuit layer is generally formed by Lin Shao or Ming alloy, which is patterned by sputtering or aluminum t gold to form a fine metal circuit. In the embodiment, for example, aluminum copper with a steel weight I percentage of less than 5% is used. The alloy acts as a thin metal line under the protective layer. In the aluminum process, a metal layer such as aluminum is first formed by sputtering on a dielectric layer such as ruthenium dioxide, and then the metal layer is patterned by photolithography etching, 9 3 1331788

After MEG 04-014TW-R, another dielectric layer such as cerium oxide or a dielectric constant of less than 2.5 is formed on the metal layer by chemical vapor deposition, and then lithographic etching can be used. The other dielectric layer is such that a plurality of openings can be formed in the other dielectric layer and expose the metal layer in the lower layer, and the subsequent processes are sequentially repeated according to the process described above. Narration. Alternatively, the thin film wiring layer metal lines may be formed by a damascene process. In the inlaid copper process, copper is protected by an adhesion/barrier layer located beneath the copper layer and on the side walls of the copper layer to prevent the migration of copper ions from affecting the active components. In the inlaid copper process, a dielectric layer such as a dioxide dioxide or a dielectric constant having a dielectric constant of less than 25 is formed by a chemical vapor deposition method, and then the dielectric layer is patterned by microlithography. The plurality of openings may be formed of gold in the dielectric layer, and then the adhesion/barrier layer of the layer of lanthanum, lanthanum or titanium nitride may be formed on the dielectric layer and the opening of the dielectric layer. Γ or chemical vapor deposition forms an adhesion such as copper: copper;:===: chemical mechanical polishing (CMP) removes the barrier at the opening of $5 and the barrier layer, followed by the process system The above-mentioned system is repeated in order, and will not be described again here. The metal lines of the thin circuit layer are generally between the chambers. In the production of thin metal wire of the film circuit layer: When: Α Dust to the city standard - generally less than or equal to the grade ig =: size is larger than 〇. 5 microns of impurities should not exceed 10. Thin 3 (SclerSI_ domain (four) scanners are all less than 5 microns. ^The thickness of the layer is generally used, and in the uppermost layer there are thunder fish connected to the electronic components to form the operating electrical pads), this metal connection point Raise the $ connection point, for example, the connection pad (bond connection. '" eight C connection circuit layer and external circuit electrically connected 10

MEG 04-014TW-R 糸You are configured on the 1C connection structure and have a plurality of openings 'exposed: IC connection structure' to provide electrical connection points. In the current technology v layer through $^ money touch chemistry (10) deposition method (Piasma

Enhanced Chemical Vapor Deposition, PECVD) #a^^ft^^^ Nitride. In forming the protective layer 4, a layer of PECVD oxide having a thickness of about Μμm may be deposited first, followed by a layer of nitrogen having a thickness greater than 〇 3 μm, preferably 〇 7 μm. It is important to find the job layer 4, which can tilt the thin film circuit layer and the thin film dielectric layer in the component 2 and 1C wiring layer 3 from moisture and transition metals such as gold, silver, copper, etc. Destruction of the foreign ion contaminant of sodium ions. For the purpose of protection, the thickness of the tantalum nitride layer of the protective layer 4 is usually greater than 0.3 micrometers, and thus is located in a sub-micron process (open) into an integrated circuit having fine lines. The formed IC circuit layer 3 and the protective layer 4 formed by the tens or micron (greater than 1 micron) process (forming a thick and wide metal interconnect structure) and the protective layer 8 The key importance, by the protection of the protective layer 4, allows the formation of the back cover 8 ,, allows a cheaper process to make thick and wide metal interconnects and thick polymer layers, and can use lower cleanliness Level clean room to manufacture. The thickness of the protective layer 4 is, for example, greater than 0.35 micrometers, and the protective layer may be formed of epoxide oxide, phosphoric silicate glass (PSG), borax glass layer in addition to PECVD oxide and PECVD nitride. (borophosphosilicate glass, BSG), borophosphosilicate glass (BPSG) or a composite layer composed of at least one of the above materials. In one embodiment, the protective layer 4 comprises a layer of a ruthenium compound and a layer of an oxonium compound, wherein the layer of the ruthenium compound is on the ruthenium compound layer, and the thickness of the ruthenium compound layer is, for example, from 0.2 micron to 1.2. Between the micrometers, the oxonium compound layer is, for example, between 0.1 micrometers and 0.8 micrometers. In general, the protective layer 4 is included in the production 1331788

MEG 04-014TW-R completes the topmost layer of nitrogen bismuth compound and the topmost layer of oxonium compound in the wafer structure, and the protective layer 4 is included in the topmost layer of the fabricated wafer structure by & vapor deposition The insulating layer formed. A plurality of openings in the protective layer 4 expose the topmost thin film wiring layer of the Ic wiring layer 3, and the lateral maximum dimension of the opening in the protective layer may be between 0.1 micrometers and 25 micrometers. The thick and wide metal lines of the back cover layer 80 can be formed on the protective layer 4 by the selective deposition process as described below. The resistance and capacitance product value of the thick and wide metal lines formed by this technique is much smaller than the protection. The resistance-capacitance product value of the thin metal line of the 1C thin film circuit layer under the layer. Figure 11) is a cross-sectional view showing a semiconductor wafer in accordance with an embodiment of the present invention. A semiconductor substrate 10 has a transistor or an electronic component formed of other materials such as polysilicon. A thin film dielectric layer 12 is formed on the surface of the semiconductor substrate 1 and covers the electronic components. The source and drain diffusion layers 120 are located in the semiconductor substrate. The gate 119 is located in the thin film dielectric layer 12, such that the chand can form a semiconductor under the gate 119. The substrate is located within the crucible and is located between the source (s〇urce) and the drain diffusion layer 120. A plurality of layers of metal/dielectric layer 14 are disposed on the thin film dielectric layer 12, wherein the patterned metal layer in the metal/dielectric layer 14 is formed, for example, by the aforementioned sputtering aluminum process or inlaid copper process. The dielectric layer in layer 14 is, for example, an oxonium compound formed by chemical vapor deposition. For example, the metal layer formed by the above-mentioned sputtering aluminum or inlaid copper process is tied to the metal/dielectric layer 14 of the top layer, and the protective layer 18 is located on the metal layer, and the opening in the protective layer 18 is located. The electrical interface 16 of the metal layer is exposed. The structure and use of the protective layer 18 herein can be referred to the structure and use of the protective layer 4 in Fig. 1a, and will not be described herein. After the protective layer 18 is formed, the previously formed semiconductor element such as M?s and the metal/dielectric layer 14 can be protected from damage by moisture, transition metal or foreign ion contaminants. Therefore, it is possible to allow a relatively inexpensive process to produce a thick and wide metal interconnect and a thick polymer layer formed on the protective layer 18, and can be used at a lower level 12 (S) 1331788

MEG04-014TW-R Clean room manufacturing of clarity grades, for example, in clean rooms of grades (4) or (8), where grade 100 is defined as more than 1 微米5 micron particles per cubic foot of environment. 〇〇 。. After the protective layer 18 is formed, a thick polymer layer 2 can be deposited on the protective layer 18. The material used for the layer 20 is, for example, Hitachi-Dupont Polyimide-1102732 or 2734 (p〇lyimide, PI), or Asahi Polyimine Ls_, i-8·5 or 8m. Another material can also be used to form the polymer layer 2〇, which is BenzoCycl〇Butene (BCB), the manufacturer is D〇w Chemical, for example, and the phenylcyclobutene is gradually substituted. The trend of quinone imine. Polyarene #香基趟1 (4), a porous dielectric material or an elastomer may also be the material of the polymer layer 20. An epoxy group-containing material such as a photosensitive epoxy resin su_8 (manufacturer 'S〇teC Co., Ltd.) can also be used as the material of the polymer layer 20. The deposition of the polymer layer 20 can be formed using spin-on coating and curing, as described below: in spin coating such as photosensitive polyimide. . After the film on the protective layer 18 and the electrical pad 16, the polymer film can be patterned by lithography to form an opening in the polymer film and expose the electrical pad 16, and then The polymer film was placed in a vacuum atmosphere or a nitrogen gas atmosphere, and a curing process of 4 hours was performed using a condition of 380 ° C. Alternatively, it may be another process in which the polymer film may be placed in a vacuum after spin coating, such as a non-photosensitive polyimine poly-3 film on the protective layer 18 and the electrical pad 16. Under ambient or nitrogen atmosphere, and using a condition of 38 degrees Celsius, a .4 row hardening process, the film of the film can be patterned by photolithography to form an opening in the polymer film. And expose the electrical pads 16. To obtain a thicker polymer layer 20, a spin coating step can be used to repeatedly form another polymer film on the previously formed polymer film until the laminated polymer film reaches the desired level. Thickness, in which multiple layers of polymerized 13 1331788

The MEG 04-014TW-R film is, for example, a photosensitive polyimide, and then the multilayer polymer film can be patterned by lithography to form an opening in the multilayer polymer film and expose the electricity. The bonding pad 16 is then placed in a vacuum environment or a nitrogen atmosphere and subjected to a curing process of 380 degrees Celsius for 4 hours, thereby forming a thick layer having a multilayer polymer film. The polymer layer 2 is on the protective layer 18. Or 'If a thicker polymer layer is to be obtained, the spin coating step can be used to repeatedly form another polymer film on the previously formed polymer film until the laminated polymer film is laminated. Achieving a desired thickness, wherein the polymer film of the layer of a layer is, for example, a non-photosensitive polyimide, and then placing the multilayer polymer film in a vacuum or nitrogen atmosphere, and using 38 degrees Celsius The condition is followed by a 4 hour hardening process, and then the multilayered polymer film can be patterned by photolithography to form openings in the multilayer polymer crucible and expose the electrical pads 16, Thus, a thick polymer layer 20 having a plurality of polymer films is formed on the protective layer 18. In addition, the polymer layer 20 can also be formed on the protective layer 18 by screen printing. When the polymer layer 20 is printed, an area can be left unprinted to form an opening, thereby exposing the electrical property. The pad 16 can eliminate the step of lithography or lithography etching. The material of the polymer layer 2 is, for example, polyimide, and then the polymer layer 20 can be placed in a vacuum environment or a nitrogen atmosphere. Next, and use a condition of 380 degrees Celsius for a 4 hour hardening process. Alternatively, the polymer layer 20 may also be formed by thermocompression bonding a dry film having an opening (on the diy protective layer 4, such that the polymer layer 2 having an opening pattern can be directly formed on the protective layer 18) in the polymerization. The opening in the layer 20 exposes the electrical pads 16, so that the steps of lithography or lithography can be omitted. Alternatively, the polymer layer 20 can also be cured by a dry film on the protective layer. Formed by the method of 4, and then formed into a dry film after thermocompression by a lithography process or a lithography process, the opening exposes the electrical pad 16, so that lithography or lithography can be omitted. Step of etching. 1331788

MEG 04-014TW-R In another embodiment, the conditions for hardening the polyimide are not limited to the above technique', and may be hardened at a maximum temperature of 320 degrees Celsius or less, or It is also possible to perform a hardening process of less than 40 minutes at a temperature of more than 320 degrees Celsius, or even a hardening process of less than 2 minutes. The thickness of the polymer layer 20 after the curing process can exceed 2 microns, for example between 2 microns and 150 microns, depending on the electrical design requirements. The thickness of the polymer layer -20 is 2 to 500 times thicker than the thickness of the thin film dielectric layer or the thin film metal layer of the metal/dielectric layer 14. After the hardening step, the sidewalls of the openings in the polymer layer 20 will assume an oblique pattern, and the angle between the sidewalls and the horizontal plane is, for example, 45 degrees or Lu is greater 'substantially between about 50 degrees and 60 degrees. Between degrees; or, the angle of inclination of the side wall can also be as small as 20 degrees. At this point the opening in the polymer layer 20 can be a semi-conical pattern. - Referring to Figure 1b, the maximum transverse dimension of the opening 27 in the polymer layer 20 is greater than the maximum transverse dimension of the opening 17 in the protective layer 18, wherein the maximum lateral dimension of the opening 17 of the protective layer 18 is, for example, Between 1 micrometer and 5 micrometers, in the preferred case 'such as between 0.5 micrometers and 20 micrometers, and the maximum lateral dimension of the electrical pad 16 is, for example, between 0.1 micrometers and 50 micrometers. Between microns, in the preferred case 'is between 0.5 microns and 20 microns, for example. The maximum lateral dimension of the opening _ 27 of the polymer layer 20 is, for example, between 1 micrometer and 1 micrometer, and preferably, for example, between 2 micrometers and 30 micrometers. Since the electrical pad 16 can be made small, it can increase the wiring of the same metal layer as the electrical pad 16; the winding capability of the circuit can reduce the gap between the electrical pad 16 and the underlying thin metal layer. The parasitic capacitance generated. - Referring to FIG. 1b' after forming the polymer layer 20, a thick metal layer 30 may be formed on the polymer layer 20 and in the opening 27 in the polymer layer 20, through a thick and wide metal of the thick metal layer 30. The line 26 can electrically connect the plurality of electrical pads 16. Please refer to FIG. 1b' for electrical transmission, such as by a semiconductor component, 12没 15 1331788

MEG 04-014TW-R - The signal can pass through the multi-layer metal/dielectric layer M of the thin film metal layer 40, 42 j interface 16 and then through the thick and wide metal line 26 (the path of the wheel is like arrow / input ^ And 4) are transferred to the other electrical pad 16, and then transferred to the closed end (10) of the other semiconductor element via the thin film metal layer of the plurality of metal to the electrical layer 14. The thick metal layer 3B shown in =ib can be referred to as _ 2a to Figure 1. The illusion 2 represents m闸s ^ with gate, source and bungee. Passive component, wherein the semiconductor component 12 can be connected to the electrical pad 16 via a metal/dielectric layer, and an opening n in the protective layer 18 exposes the electrical pad 16, and the polymerization can be formed by the method described above. The layer 2 is on the protective layer 18, and the opening d 27 in the layer 2G exposes the electrical interface 16, as shown in Fig. 2a. ^ Next, referring to FIG. 2b, after forming the polymer layer 20 onto the protective layer 18, an adhesion/barrier layer 2 can be sputtered on the polymer layer 2, and the opening σ 17 + in the polymer layer can be sputtered. And the electrical interface 16 , the adhesion / barrier layer of the crane alloy, chromium, copper alloy, Qin, Syrian, nitrogen compounds or titanium nitride compound f thickness of about 0.01 micron to 3 micron, in comparison In a preferred embodiment, for example, between 200 angstroms (angStro _ 5 angstroms), then using a sputter or electroless plating to form a seed layer 2 〇 2 in the adhesion/obstruction layer. The material of the seed layer 202 is, for example, copper, gold, silver, gems, face, enamel, sulphur or nickel, and the thickness thereof is between about G.G1 and 3 microns, and in the case of the case, for example, 300 angstroms to loooo angstroms. Next, please refer to Fig. 2c' to form a thick photoresist layer 2 〇 3 on the seed layer 2 〇 2 thickness between about 1 micron and 1 〇〇 micron, The thick photoresist layer 203' can then be patterned by lithography to form an opening in the thick photoresist layer 2〇3 and expose the seed. The layer 202, wherein the photoresist layer 203 can be exposed by an exposure aligner or a step (1X) stepper. For example, please refer to FIG. 2d, and then the electric clock can be utilized. Or a method of forming a metal layer 204 on the seed layer 202 exposed by the opening of the thick photoresist layer 203, gold 1331788

The material of the MEG 04-014TW-R genus layer 204 is, for example, copper, gold, silver, or m-genus, which is formed by electron microscopy to form a large weight percentage; Or even more than 99% of the copper, the material of the seed layer 2〇2 may be, the ratio is greater than 90% or even greater than the copper of the crucible, when the metal layer 2〇4 is formed by the electric clock to form a weight percentage greater than 90% Or even more than 99% of the gold, the material of the seed sound 2〇2 may be a weight greater than 9G% or even more than 99% of the gold; when the metal layer 204 is formed by means of electric ore to form a weight percentage greater than 9〇% or even When the silver is larger than "%, the material of the seed layer 202 may be silver with a percentage of t greater than 90% or even greater than 99%; when the metal layer 2〇4 is formed by means of electric ore, the weight is greater than 90 When % or even more than 99% of palladium, the material of the seed layer 2〇2 may be more than 9G% or even more than 99% by weight; when the metal layer system is formed by electricity, the weight percentage is greater than 90%. Or even more than 99% of the turn, the material of the seed-layer 202 may be greater than 90% by weight or even greater than 99°/. Platinum; when the metal layer 204 side is formed by electroplating to a weight percentage greater than 9〇% or even greater than "%, the material of the seed layer 202 may be greater than 90% by weight or even greater than 99%; The metal layer 2〇4 is formed by electroplating to form a weight of • 大于 greater than 90% or even greater than 99%, and the material of the seed layer 2 〇 2 may be more than 90% by weight or even more than 99. /. Then, when the metal layer 2〇4 is formed by electroplating, the weight percentage is greater than 90. /. Or even more than 99% nickel, the material of the seed layer 202 may be more than 90% by weight or even more than 99% of nickel. Thus, the present invention reduces the waste of material by forming a thick metal line on the protective layer 18 by a selective deposition process, particularly when precious metals such as gold, silver or palladium are used. In contrast, using a standard inlay copper process to form a thin film metal, the metal is fully plated on the wafer, so that the entire wafer is covered with a thick metal, causing wafer warpage to cause process problems; Inlaid copper process is removed by polishing to eliminate the need for 17 1331788

The metal removed by MEG 04-014TW-R metal is often contaminated and cannot be reused at high cost. The selective deposition process of the present invention 'the metal sound 204 formed by selective deposition is limited only by the light_thickness, so the selective deposition of the present invention can be different. The cost is as follows. In contrast, the inlaid copper process is used to form a metal line that is more technical than that of tn, and the oxidized % dielectric layer formed by the deposition method is 27 Electrically form a thick oxygen-cut dielectric layer and deposit a thick oxidized dream solution. Next, please refer to Figure 2e. After the metal layer is formed, you can go to P and the layer 2〇3. After that, please refer to Figure 2f. Then, the patterned metal layer 2〇4 is used as an etch mask, and the side layer is sequentially removed without being covered by the metal layer 2〇4, and the layer 2〇2 and the adhesion/barrier layer 200 are left only in the metal. Seed sound 2 〇 2 under layer 204 • and adhesion/barrier layer 200. t θ adhesion/barrier layer after self-aligned wet-type engraving process, recess 205 (undercut) will stick/ The periphery of the barrier layer 2〇〇 and the underside of the metal layer 2〇4 are formed. The recessed portion 205 has a recess depth of about 0 03 μm to 2 μm. Between the etched parameters and the etching time, there is a clear boundary between the seed layer 202 formed by sputtering and the metal layer 2〇4 formed by electroplating. For example, penetration can be used. And scanning electron microscope (TEM) observed. m Please refer to the figure %. In the above process, when the material of the metal layer 204 is copper, another metal layer 206 may be formed on the metal layer 2〇4. The material of the metal layer 206 is made of gold, silver, palladium, ruthenium, iridium or nickel, and the thickness thereof is, for example, between 丨 micrometer and 1 〇〇 micrometer. Preferably, the embodiment is between 2 microns and 1 micron, and the thickness of the metal layer 2, 4 is, for example, between 1 and 100 microns, and in the preferred embodiment is between 2 microns. Between 10 micrometers. In terms of process, 18 'S, 1331788 in the formation of the metal layer 204 in the photoresist layer 203

After the MEG 04-014TW-R is exposed on the seed layer 202 (as shown in Figure 2d), the metal layer 2〇6 may be formed on the metal layer 2〇4 by means of electro-mine or electroless plating. - performing a process of removing the photoresist layer 203, and then using the patterned metal layer 2〇4 as an etch mask, sequentially removing the seed layer 202 not covered by the metal layer 204 and adhering/blocking by means of money etching The layer 2 is only left with the seed layer 202 and the adhesion/barrier layer 200 under the metal layer 2〇4. In this way, during the etching of the adhesion/barrier layer 200 and the seed layer 202, the etching of the metal layer 2〇6 can prevent the etching liquid from etching away from the metal layer 204. The copper etching rate can be used at this time. The etchant is used to etch the seed layer 202 and the adhesion/barrier layer 2, which can reduce the consumption of the copper layer of the metal layer 2〇4. In this embodiment, since the money engraving agent for etching the seed layer 2〇2 and the adhesion/barrier layer 200 is engraved from the sidewall of the metal layer 2〇4, there is a 'metal layer 106 edge. The lower surface is exposed to the outside phenomenon. The thickness of the thick and wide metal line formed on the protective layer 18 by the above process is about 1 micrometer to 100 micrometers, and the line spacing of adjacent thick and wide metal lines of the same layer can be More than 2 micro-seeking. The metal process described above on the protective layer 18 can be fabricated in a clean room of class 1 〇〇 or more, and an aligner or an aligner can be used when fabricating the metal line on the protective layer 18. Yes! Double (1χ) exposure stepper (9) printing (4) lithography process for photoresist layer 2〇3 with thickness between 1 micron and 100 micron, so the cost of purchasing waste houses and machinery can be very low. Compared to 1C, thin film metal, use 5 times (9) exposure stepper, scanners or better instruments, _ ϋ ίίί cleanliness level is less than 1G, so the cost of purchasing plant and equipment Very high. • Referring to Figure 2h 'in forming a thick and wide metal line on the polymer layer 2, it is also possible to form a further polymer layer 222 on the thick and wide metal line and on the polymer layer 20' The thick and wide metal circuit formed before the protection, wherein the manufacturing method of the polymer layer 222 can refer to the manufacturing method of the above polymer layer %, located at 1331788

The opening 223 in the MEG 04-014TW-R polymer layer 222 may expose a thick and wide metal line pad, after which bumps or gold bumps may be formed on the interface, or the gold wires formed by the process may be bonded. On this pad. However, the present invention is not limited to the fact that 'the thickness of the protrusion is affected by the line' is not able to form a polymer sound having a flat upper surface. This can be formed by the process of decomposing the polymer layer 222. The flat upper surface layer 222' is as shown in Fig. 2i, wherein the material of the polymer layer is drawn, such as a ring of butyl, a polyimine, a polyarylene (4), a porous material or an elastomer. . For details, for example, after the polymer layer 222 is formed by spin coating as described below, the polymer layer 222 can be hardened by the baking step, and then the mechanical polishing process is flat. The upper surface of the polymer layer 222 is then etched into the polymer layer by a radiant opening 223 to expose a thick and wide metal line pad. Alternatively, other processes may be employed: after the poly layer 222 is formed by coating, the upper surface of the polymer layer 222 may be planarized by a mechanical polishing process or a chemical mechanical polishing process, and then formed by the shadow side. The opening ^ is cured in the polymer layer 222 by a step of baking the exposed metal wiring of the thick and wide metal lines. Alternatively, it may be a potting process. After forming the polymer layer 222 by spin coating, the π 223 may be formed in the polymer layer 222 by means of a lithographic side to expose a thick and wide metal line. The pad is then planarized by the mechanical polishing process or the chemical mechanical polishing process to planarize the upper surface of the polymer layer 222, and then subjected to a baking step to harden the polymerization. Alternatively, it may be another process. After the ruthenium polymer layer 222 is formed by spin coating, the opening a3 may be formed in the poly person layer 222 by the lithographic side to expose a thick and wide metal line. After the second step, the polymer layer 222 is hardened, and then the upper surface of the polymer layer 222 is planarized by a mechanical polishing process or a chemical mechanical polishing process. Forming a flat poly 20 (3⁄4) 1331788

In the process of the MEG 04-014TW-R layer 222, the baking conditions and environment can be referred to the baking conditions and environment of the polymer layer 20 as shown in the figure. Using the polymer layer 222 formation method as disclosed in Figures 2h and 2i, a polymer layer can also be formed on the thick and wide gold's line on the protective layer 18 as shown in Figure 2g. In the method of forming the thick metal line of Figures 2a-2g above, the thick metal line on the protective layer 18 covers the entire sidewall of the opening in the polymer layer 20. However, the present invention is not limited thereto, and the thick metal line located on the protective layer 18 can also cover only the partial surface of the opening in the polymer layer 20, so that the space for the wiring of the line can be saved, so that it can be allowed. More thick metal lines are formed on the polymer layer 2, and the related processes can be seen in Figures 2j and 2k. Please refer to FIG. 2j for the opening of the adhesive/barrier layer 2 and the seed layer 2〇2 on the polymer/layer 20, the sidewall of the opening 27 in the polymer layer 20, and the protective layer 18. After the exposed electrical pads 16 are formed, a patterned photoresist layer 2〇3 may be formed on the seed layer 2() 2 on the polymer layer 2G, and a portion of the patterned photoresist layer 2〇3 is formed. The seed layer 202 on the side wall of the .27 new smear σ 27 of the polymerizer can be formed on the seed layer 2G2 exposed by the opening of the metal layer 2〇4 in the photoresist layer 2〇3. In this embodiment, the method, material and thickness of the adhesion/barrier layer, the seed layer 202 and the + metal layer 204 can be respectively referred to FIG. 2 in the core of the adhesive/barrier layer, the seed layer 2G2 and the metal layer. Description of the formation method and thickness. - Please refer to ® 2k ' and then remove the patterned photoresist layer 2〇3 and the seed layer 202 and the adhesion/barrier layer 200 which are not under the metal layer, under the seed layer and the adhesion/barrier layer 2〇〇 The surrounding is present - the depression 2〇5. In the present embodiment, the size of the depressed portion 205 can be referred to the description of the size of the depressed portion 2〇5 in Fig. 2f. Thus, the thick metal line on the protective layer I8 can cover only a portion of the sidewalls of the opening 27 in the polymer layer 2''. 1331788

MEG 04-014TW-R In addition, when the material of the metal layer 204 is copper, another metal layer 206 may be formed on the metal layer 204 to prevent corrosion of the metal layer 2铜4 of the material, wherein - metal The material of the layer 206 is, for example, gold, silver, handle, platinum, money, rhodium or nickel, the thickness of which is, for example, between 1 micrometer and 100 micrometers, and the thickness of the metal layer 204 is, for example, between 1 micrometer and 100 micrometers. The interval ' is shown in Fig. 21 and Fig. 2m. Referring to FIG. 21, in the process, after the metal layer 204 is formed on the seed layer 202 exposed by the opening in the photoresist layer 203 (as shown in FIG. 2j), electroplating or no The method of forming the metal layer 206 on the metal layer 204 is as follows. Next, the process of removing the photoresist layer 203 can be performed, and the subsequent process is as described above, and will not be described herein. Referring to Figures 2j through 2m, the maximum lateral dimension of the opening 27 in the polymer layer 20 is greater than the maximum transverse dimension of the opening 17 in the layer 18, wherein the maximum lateral dimension of the opening 17 of the protective sound '18 is It is between 微米.1 μm and 50 μm. In the preferred case, for example, between 0.5 μm and 20 μm, and the maximum lateral dimension of the electrical pad 16 is, for example, 〇.1. Between microns and 50 microns, preferably between 0.5 microns and 20 microns. The maximum lateral dimension of the opening 27 of the polymer layer 2 is, for example, between 1 micrometer and 1 micrometer, and preferably between 2 and 30 micrometers. * In one embodiment, a plurality of thick metal layers and a thick polymer layer may be formed on the protective layer, as shown in Figures 3a and 3b. Referring to FIG. 3a, the polymer layer 2 is formed on the protective layer 18. The material and formation method of the polymer layer 20 can be used to moxibus the material and formation method of the polymer layer 20 as shown in FIG. 1b; The metal layer 30 is on the polymer layer 20' and is connected to the electrical pads 16 through the openings in the polymer layer 20 and the protective layer. The detailed structure and formation method of the thick metal layer 30 can be referred to as shown in Figures 2a-2g and 2j. Detailed structure and formation method of the thick metal layer shown in FIG. 2m. The polymer layer 50 is formed on the polymer layer 20 and the thick metal layer 30. The material and formation method of the polymer layer 50 can be referred to as shown in FIG. Show polymer layer 2 〇 材 士 22 1331788

MEG 04-014TW-R and the forming method, the thick metal layer 60 is formed on the polymer layer 5, and the thick metal layer 30 is connected via the opening in the polymer layer 50, and the thick metal layer 50 is detailed. - The formation method can refer to the detailed structure and formation method of the thick metal layer shown in Figures 2a-2g and 2j-2m; then the polymer layer 70 is formed on the polymer layer 50 and the thick metal layer, the polymer layer For the material and formation method of 70, reference may be made to the material and formation method of the polymer layer 20 as shown in the figure, and the opening 77 in the polymer layer 70 may expose the pad of the thick metal layer 60, and then may be formed. Tin-lead bumps or gold bumps may be attached to the pads, or gold wires formed by the wire bonding process may be bonded to the pads. Thus, the thick metal layer and the thick polymer layer can be repeatedly formed in order to form a wide and thick metal wiring structure. Referring to FIG. 3b, the polymer layer 20 is formed on the protective layer 18. For the material and formation method of the polymer layer 20, reference may be made to the material of the polymer layer 2 as shown in FIG. And forming a method; then forming a thick metal layer 30 on the polymer layer 20, and connecting the electrical pads 16 through the openings in the polymer layer 20 and the protective layer 18, the detailed structure and formation method of the thick metal layer 30 can be Referring to the detailed structure and formation method of the ▲ metal layer as shown in Figures 2a_2g and 2j 2m; then forming a polymer layer 50 having a flat upper surface on the polymer layer 2 and the thick metal layer 3 on the polymer layer 5 For the material formation method, reference may be made to the material and formation method of the polymer layer a2 as shown in the figure; then, the thick metal layer 60 is formed on the polymer layer 5 having a flat upper surface, and via the polymer layer 50. The opening of the thick metal layer 3〇, the thick metal layer 5〇 of the second,, and the formation and formation method can refer to the detailed structure and formation method of the thick metal layer shown in Figures 2a-2g and 2j-2m; Shape «Hemu 7G in the aggregation of 50 and thick, on the layer 60 'poly The material and formation method of the Qiqi 7 can be transferred to the material and formation method of the polymer layer 20 as shown in the figure. The opening 2 7 J located in the polymer layer 7〇 exposes the thick metal layer 6 The pad can then be formed with tin bumps or gold bumps on the pads, or the gold wires can be bonded to the pads. Thus, it is possible to repeatedly form a thick metal layer and a thick polymer layer in sequence. 23 1331788

The MEG 04-014TW-R protective layer 18 is formed with a plurality of layers of wide and thick metal wiring structures. 20 照® 聚合物' polymer layer 2 〇 is formed on the protective layer .18, polymer layer. G 贞 贞 村 村 转 转 转 如 如 ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib ib The layer 3G is on the polymer layer 2, and the electrical connection pad is connected to the opening in the composite layer 20 and the protective layer 18. The thick metal reed ==砰: the fine structure and the forming method can be (4) as shown in Fig. 2a_2gA2j 2m The thick layer structure and the formation method of the layer are shown; then the polymer layer 5 is formed on the polymer layer and the thick metal layer 3, and the polymer layer % covers the side wall of the polymer layer 2〇, It is worth noting that 'when the polymer layer 5G is formed, it can be formed by spin coating first - the opening 29 of the polymer film on the thick metal layer 3G, the polymer layer %, the layer 18 and the protective layer 18. After exposing the electrical pad 16, the polymer film disposed on the protective layer and the position exposed by the opening 29 may be removed in a lithographic or flank manner. Electrically ^ 聚合物I6 on the polymer film 'and can form an open σ Μ exposed thick metal layer Deng Zhilian' For the material of the polymer | 50 and a more detailed formation method, reference may be made to the above-mentioned material and formation method of the polymer layer 2 如图 as shown in FIG. 1b; after that, it may be turned into a tin bump or a gold bump in the polymer layer. The electrical pads 16 exposed on the pads exposed in the opening 28 of the opening 28 or the openings 29 in the protective layer 18, or the gold wires formed by the wire bonding process may be bonded in the polymer layer 5 The exposed pad 28 is exposed on the pad or the electrical pad 16 exposed by the opening 29 in the protective layer 18. Referring to Figures 3a, 3b and 3C, the thick metal layer 3 on the protective layer 18 is permeable. The thick metal line 26 can be connected to the gate 119 of the two M〇s elements. The thick metal line 26 on the protective layer 18 can function as a signal transmission wheel and can also serve as a power bus or power plane for power distribution. And can be connected to the power bus or power plane of the thin film metal layer under the protective layer 18; in addition, the thick metal line 26 on the protective layer 18 can also serve as a ground bus for the ground distribution 24 1331788

MEG 04-014TW-R or ground plane, and can be connected to the grounding or ground plane of the thin film metal layer under the protective layer 18. Thus, by forming the thick metal wiring layer 3 and the 6-turn-on-layer 5 layer 18 to form a signal line, a power supply or a ground busbar, the connection of the tin-lead bump, the gold bump or the wire bonding wire to the semiconductor wafer can be simplified. The internal wiring structure of the printed circuit board. + Referring to FIG. 3d, the metal cover 99 may be formed on the electrical interface 16 such as a sputtered or inlaid copper, which may be formed by sputtering aluminum or Electroplating gold. After the metal cover 99 is formed, the polymer layer 20 can be formed on the protective layer 18. The material and formation method of the polymer layer 20 can be referred to the material and formation method of the polymer layer 20 as shown in FIG. The opening in the layer 20 exposes a metal cover 99 which may be formed on the polymer layer 2 and connected to the metal cover 17 via an opening in the polymer layer 20, wherein the detailed structure of the thick metal layer / 30 For the formation method, reference may be made to the detailed structure and formation method of the metal layer shown in Figures 2a 2g and 2j_2m. The exposed metal cover 99 (the leftmost metal cover 99) can be passed through a short distance interconnect formed by a thin aluminum foil or a damascene copper under the protective layer 18. 98 A thick metal line connected to a thick metal layer on the protective layer 18 wherein the length of the short-length φ interconnect 98 is, for example, between 50 microns and 1000 microns. After forming the thick metal layer 30, tin-lead bumps, gold bumps, or wire bonding wires formed by a wire bonding process may be formed on the exposed metal cap 99 (on the leftmost metal cap 99). Electrically connected to an external line. - In addition, in FIG. 3a, FIG. 3b, FIG. 3c, and FIG. 3d, the polymer layer 20 is formed before the formation of the thick metal layer 30. However, the application of the present invention is not limited thereto, and the formation of the polymerization may be omitted. The step of the layer 20 is formed by directly contacting the thick metal layer on the protective layer 18. 4a, 5a, 6a, and 7a illustrate the concept of fan-out pads, pads changing positions, reducing pad configurations, and adding pad configurations through printed circuit boards, such as pads 25!331788

MEG 04-014TW-R is used for signal transmission, ground voltage connection or power supply voltage connection. Figure, %, 6b, and 7b illustrate the concept of fan-out pad-pad, pad change position, reduced pad configuration, and increased pad configuration through a thick and wide metal line on the protective layer. It is used for signal transmission, ground voltage connection or power supply connection. FIG. 4a illustrates the case where the fan-opening concept of the BGA substrate is used on the flip chip package, and the integrated circuit 10 of the five tin-lead bumps 101-105 is taken as an example, and the line in the BGA substrate 130 is used. The 7' bump 101 can change the position of the wheel input/output ^ to the position of the ball solder ball 111. The bump 102 can change the position of the input/output point to the position of the ball solder ball 112, and the bumps 104 and 105 are similarly The position of the input/output points to the ball solder balls 114 and 115 can also be changed. The spacing between adjacent connection points 1; 11 to 115 may be greater than the distance between adjacent tin-lead bumps 101 to 105, and the closer to the intermediate position of the semiconductor wafer 100, the bumps are electrically connected to the bumps The lateral shift of the block is smaller, for example, the lateral displacement of the ball solder ball 113 relative to the bump 1〇3 is smaller than the lateral displacement of the ball solder ball 111 with respect to the bump 101. FIG. 5a illustrates the concept of changing the position of the input/output point for use in a flip chip package connected to the BGA substrate, for example, an integrated circuit 100 including a 5 値 tin-lead bump 1〇1_1〇5. By using the metal lines 131 in the BGA substrate 130, the pads under the b&a base plate 13 can be reordered in any order, depending on the line gauge or package structure. For example, the leftmost bump -101 ' located on the integrated circuit 101 is reconfigured via the metal line 131 in the BGA substrate 130, and can be connected to the second tin-lead formed by ball implantation on the right side below the BGA substrate 130. Solder ball 124. The other bumps 102-105 pass through the metal lines in the BGA substrate 130! 31 After reconfiguration, you can always go to other axes 125, 122, 123 and 121. Figure 6a shows the concept of input/output contact reduction. When the flip chip package is connected to the BGA substrate, the tin-lead bumps 1〇1_1〇5 can be connected to the power, ground or signal pads of the BGA substrate. It is one of 5 tin-lead bumps 1〇1_1〇5

MEG 04-014TW-R

The integrated circuit 100 is taken as an example. The structure of the BGA substrate 130 with lines is shown in the figure, wherein the line includes three line units 132, 134, 136, such as power distribution, ground distribution and signal distribution, respectively, for use in the integrated circuit. The line 132 in the BGA substrate 130 can connect the tin-lead bumps 101, 103, and 105 to one of the connection points 138' below the BGA substrate 130, such as a tin-lead solder ball formed by ball bonding. The other bumps 1〇2 and 104 are reconfigured via the metal lines 134 and 136 in the BGA substrate 130, and can be respectively connected to other tin-lead solder balls 142 and 14〇 formed by ball bonding. In the method, the total number of input/output contacts for connecting the integrated circuit 1 through the BGA substrate 130 can be reduced from the original five to three. In the case of some cases containing a large number of tin-lead bumps, i.e., in the case of conventional flip-chip integrated circuits, it is advantageous to reconfigure the lines by the BGA substrate 130 to form fewer input/output contacts. The concept of the input/output contact increase is shown in Fig. 7a when the flip chip package is connected to the BGA substrate, in which the integrated circuit 100 including three tin bumps 1〇11〇3 is taken as an example. The structure of the BGA substrate 130 including the line is as shown in the figure, wherein the line includes three line units 15 153, 155, such as power distribution, ground distribution and signal distribution respectively for the integrated circuit. The line 153 in the BGA substrate 13 can be connected to the tin-lead bumps 103 to the three connection pads 16 163, 165' below the BGA substrate 13 其, which are, for example, tin-lead solder balls formed by ball placement. After the other bumps 1〇1 and 105 are reconfigured through the metal lines 151 and 155 in the BGA substrate 130, they can be respectively connected to other tin-lead solder balls 162 and 164 formed by ball bonding. In the method, the total number of input y output contacts for connecting the integrated circuit 1 through the BGA substrate 130' can be increased from the original three to five. The functions of the BGA substrate 130 described above, including the opening of the pad, the change of the pad position, the reduction of the pad configuration, and the addition of the pad configuration, can be achieved by the thick metal lines described above on the protective layer. It can be seen from Fig. 4b, Fig. 5b, Fig. 6b and Fig. 7b that the thick metal line on the protective layer can realize the opening of the fan and change the position of the pad 1331788

The concept of MEG 04-014TW-R setting and reducing the pad configuration' and adding the recording configuration is as follows. The thick metal line formed on the protective layer 4 can have the same. FIG. 4b illustrates the function of the thick metal line having the function of the fan-out pad. The metal interface 3〇1_3〇5 exposed in the opening in the layer 5 can pass through the protective layer 4 described above. The thick metal line is divided into external contacts 3 ΐ 3 ΐ 5, such as tin bumps, gold bumps or wire secrets. The metal pads 301-305 in the (4) layer 4 may be arranged in a matrix. In the embodiment, the column-metal contacts 3m-3〇5 may pass through the protective layer 4 described above. The thickness = the line is sequentially fanned out to the parallel arrangement of the external connection point 3 ιι_3 ΐ 5, the fan, the external points 311-315 may also be a matrix arrangement, in this embodiment only the green column, wherein the adjacent external connection The spacing of 3(10)5 may be greater than the lateral displacement of the adjacent gold relative to the metal to which it is electrically connected, and the lateral displacement of 33=3 of the metal interface is less than 311 with respect to the metal pad. The lateral displacement of 301. The thick metal line formed on the f-protective layer 4 can have the function of touching the position of the interface, as shown in the figure. Figure 5b _ thick metal line has the TF intention of re-mating position and sequence function, through the above-mentioned protective layer 4, the metal pad purchase 5 exposed by the opening of the protective layer 4 can be connected separately, to the order and Position and metal connection 3G1 move different from the external contact milk, 323, two two Γ Γ ί 中 中 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 The distance of 321_325 may be the spacing of the metal pads 301-305 of the large adjacent. The thick metal lines formed on the protective layer 4 may have a function of reducing the pad configuration ==6b. Figure (4) shows that the thick metal circuit has the function of reducing the connection configuration. Illustrated, through the thick metal line on the protective layer 4, the metal pad 3 exposed in the opening in the protective layer 4 can be removed. 5 connected to a connected external point 28 1331788

MEG 04-014TW-R 328 'to perform the same function' is used as distributed power supply voltage, distributed ground voltage or distributed signal, and metal interfaces 303, 304 are connected to external contacts 332, 330, respectively. The external contacts 328, 330, 332 are, for example, tin-lead bumps, gold bumps or wire bonding pads. In this embodiment, the total number of external contacts 328, 330, 332 may be less than the total number of metal pads 3〇1_3〇5 exposed by the openings in the protective layer 4. The thick metal line formed on the vine 5 layer 4 can have the function of increasing the interface configuration as shown in Fig. 7b. FIG. 7b is a schematic diagram showing the function of adding a pad arrangement to a thick metal line. The thick metal line on the protective layer 4 can connect one metal interface 303 exposed by the opening in the protection layer 4 to a plurality of Connect external contacts 361, 363, and 365' to perform the same function, such as distributed power supply voltage, distributed ground voltage, or distributed signal. Metal pads 3〇1, 3〇5 are connected to 'connected external contacts, respectively. 362, 364 ' Among them, the external contact points 361-365 are, for example, tin-lead bumps, gold bumps or wire bonding pads. In this embodiment, the total number of external contacts 361-365 can be less than the total number of metal pads 3〇1, 3〇3, and 3〇5 exposed by the openings in the protective layer 4. In other embodiments, the inductor element can be formed on the protective layer using the above-described process of forming a thick metal layer on the protective layer, as shown in Figure 8a, wherein the inductive component is, for example, comprised of horizontally surrounding support coils. After forming the polymer layer 2 on the protective layer 18, a thick metal layer can be formed on the polymer layer 20. The material and formation method of the polymer layer 2 can be referred to the polymer layer 2 as shown in the figure. The material and formation method of the crucible; then, a thick metal layer including the thick metal line 26 and the inductance element 34 is formed on the polymer layer 20, and the electrical connection is made via the opening in the polymer layer 2 and the opening in the protective layer 18. For the detailed structure and formation method of the pad 16, the thick metal layer, reference may be made to the detailed structure and formation method of the thick metal layer shown in FIGS. 2a-2g and 2j-2m. In this embodiment, the inductive element line 40 is in the form of a plane and is parallel to the surface of the substrate 1 , but by a plurality of layers of the metal/dielectric layer 14, the protective layer 18 and the thick polymer layer 2 〇 29 1331788

MEG 04-014TW-R is padded to make the inductance element 34〇 away from the substrate 10 such as 矽, so it can reduce the eddy current effect induced by the inductance element in the substrate 1〇, and 70 pieces of inductance The 34G is stored in a wide and thick Jinlin Road structure, so the loss of resistance energy can be reduced. Therefore, the quality parameter of the inductance element 40 can be improved. Wherein, the inductor element 340 can be paste-mode, the shape of the sister is a low-resistance metal of gold, silver or copper, and the thickness of the metal line of the inductance element 340 is, for example, greater than or μm. In the preferred case, for example, Between 2 microns and 1 micron, the distance between adjacent metal lines of the inductive component 34 can be as small as 4 microns, typically between 0.5 microns and 50 microns. In addition, another polymer layer can be formed on the thick metal line 26 and the inductive element 340. Referring to the figure, for example, the two contacts of the inductive component 340 are connected to the electrical pads 16 exposed by the opening of the protective layer 18; however, the application is not limited to this. One of the contacts of the component 340 is connected to the opening of the protective layer 18 - the exposed electrical pad 丨 6 , and the other contact is formed by a tin-lead bump, a gold bump or a wire bonding process. The wires are externally connected to the outside, and the two contacts of the inductive component 340 can be externally connected to an external circuit through tin-lead bumps, gold bumps or wire bonding wires formed by a two-wire process. Referring to FIG. 8a, the inductive component 340 is formed on the polymer layer 20 on the protective layer 18. However, the application of the present invention is not limited thereto, and the configuration of the polymer layer 20 may be omitted, but the inductive component may be omitted. 34〇 is directly contacted on the protective layer ,8. As shown in FIG. 8b, the detailed structure and formation method of the inductor element 34〇 can refer to the detailed structure of the thick metal layer as shown in FIGS. 2a-2g and 2j-2m. And the formation method. After the inductor element 340 is formed, a polymer layer 341 can be formed on the inductor element 34 and the protective layer 18. The material and formation method of the polymer layer 341 can be referred to the material of the polymer layer 20 as shown in FIG. Forming method. 9a-9b are schematic cross-sectional views showing a transformer formed on a protective layer in accordance with a preferred embodiment of the present invention. The transformer includes the bottom coil 36〇 and the upper layer 30 1331788

MEG04-014TW-R coil 362', wherein the bottom layer coil 360 and the upper layer coil 362 are fabricated by using a metal line process as shown in FIG. 2a-2f or FIG. 2j-2k, or both are as shown in FIG. 2g or FIG. -2m metal circuit process; or, the bottom layer is fabricated by using a metal circuit process as shown in Figures 2a-2f or 2j-2k, and the upper layer 362 is fabricated using, for example, Figure 2g. Or the metal line process shown in FIG. 2k2m; or the bottom layer coil 360 is fabricated by using a metal line process as shown in FIG. 2g or FIG. 21-2m, and the upper layer coil 362 is fabricated, for example, as shown in FIG. 2a. -2f or the metal line process shown in Figure 2j-2k. The two contacts for connecting to the underlying coil 360 are, for example, metal contacts 16' electrically connected to the openings in the protective layer 18, and for forming tin-lead on the two contacts for connecting the upper coils 362. The bump or gold bump may be connected to an external circuit such as a printed circuit board, or a gold wire formed by a wire bonding process may be bonded to the contact. In the present embodiment, the bottom layer coil 36 is formed, for example, on the polymer layer 2G on the protective layer 18, and the material of the polymer layer 2G of the head 9a and 9e is formed as shown in FIG. The material of the polymer layer 2〇 and the method of forming the same. Alternatively, the configuration of the polymer layer 2〇 may be omitted, and the underlying coil 36〇 may be directly contacted to be formed on the protective layer 18 as shown in the figure and 9d. After forming the bottom layer coil 360 on the protective layer 18 or on the polymer layer 2, the polymer layer 5G may be formed on the bottom layer _36, as shown in Figures 9a-9d. If it is applied to a process that does not require high precision on the line, the polymer I% material f and the formation method can be referred to the material and formation method of the polymer layer 2〇 shown in Fig. 1b, at which time the polishing process can be omitted. 'But the upper surface of the polymer layer% miscellaneous lanthanum is formed by:,, and the upper layer coil 362 formed later is formed on the uneven upper surface of the polymer layer 5〇: the upper layer coil 362 cannot reach a very high level. Accuracy, such as _% and location = if the application is on a high-precision process, the material and shape of the polymer layer 5 can refer to the material and formation method of the polymer layer 222 as shown in FIG. The mechanical polishing or chemical mechanical polishing process can planarize the upper surface of the polymer layer 505 I331788 MEG 04-014TW-R, since the upper layer coil 362 formed later can be formed on the flat upper surface of the polymer layer 50, The upper coil 362 can achieve higher precision, as shown in Figures 9c and 9d. After the underlying coil 360 is formed on the protective layer 18 or on the polymer layer 2, = to form the polymer layer 70 on the upper layer coil 362, as shown in Figures 9a-9d, the opening 77 in the polys layer 70 can be Exposing the two contacts for connecting the upper layer 3 phantoms, by forming tin-lead bumps or gold bumps on the contacts, the upper layer coil 362 can be connected to an external circuit such as a printed circuit board, or by wire bonding The gold wire formed by the process can also be bonded to this joint. For the material and formation method of the polymer layer 7〇, reference may be made to the material and formation method of the polymer layer 2〇 shown in FIG. 1b, in which case the grinding process can be painfully removed, but the polymer layer 7 has a relatively uneven upper layer. The surface is shown in Figures 9a and %. For the material and formation method of the polymer layer 5, reference may also be made to the material f and the forming method of the polymer layer 222 as shown in Fig. iff. At this time, the mechanical grinding or chemical mechanical polishing process can planarize the upper surface of the polymer layer 5G5. As shown in Figure 9d. Figures 1a to 1c illustrate a cross-sectional green view of a capacitive element = in accordance with the present invention, the capacitive element being tied to the layer 18 or layer 2. The capacitor element has a lower electrode 342, a capacitor dielectric layer and an upper layer = 345, wherein the upper electrode 345 and the lower electrode 342 are fabricated by using a metal line process such as ^ 2a-2f or FIG. 2 > 2k , or both use the metal line process as shown in Figure 21-2m; or, the lower electrode 342 is made, for example, _如® 2 or Figure 2 asks the pillow Jinguan Road process, and 345, the production method is as It is to use the figure shown in Fig. 2g or the figure; or, the manufacturing method of the lower electrode M2 is, for example, the metal line process of the paste as shown in Fig. 2 or Fig. 2, and the manufacturing method of the upper electrode 345 is Use the metal circuit process shown in Figure _. Capacitor dielectric layer such as ^ chemical vapor deposition or physical vapor deposition, capacitance dielectric layer material = ratio 32 1331788

MEG 04-014TW-R

Such as titanium dioxide (Ti〇2), tantalum pentoxide (Ta2〇5), high molecular polymer, nitrogen bismuth compound (Si#4) or oxonium compound (si〇2), tetraethyl oxoxane ( TE0S), titanate (SrTi〇3), etc., and the thickness of the capacitor dielectric layer 346 is, for example, between 5 〇〇 and 5 〇〇〇〇. In this embodiment, the lower electrode 342 is formed on the polymer layer 20 on the protective layer μ, as shown in FIG. 10b and FIG. 2c, wherein the material and formation method of the polymer layer 2 can be referred to as The material of the polymer layer 2〇 shown in FIG. 1b and the method of forming the layer 2, or the configuration of the polymer layer 2〇 may be omitted, and the lower electrode 342 is formed in contact with the protective layer 18, as shown in FIG. In the embodiment, a polymer layer may be selectively formed on the upper electrode 45 of the capacitor element to protect the capacitor element. The method of forming and forming the polymer layer can be illustrated. The material and formation method of the polymer layer 20 shown. 10a to 10c, the electrode phantom and the upper electrode of the capacitor element are connected to the electrical interface exposed by the opening in the protective layer 18 (6). However, the electrical pad 16 of the present invention, Or, the upper electrode of the capacitor element: 5 is an electrical pad 16 exposed by the opening in the 18th day, and the capacitor part 42 is connected to the lead through the tin-lead bump, the gold bump ^ The external miscellaneous road, the section (4) connects the electrical contact exposed by the wire of the ^_ into the wire, or the embossed layer of the electro-textile layer 8 ^ openings are transmitted through the _ bump, the gold convex line and the uniform 45 Connected to the external circuit, Ke is connected down to the external electrical pad 16 of the Lay conductor. The opening of the opening is formed on the surface protective layer 18, and between the 70 pieces of the valley and the casting substrate 1 as shown in FIGS. 10a to 10c', since it is electrically and away from the semiconductor substrate 1, the electricity can be reduced. 1331788

MEG 04-014TW-R Parasitic electricity ^. Further, by the above process, the electrodes 342 and 345 of the capacitor element having a large thickness and a large area can be formed, so that the resistance values of the two electrodes 342 and 345 of the capacitor element can be reduced, which can be applied particularly in the field of wireless. Referring to FIG. 1b and FIG. 2〇c, the polymer layer 2 can be formed on the protective layer 18, and through the patterning process, the opening of the thick polymer layer 20 can be exposed to the electrical pad>16 . In one embodiment, the maximum lateral dimension of the opening of the polymer layer 2 is less than the largest lateral dimension of the opening of the security layer 18, and the polymer layer 2 is covered by the electrical pads 16 exposed to the protective layer 18. A portion of the area outside the opening, as shown in Figure 10b. However, in another embodiment, the most lateral dimension of the opening of the polymer layer 2 is greater than the maximum lateral dimension of the opening of the protective layer 1S, and the opening in the polymer layer 20 exposes the electrical pads. 16 is exposed to all areas outside the opening in the protective layer 18. By the configuration of the polymer layer 20, the arrangement of the capacitor elements can be shifted upward by a distance equal to the thickness of the polymer layer 20, so that the capacitor element can be disposed farther away from the semiconductor substrate 1, so that the capacitor element can be greatly reduced. The parasitic capacitance between the lower electrode 342 and the semiconductor substrate 1. 11a-11c illustrate cross-sectional schematic views of a resistive element formed on a semiconductor wafer, the resistive element 448 being formed on the protective layer 18 or on the polymer layer 2''. The resistor element 448 is made of a material that can provide an electrical resistance value and the current can flow through the material. The resistive element 48 can be formed by physical vapor deposition or chemical vapor deposition, and the material of the resistive element 48 is, for example, a nitrogen compound (TaN), a nickel-chromium alloy (NiCr), a nickel-tin alloy (NiSn), or a tungsten (W). ), titanium tungsten alloy (TiW), titanium nitride compound (TiN), chromium (Cr), titanium (Ti), nickel (Ni) or bismuth compound (TaSi). In these materials, the 'recording alloy' can provide a superior temperature coefficient of resistance, which can be as small as 5 ppn]/0c. The length, thickness and width of the resistive element can be designed for different applications. Referring to lib and 11c, after forming the polymer layer 20 on the protective layer 18, the resistive element 448 can be formed on the polymer layer 20, and the resistive element 48 can pass through 34 1331788.

The electrical interface of the MEG 04-014TW-R in the polymer layer 20 is exposed to the opening in the protective layer 18. The material and formation method of the polymer layer 20 can be referred to as shown in FIG. The material and formation method of the polymer layer 20 shown. The distance between the resistive element 448 and the semiconductor substrate 1 can be increased by the configuration of the polymer layer 2 (the increased distance is substantially equal to the thickness of the polymer layer 20), and the relationship between the resistive element 48 and the substrate 10 can be reduced. The parasitic capacitance effect can improve the performance of the resistive element (since the loss of parasitic capacitance can be reduced), so the electrical performance under high frequency operation can be improved. However, the configuration of the polymer layer 20 can also be omitted, and the resistive element 448 is formed in direct contact with the protective layer 18 as shown in Fig. 11a. Further, a polymer layer may be selectively formed on the resistive element 448 to protect the resistive element 448. Referring to lla-llc, the two contacts of the resistive element 448 are connected to the electrical pads 16 exposed by the openings in the protective layer 18; however, the application of the present invention is not limited thereto, and may be One of the contacts of the resistive element 448 is connected to the electrical pad 16 exposed in the opening of the protective layer 18, and the other contact is formed by a tin-lead bump, a gold bump or a wire bonding process. The wire bonding wire is externally connected to the external circuit, and is not connected to the electrical interface exposed by the opening of the protection 18; or the two contacts of the resistive component 448 can pass through the tin bump, gold The bumps or the wire of the wire-cutting process are externally connected to the external circuit, and are not connected to the electrical pads 16 exposed in the openings of the protective layer 18. Referring to Figures i2a and 12b, there is shown a schematic diagram of a passive π-piece bonded to a semiconductor wafer in accordance with one embodiment of the present invention. In this embodiment, the solder 452 can be formed on the electrical interface, so that the electrical interface can be connected to the completed passive component 454 through the solder 452, wherein the device 454 is Inductive components, capacitive components, exhibitors, or other passive components that have been fabricated. A metal layer 45 can be formed on the electrical interface 16 exposed by the opening in the protective layer. The solder can be formed on the metal layer by a conventional ball or screen printing process. Lord at 35 1331788

MEG 04-014TW-R When the finished electronic component 454 is bonded to the solder 452, the flux can be sprinkled onto the solder 452, and the finished electronic component 454 can be fabricated by a reflow process. The solder 452 is bonded. The fabricated electronic component 454 can also have solder 453, which can improve the bond between the fabricated electronic component 454 and the underlying semiconductor wafer. Referring to FIG. 12a and FIG. 12b, when the solder 452 is completed by an electroplating process, an adhesion/barrier layer such as titanium or chromium may be formed on the semiconductor wafer by sputtering, and then the sputtering method may be used. Forming a seed layer such as copper on the adhesion/barrier layer, and then forming a photoresist layer on the seed layer, wherein the opening-opening π in the photoresist layer exposes the seed layer, and then can be plated. Forming a copper layer on the seed layer exposed by the opening in the photoresist layer, and then forming a nickel layer on the copper layer by means of an electric clock, and then forming a solder by using electroplating - layer 452 On the nickel layer, the thickness of the solder layer 452 is, for example, between about 5 micrometers and -500 micrometers, and the material of the solder layer must be 2, such as tin-lead alloy or tin-silver alloy. Thereafter, the photoresist layer can be removed, and then the seed layer and the adhesion/barrier layer not under the patterned solder layer 452 can be removed. In this embodiment, the metal layer 450 is composed of an adhesion/barrier layer, a seed layer, and a copper layer and a nickel layer formed by electroplating, and the thickness of the metal layer 450 is, for example, 〇.丨micron to 2 〇 between microns. Referring to FIG. 12a and FIG. 12b, when the solder 452 is completed by a screen printing process or a ball-and-ball process, an adhesion/barrier layer such as titanium or chromium may be formed on the semiconductor wafer by sputtering. Then, a seed layer such as copper is formed on the adhesion/barrier layer by sputtering, and then a photoresist layer is formed on the seed layer, and an opening in the photoresist layer may expose the seed layer. Then, a copper layer can be formed on the seed layer exposed by the opening in the photoresist layer by using electric money, and then a nickel layer can be formed on the copper layer by electroplating, and then a plating method can be used to form a copper layer. The gold layer is on the nickel layer, after which the photoresist layer can be removed, and then the seed layer and the adhesion/barrier layer not under the patterned copper layer, the nickel layer and the gold layer can be removed. At 36 1331788

MEG 04-014TW-R In this embodiment, the metal layer 450 is composed of an adhesion/barrier layer, a seed layer, and a copper layer, a nickel layer and a gold layer formed by electro-mineralization, and the thickness of the metal layer 450 is as It is between 0.1 microns and 20 microns. Thereafter, a solder layer 452 may be formed on the gold layer of the metal layer 450 by a screen printing process or a ball bonding process, and the thickness of the ten solder layer 452 is, for example, between about 5 micrometers and 300 micrometers, and the solder layer 452 is The material is, for example, tin-lead alloy or tin-silver alloy. In this embodiment, the gold layer of the metal layer 50 for connecting the solder layer 452 is not too thick, for example, between 微米5 μm and i μm, so that the gold layer of the metal layer 50 is prevented from being excessively diffused. In the gold to solder layer 452 'this can avoid the brittleness problem caused by the tin-gold alloy.曰 Next, the circuit design made using the thick metal layer on the protective layer will be detailed. Please refer to heads 13a-13c for the line structure for distributing the supply voltage or grounding. The semiconductor wiring 12 is formed on the surface layer of the semiconductor substrate, and these semiconductor elements 12 may be nmos elements, PM 〇 s elements, and CM 〇 s elements. Each half of the conductor, component 12 has a variety of nodes, can be connected to other lines _ to connect the power supply voltage (Vdd) or ground voltage (Vss) power / ground line, a typical semiconductor component I2 contains power nodes, ground nodes and signal nodes . The electrostatic discharge protection line μ4 is formed on the surface layer of the semiconductor substrate i, and the semiconductor element U is damaged by the breakout = electrostatic discharge. The semiconductor element 12 and the electrostatic discharge protection line 544 are both formed in the element layer 2. On the 1C circuit layer 3 series cake element layer 2, the 561 system of the 1C circuit layer 32 and the semiconductor element 12 and the electrostatic discharge protection line 544 are layered 4 on the Ic circuit layer 3, and the opening in the tilt layer 4 can be The electrical pad of the circuit 1C and the circuit layer 3, in this embodiment, the semiconductor wafer structure under the protective layer 4 in FIG. 1A = the rear protective layer 8〇 structure of the structure of the egg and the thick polymer layer In the protective layer 4 (four) phase structure and production method can be used for the test 1b (4), the sound of the ^ ^ ^ and see the connection network 566, for example, one or more layers of thick gold, thick and wide connection The network 560 is formed in direct contact, for example, in the security 37

MEG 04-014TW-R 2 4 is 'on or formed on the thick polymer layer on the protective layer 4, the thick and wide system is connected to the financial IC layer 3 (10), the internal wiring 56, the electrostatic discharge f can pass through the thick and wide The connection network 566 is connected in parallel to the source node 'the thick and wide connection network 566 such as the power plane; or the connection network 566 through which the ESD protection circuit M4 can be connected in parallel Connecting a plurality of semiconductor lines to ground H is a point, wherein a thick and wide connection network 566 such as a ground bus or a volt map 13 & and FIG. 13 brook bump or gold bump can be formed in Thick and wide (10) one or more of the contacts 568' makes the thick and wide connection network grounded to be connected to the power supply or the line of the external circuit such as the printed circuit board. The wire of the job can be fed in a thick and wide connection can be tw: $ or 夕 contacts 568' to make a thick and wide connection network 566 Cheng shield connected to the external circuit such as the printed circuit board Terminal or grounding ^ thick and wide wiring network 566 is distributed through the power supply terminal connected to multiple points or The end, can be made thick and wide network connection 566 more stably electrically iv Xun source ground voltage. In the present invention, different electrostatic discharge protection lines 544, that is, an electrostatic discharge protection line (10), may be separately connected to each of the two connection ports 568 of the power supply or the connection of the external ground source. Electrically connected to a plurality of pads 568 for external power supply connection or electrically connected to the mat, an external ground source connection pad S68, a plurality of external power supply connections or a plurality of pads 568 connected to an external ground source. A = protection line 544' can be shared together so that power loss due to the electrostatic discharge force can be reduced. The electric kiss referenced by the 13c' position in the opening in the protective layer 4 is exposed to the electrical network through a protective layer 4, one of the thin film lines is electrically connected to a thick and wide connection, 'circumference path 566, tin lead Bumps or gold bumps can be formed on this electrical pad % to wire ^31788

The wires formed by the MEG 04-014TW-R process can also be bonded to the electrical pads 16. The thick and wide connection network 566 is not directly electrically connected to the external circuit, but is electrically connected to the external circuit through the thin film line 98 located under the protective layer 4. The winding length of the thin film line 98 is, for example, Between 50 microns and 1 〇〇〇 microns. It is worth noting that after making a wide and thick interconnect network 566, the electrical pads 16 are still exposed. Referring to FIG. 13b'1C, the circuit layer 3 further includes a plurality of interconnect networks 567, which are located under the security layer 4, and the plurality of semiconductor components 12 can be connected through the interconnect network 567, and the plurality of interconnected networks 567 can be connected by a thick and wide connection network 566 located on the protective layer 4. Portions of the semiconductor component 12 can be connected to the thick and wide wiring network 566 located on the protective layer 4 via the interconnect network 567 located under the protective layer 4. However, the application of the present invention is not limited thereto, and all of the semiconductor components may be connected to the thick and wide connection network located on the protective layer 4 by the interconnect network located under the protective layer 4. Road 566 is shown in Figures 13a and 13c. Referring to FIG. 13a to FIG. 13c, the thick and wide connection network 566 disposed on the protective layer 4 can replace the thin and thin interconnections under the protective layer 4 in the prior art.疋As a metal connection or wire of the power supply or ground bus, so some of the thin interconnects can be removed, so the low parasitic capacitance of the semiconductor component is: 曰' and is formed on the protective layer 4 and The wide connection network is more able to withstand the impact of external voltage changes. In the present invention, the thick wire connection network 566 passing through the protective layer can be connected in parallel to the electrostatic discharge protection circuit 544 and the plurality of parts 12' due to the connection on the protective layer 4. The line network 566 is thick and wide, thereby reducing the occurrence of unintended power surges. In the embodiment t, when the power supply or the grounding node of the semiconductor wafer connector component of the present invention is externally powered, the external Ρ grounding pad may not be in position with the de-conductor chip yelling at the other semi-conductor 39 1331788

Meg 04-014TW-R The electrostatic discharge protection circuit of the body crystal is electrically connected, and the projection is directly connected to another semiconductor wafer; == or at the it===== and the semiconductor wafer Internal connection. Often electrostatic discharge protection line power such as ii=, 14r4h, thick and wide connection network on the protection layer 4 tearing signal, etc.: address signal, data signal, logic signal or class = I, etc., typical + The conductor element comprises a power supply node, the grounding is connected to the semiconductor such as 2, and the wide connection network 566 can also transmit the power/ground current from the voltage. The semiconductor circuit 12 is formed. In the element output line 545 and other semiconductor elements 12 are formed in the element layer 2, the electrostatic discharge protection line 5 12 is damaged by the curry discharge, and the inner connection line 561 of the circuit layer 3 is lined up. On the element layer 2, the Φ circuit 544 and the driver circuit, the connection - + 12, the electrostatic discharge protection wire protection layer 4 are deposited on the IC circuit layer 3 on the line 545. Bao K: the electrical pad of the circuit layer 3, The opening of the present invention can expose a t-body slab of a semiconductor wafer junction layer and a thick polymer layer under the underlying layer 4 of the protective layer 4 in FIG. 1A. The detailed structure and production of Jin Hu (4) are on the protective layer 4, the rear structure and the production method. The layer (10) and the thick layer of the layer shown in FIG. 3 or the thick layer of the metal layer, and the connection network 566 of the f is formed, for example, by a contact-connection in the protection of the reed 4 t. 566 is, for example, a direct layer, a thick and wide thick polymer layer on the i-network sheath 4, which is connected to the interconnect in the 1C circuit layer 3, 1331788

MEG 04-014TW-R. The electrostatic discharge protection line S44 is a fine parallel circuit, receiver line or input/output line 545. Referring to Figures 14a-14d, the rear cover 80 is connected to the opening of the layer, and a tin bump or gold bump can be formed on the port 57, so that the half is "It can be electrically connected to the circuit of the cake; or it can be joined by the method of bonding. The semiconductor wafer can be connected to the external circuit, and the 544 is electrically connected to the external circuit." In this way, it is possible to avoid damage to the line in the +conductor day when the non-pre-marriage occurs. The processing from the external circuit via the pad 57 a clock signal or other signal through the receiver line 545 can be used. The wide and thick interconnect network on the protective layer 4 is redistributed to the plurality of semiconductor components 12; and the signal output from the semiconductor component 12 can be transmitted through the protected sound 4 ΐίΐ and the thick interconnected network The 566 is then transmitted to the chicken line 545, and after being amplified by the driving 545, it can be transmitted to the outside via the port 57. It is worth noting that the wide and thick interconnect network 566 is not electrically connected externally. The length of the winding between the pads 170 to the driver, receiver or output/input line 545 can be from the length of the winding between the pads 57 to the ESD protection line 544, where the fJ70 is connected to the driver, receiver or output. The winding length ratio between the input line and the input line μ5 is between 1 〇〇 micrometer and 1 cm. Further, the distance between adjacent pads 57A is, for example, between 100 microns and 1 cm. Referring to FIGS. 14e-14h, the electrical pads 16 exposed in the openings in the protective layer 4 are formed of tin bumps or gold bumps, so that the semiconductor wafer can be electrically connected to the Xijie Road. Or the wire bonding wire formed by the wire bonding process can be electrically connected to the semiconductor chip to electrically connect to the external circuit. The electrostatic discharge protection circuit 544 is electrically connected to the circuit connected to the electrical pad 16, so that damage caused by the in-progress area semiconductor crystal line can be avoided. A clock signal or other signal transmitted from an external circuit via the electrical pad 16 1331788

The MEG 04-014TW-R can be redistributed to the plurality of semiconductor components 12 via the interconnect network 566 on the protective layer 4 after processing by the receiver circuit 545; and the signal is protected from a semiconductor component. The width and thickness of the layer 4 is transmitted to the drive read path 545' and is transmitted to the outside via the hybrid pad 16 after being amplified by the driver circuit 545. The value of hiding is that the wide and thick interconnected 566 system is not electrically connected to the outside, and after the width and thickness = 哭 cry = 66, the electrical interface 16 is still exposed. The length of the winding between the electrical pads ΐ6 to 2, the receiver or the output/input line 545 may be longer than the length of the winding between the electrical galvanic protection lines 544, wherein the electrical pads are slightly thinner. The length of the winding between the output or input/output line 545 is, for example, between 100 rpm. In addition, the distance between adjacent electrical pads 16 is between, for example, between 1 cm and 1 cm. The edge network 3^6;, Md, (4), and 1<: the circuit layer 3 further includes a plurality of thick and wide connection networks 566 connected to the security layer 4 to connect the circuit 567. A portion of the semiconductor component 12 can be connected to the thick and wide wiring network $ located on the protective layer 4 without passing through the protective layer 56I: f-wire bypass 567. However, the application of the present invention is not limited thereto, and it is also possible that all of the semiconductor elements are connected by an interconnecting network located under the protective layer 4 to a wide and wide connection on the protective layer 4. Network 566 is shown in Figures 14a, 14c, ... and Mg. Til fruit ^ connected to the county magistrate and / or __ (netafdrcuitsM load is under the rail, the wafer pair __ or receiving (four) things _ a r re ^ eiver) may be necessary, as shown in Figure Mc, (4) The chip-to-input driver or receiver 58G is used to process the money transfer between the receivers in the wafer, or to process the chip external drive or receive the 545 and semiconductor components. Inter-signal transmission, slice external driver or receiver 545 is used to process the chip internal drive or receive = 42 (S) 1331788

Signal transmission between the MEG 04-014TW-R 580 and an external circuit. These chip-in-chip drivers or receivers 580 are typically smaller than the chip external (〇ff_chip) driver or receiver 545, and the intra-chip driver or receiver 580 has a smaller sense amplifier (sensing-lifier). ), a small shackle input line (latchedMput - dipole ^ small cascade circuit (cascade stage). In terms of the ability to detect signals, the sensitivity of the receiver will be affected by the sense amplifier, shackle input line or series circuit The chip-to-in-chip driver or receiver 580 does not have an ESD protection line and an input/output line. However, for short-distance intra-wafer wiring, an internal driver or receiver may not be required, as shown in the figure. 4a, FIG. 4, FIG. 4e and FIG. 4f. The community, the diagram (10), the diagram i4g and the diagram 14h, in the same-semiconductor wafer, or the processing of the receivers % and 580 transmits the ί 或 或 界 circuit; Or the transmission of the signal can be transmitted to the semiconductor component u via only the transfer of the second-order or the dynamic H 545, as shown in Fig. 4a, Fig. 4b, Fig. 4e and Fig. 4f. , the edge shows two drives, The receiver or input/round-out line % is connected by a thick and awkward connection network 566 to make = to every = same ^ = width:: line 566 to connect two 12. Driver, connector or input / The wheel 炙 V V V body 7 可 can be: After: the layer 70 in the object 70 is connected to = electric protection line 544 In addition, the use of the protection layer 4 on the previous drive, receiver or wheel / wheel ^ H ^ 566 The multi-discharge protection circuit 544 can be connected to one or more electrostatic discharge lines M5 and two electrostatics, receivers or wheel/wheel low impedance multiple thick and wide interconnection networks. The road passes through the device or the transmission on the protective layer 4, and the line passes through the protective layer (S) 43 1331788

The MEG 04-014TW-R is connected to the internal wiring line 12. Referring to FIG. 15a to FIG. 15d, a plurality of broad and thick connection networks on the de-layer 4 are spliced in the present cow ^=over=the protective element 12 does not need to be widened. And the thick connection network 566 ^ to the outer wide and thick connection network 566 connection, wide and thick connection _ for the time = number. Tree Transmission (4) No special receiver or driver is provided to handle the 之间 between the material elements 12

^ 2 wide and thick wired network 566 does not need to be electrically connected to the semiconductor read I2 via the receiver or driver 3, as shown in Figure 1Sa and illustrated. If it is ^12 _ transmission distance is very far 'component layer 2 can provide receiver or drive to ίί body 12 between the signal transmission, at this time the thick _ road tearing is sitting by the receiver or driver 580 electrical Connected to the semiconductor component 12, as shown in Figures 5β and 15d, the receiver or driver 58 is less than a receiver or driver typically used for processing signals between the external circuitry and the external circuitry. One. Referring to Figures 15b A 15d, the 1C circuit layer 3 further includes a plurality of interconnect network 567, 'positioned under the tilt layer 4, and the plurality of conductor elements 12 are connectable via the interconnect network 567, located in the protective layer 4. The thick and wide connection network 566 is connected to the interconnect network 567. Portions of the semiconductor component 12 can be connected to the thick and wide wiring network 566 located on the protective layer 4 via the interconnect network 567 located under the protective layer 4. However, the application of the present invention is not limited thereto, and it is also possible that all of the semiconductor elements 12 are not connected to the thick and wide wiring network located on the protective layer 4 via the interconnect network positioned under the protective layer 4. Road 566 is shown in Figures 15a and 15c. Figure 16 illustrates the transmission of a signal from semiconductor component i2a to another semiconductor component 12b using a series of drivers/receivers 601, 602 or converters 〇3 (transceiver). Through a series of repeaters or converters 603 and a thick and wide connection 666 on the protective layer 4, the two semi-guide elements i2a 1331788 can be separated by a distance.

MEG 04-014TW-R ^ = signal transmission between. A repeater or converter - generally includes a revenue 602 and a driver 601. The line under the protection layer 4 can still connect the receiving pirate 6 〇 2 and the driver 6 〇 1 through the bit. A thick and wide connection in the protective layer 4. The semi-conductive signal is processed by the driver 611, and can be connected via a bit m wide, a line 666 to a series of repeaters or a thick and wide connection 666 on the protective layer 4. After the processing of the device 612, the signal can be transmitted to the ===? The semiconductor wafer structure under the protective layer 4 can refer to the back layer of the structure of the thick polymer layer of the semiconductor wafer under the protective layer 4 in FIG. 1A. The 8G system can be formed on the protective layer f. The thick and wide lines in the back layer 80 can be formed by the phase 1b and the == and = ^ ' shown in Fig. 3_, for example, by one or more layers of 666, such as direct contact. ^Protection 9 or formed on a thick polymer layer on the protective layer 4. In the case of a wafer winding design in which the electrical connection between the semiconductor elements is changed, when the system is less than D, the driver or the driver and the thick and wide line are required to be connected. After the actuator or receiver is connected to the half-belt, the fish-connected small driver or receiver means less than the general and external circuits to the ESD protection circuit and the input/wheeling circuit. The following thick protective layer has the best _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 74 〇 is a thin film dielectric layer, label 45

Cs)

The meg 04-014TW-R No. 741 is the second line of the thin film metal layer and is located on the thin film dielectric layer. The polymer layer 742 located on the protective layer 1S can refer to the material of the polymer layer 2〇 illustrated in FIG. 1b and the manufacturing method. The thick metal layer M3 is in the polymer layer. On the 42nd, the detailed structure of the county can be transferred to the detailed structure and formation method of the thick metal layer shown in Figure Wg and 2. Please refer to the figure Π 'The thick and wide metal line 743 on the protective layer ls in the present invention (in this embodiment, 'is composed of an adhesion/barrier layer, a seed layer and one or more layers of plated metal layers) The thickness t2 is thicker than the thickness t1 of the thin interconnect 741 of the metal layer under the pour layer 18, and the multiple of the thickness is between about 2 and 2 times. This thick and wide metal wiring 743 is formed as a connecting line, and its width W is also between 2 and 1,000 times wider than the width w1 of the thin film gold-like wire 741 to which it is connected. The thick and wide metal line 743 has a thickness t2 of between about 2 microns and 100 micro-productions, a width Μ greater than or equal to 2 microns, and a line spacing C greater than or equal to 2 microns' and a thick and wide metal line 743 can have a lower thickness. The resistance value. ΓImplementation Office 'Please refer to _17, Cong riding 18 under the structure, the thickness of the metal wire is about 2 microns, the width is about two meters, the thickness of the film two electrical layer 740 is about 2 microns , the line spacing si is about the working meter, the film is tight] 74 〇 is the dioxide eve; in terms of the structure on the protective layer 18, the metal line is 5 microns, the width W2 is about 10 microns, the dielectric layer The thickness of 742 is 5^: 5 μm, the line spacing s2 is about 1 μm, and the dielectric layer μ is polyimine. Under the tti piece, the resistance of the metal line 743 on the m and * can be made due to the difference in the thickness of the metal line 743 on the protective layer 18 of the protective layer. The resistance value of the metal line (4) under the thin film metal layer under the protective layer 18 can be 2 times smaller than that of the metal line (4). After the above condition & 5 layer, the metallurgical structure of the sheath metal layer is 6.25 times, or about 5 times larger than the resistance and capacitance product of the wiring metal layer under the protective layer. In the other example, please refer to Figure 17' for the structure under the protective layer 18, 1331788

MEG 04-014TW-R Thin film metal layer connection line 741 is 10 microns thick, thin film dielectric layer 740 is thick dl, width (about tT, ZlXtlV7' ^w2 10^ fine internal connection metal line 741 and protective layer The difference is that the metal on the protective layer 18 can be made; the π genus line ^743 is connected to the metal line 74 in the thin metal layer below the thickness of the metal line 74 == layer α, so 'under the above conditions' can be made on the protective layer After that, the thin layer of the film is connected to the other layer. In addition, the thickness of the film dielectric layer 740 is about 0.2 μm 0.2 μm, and the thickness of the thin film dielectric layer 740 is about 〇 = ^ 0.2 ^ 74〇; ^ In terms of structure, the thickness U of the metal line 743 is about 5 microns, the width w2 ^ m, the thickness d2 of the dielectric layer 742 is about 5 microns, the line spacing & about (7) (four), the human body layer 742 It is a polyimine. Under the above conditions, due to the thickness of the protective layer, the value of the metal line on the protective layer ls can be the value of the metal line of the thin metal layer under the J 18 Small ^ 18 times. In ίίϊΓ 'Therefore, the protective layer 18 has a back cover metal structure than the protective layer under the thin film metal layer The resistance-capacitance product value of the thin connection line is less than 2 times. In another embodiment, in terms of the structure under the protective layer 18, the thickness of the thin film gold: the connection line 741 is about 〇.4 μm, and the width wl is about The thickness dl of the dielectric layer 740 of the 〇 2 μm film is about 〇. 4 μm, the line pitch sl is about 微米 2 μm, and the dielectric layer of the thin film is oxidized; the structure on the protective layer 18 is Words, metal (S) 47

MEG 04-014TW-R Degree: about Μ micron, width W2 is about 10 microns, dielectric sound

The electrical resistance of the metal interconnect 743 on the metal line 743 on the layer 18 is smaller than that in the thin metal interconnect 741 of the metal layer 743. Therefore, under the above conditions, the resistive capacitance i of the protective layer 18 can be made after the protective layer 18 (the metal wire of the StT galvanic metal layer; according to the above discussion, the protective layer 18 has the back protective layer metal structure Between the protection layer 18 = the thin metal layer of the film metal layer, the number of wires is 5 times to 1 〇 _, and the resistance and capacitance product value of the metal structure of the back cover layer on the protective layer 18 can be The dielectric layer 42 on the protective layer 18 is exemplified by the polyaniline #-cyclobutene. Several advantages of the present invention are as follows:

U can improve the resistance-capacitance product of thick and wide metal lines due to the use of thick and wide metal lines (resulting in a drop in resistance) and the use of thick dielectrics in metal connection lines (resulting in a drop in parasitic capacitance) The value can therefore increase the reaction rate of the integrated two signals and improve the performance of the integrated circuit. , < 2) does not need to use the expensive instruments traditionally used in sub-micron integrated circuit manufacturing, nor does it need to be in a more demanding clean room like sub-micron integrated circuits (such as cleanliness of 1 〇 or less) Made in China. On the other hand, the back sheath process of the present invention can be manufactured in an environment with a clean room cleanness of 1 或 or more, and therefore, the manufacturing cost is relatively low. 3) Through the thick metal lines of the present invention on the protective layer, it is easy to integrate the power bus, the ground bus and the clock distribution networks. 4) In the systemized chip (S0C) design, through The present invention is located on the protective layer 1331788

MEG 04-014TW-R =:: The intermediate type is quite far away and has different functions. The second method is: = the soft connection is required. 6) Provide a standard BGA package. = 属 ϋ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Hometown. Use the thick metal line function on the secret layer, the feather connection, reconfigure the pad position, reduce or increase the number of pads to dispose the tin bump, gold bump or wire pad in a suitable place. And the flexibility of the ^^ lower-stage package, especially in the design of the winding of the secret packaging (SIP) and the solar module. 10) Provide a method of distributing the power supply voltage, distributing the ground voltage, and distributing the signal to reduce the number of pins that connect to the external circuit when needed. U) The maximum size of the opening of the protective layer may be between 25 micrometers and 01 micrometers, and a thick metal line on the protective layer may be connected to the thin film metal wiring under the layer through the opening of the protective layer. The thin metal ruthenium hides the thickness of the granules. 13) The function of the BGA connection line is replaced by providing a back-layer metal structure (metal structure on the protective layer) which is thinner than the metal design of the BGA substrate. . Thus, the BGA substrate design becomes simpler and the cost can be greatly reduced. 49

Claims (1)

1331788 Patent Application No. 095135704 Patent Application Replacement (May 99) ___ X. Patent Application 9f I Positive Replacement Page 1 · A wafer structure comprising: a semiconductor substrate; a plurality of metal contacts lie in the semiconductor a protective layer on the semiconductor substrate, wherein the protective layer has a plurality of openings, the openings exposing the metal pads, the protective layer is made of a nitride or an oxide; the plurality of metal bumps are located The protective layer has a total number of such metal bumps less than the total number of the metal pads; and a circuit layer on the protective layer, and the circuit layer includes a thickness of 2 a metal layer between 10 microns, wherein the metal is made of copper, and the metal pads are connected to the metal bumps via the circuit layer. The wafer structure of claim 1, wherein the circuit layer comprises a metal line, and one of the metal pads is connected to the plurality of metal bumps via the metal line. 3. The wafer structure of claim 1, wherein the circuit layer comprises a metal line, and one of the metal bumps is connected to the plurality of metal structures via the metal line. 4. The wafer structure of claim 1, wherein the step further comprises a polymer layer between the protective layer and the circuit layer. 5. The wafer structure of claim i, wherein the circuit layer further comprises an adhesion/barrier layer and a seed layer, the metal layer being on the seed layer. The material of the adhesion/barrier layer comprises Titanium or neon, and the material of the seed layer includes copper. 143022-990512.doc 1331788 Silk replacement page. 6. If you apply for a patent II! The wafer structure of the item, wherein the line month comprises a metal line, and the metal line is used as a distributed power source or a ground voltage. 7. The wafer structure of claim 1, wherein the material of the metal bumps comprises tin or gold. The wafer structure of claim 1, wherein the lateral maximum dimension of the openings is between 〇.丨 microns and 25 microns. 9. A wafer structure comprising: a semiconductor substrate; an integrated circuit (1C) wiring layer on the semiconductor substrate; a germanium layer on the integrated circuit wiring layer and contacting the integrated circuit wiring layer The total number of external contacts on the protective layer is less than the total number of metal pads exposed by the openings in the protective layer, and the lateral maximum dimension of the openings is between 1 micrometer and 25 micrometers. And wherein the external contacts are metal bumps; and a circuit layer is disposed on the protective layer, and the circuit layer comprises a metal layer having a thickness between 2 micrometers and 10 micrometers, wherein the interconnects are externally connected The point is connected to the metal interfaces via the circuit layer. 10. The wafer structure of claim 9, wherein the circuit layer comprises a metal line, and one of the metal pads is connected to the plurality of external contacts β 11 via the metal line. The wafer structure of claim 9, wherein the circuit layer comprises a metal line, and one of the external contacts is connected to the plurality of metal pads via the metal line. 143022-990512.doc 1331788 Λ i , wherein the protection 12. The wafer structure layer of claim 9 includes a nitride or an oxide. 13. The wafer structure of claim 9, wherein the metal layer is made of copper. 14. The wafer structure of claim 9, wherein the circuit layer further comprises an adhesion/barrier layer and a sub-layer on the seed layer, and the adhesion/barrier layer material Includes titanium or button. 15. The wafer structure of claim 9, further comprising a polymer layer between the protective layer and the circuit layer. The wafer structure of claim 9, wherein the wiring layer comprises a metal wiring, and the metal wiring is used for distributing a power supply voltage or distributing a ground voltage. The wafer structure of claim 9, wherein the integrated circuit layer comprises a copper layer and a sulphide/male, and the adhesion/obstruction layer The layer is located below the copper layer and on the side wall of the copper layer. 18. A wafer structure comprising: a semiconductor substrate; an integrated circuit (1C) circuit layer on the semiconductor substrate; a plurality of metal pads on the integrated circuit circuit layer; a protective layer located in the integrated body The circuit circuit layer is in contact with the integrated circuit circuit layer, wherein the protective layer has a plurality of openings, the openings are located on the metal pads, etc., and the maximum size is between micrometers and Μ micrometers. And the material of the protective layer comprises a nitride or an oxide; a plurality of metal bumps are located on the protective layer, wherein the metal bumps are 143022-990512.doc 1331788 ___ · month 5, 3⁄43⁄4 shout! The equal number of the metal pads is less than the total number of the metal pads, and the metal pads are connected to the metal bumps; and a metal line is located on the protective layer, and the metal lines comprise a thickness of 2 micrometers to A metal layer between 1 micron, wherein one of the metal bumps is connected to the plurality of metal pads via the metal line, the metal circuit being used as a distributed power supply voltage. 19. The wafer structure of claim 18, wherein the semiconductor substrate is a "shattered substrate. 20. The wafer structure of claim 18, wherein the metal layer is made of copper. 21. The wafer structure of claim 18, further comprising a polymer layer between the protective layer and the metal line. 22. The wafer structure of claim 18, wherein the metal circuit further comprises an adhesion/barrier layer and a sub-layer, the metal layer is on the seed layer, and the adhesion/barrier layer material Includes titanium or tantalum. The wafer structure of claim 18, wherein the material of the metal bumps comprises tin or gold. 2. The wafer structure of claim 18, wherein the metal bumps are gold bumps. 25. The wafer structure of claim 8, wherein the integrated circuit layer comprises - a copper layer and a material/barrier layer, and the adhesion/obstruction layer is located under the copper layer and on the side wall of the copper layer. 曰26. The wafer junction layer according to the patent application scope is formed by electroplating. ^Metal 143022-990512.doc 1331788 2 7. A wafer structure comprising: a semiconductor substrate; an integrated circuit (1C) circuit layer on the semiconductor substrate; a plurality of metal pads on the integrated circuit circuit layer; a protective layer is disposed on the integrated circuit circuit layer and contacts the integrated circuit circuit layer, wherein the protective layer has a plurality of openings on the metal pads, and the lateral maximum dimension of the openings is between Between 1 micrometer and 25 micrometers, and the material of the protective layer comprises a nitride or an oxide; a plurality of metal bumps are located on the protective layer, wherein the total number of the metal bumps is less than that of the metal pads a total number, and the metal pads are connected to the metal bumps; and: a metal line on the protective layer, and the metal line includes a metal layer having a thickness between 2 micrometers and 1 micrometer And wherein one of the metal bumps is connected to the plurality of metal pads via the metal line, and the metal circuit is used as a distributed ground voltage. The wafer structure of claim 27, wherein the semiconductor substrate is a stone substrate. 29. The wafer structure of claim 27, wherein the metal layer is made of copper. The wafer structure of claim 27, further comprising a polymer layer between the protective layer and the metal line. The wafer junction according to claim 27, wherein the metal circuit further comprises a point/blocking land for the aging layer and a sublayer 'the metal layer is on the seed layer' and the bonding/layer material f includes titanium or a group. 143022-990512.doc 1331788 i 曰 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji ji The material of the crystal bumps as described in claim 27, which includes the tin or gold. 33_ The crystal bumps as described in claim 27 of the patent application are gold bumps. 34. The circuit circuit layer of claim 27, comprising a copper layer and an adhesion/obstruction layer under the steel layer and on the side wall of the copper layer. 35. The crystal layer described in claim 27 is formed by electroplating. 143022-990512.doc