WO2005024914A1 - Semiconductor arrangement with thin-film resistor - Google Patents

Semiconductor arrangement with thin-film resistor Download PDF

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Publication number
WO2005024914A1
WO2005024914A1 PCT/IB2004/051656 IB2004051656W WO2005024914A1 WO 2005024914 A1 WO2005024914 A1 WO 2005024914A1 IB 2004051656 W IB2004051656 W IB 2004051656W WO 2005024914 A1 WO2005024914 A1 WO 2005024914A1
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WO
WIPO (PCT)
Prior art keywords
thin
film resistor
isolation layer
metallization
semiconductor arrangement
Prior art date
Application number
PCT/IB2004/051656
Other languages
French (fr)
Inventor
Wolfgang Schnitt
Original Assignee
Philips Intellectual Property & Standards Gmbh
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Intellectual Property & Standards Gmbh, Koninklijke Philips Electronics N.V. filed Critical Philips Intellectual Property & Standards Gmbh
Publication of WO2005024914A1 publication Critical patent/WO2005024914A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits

Definitions

  • the invention relates to a semiconductor arrangement comprising a thin-film resistor, and to a method of manufacturing a semiconductor arrangement comprising a thin- film resistor.
  • the integration of thin-film resistors on semiconductor substrates enables semiconductor components to be down-sized and manufactured more economically.
  • the patterns of the photosensitive lacquer layer are transferred into the resistive layer by means of etching. After removal of the photosensitive lacquer, the resistive pattern thus obtained as well as the exposed regions of the first isolation layer are covered with a second isolation layer. For contacting a resistor, a further photosensitive lacquer layer is provided onto the second isolation layer and patterned in accordance with the later pattern of the contact holes. After etching and removal of the lacquer layer, contact holes are obtained in the second isolation layer. Besides contact holes to the resistors, also contact holes to the active components are required.
  • WO 95/28004 proposes to cover the resistive layer with a conductive protective layer.
  • a drawback of this method is, however, that further process steps, such as deposition of the conductive protective layer and, if necessary, patterning or removing the protective layer, are required. It is therefore an object of the present invention to provide an improved semiconductor arrangement comprising a thin-film resistor, which can be manufactured in a simple and economical manner.
  • this object is achieved by a semiconductor arrangement having a thin-film resistor, comprising: - a semiconductor substrate, an isolation layer, which is arranged on the semiconductor substrate, a metallization, which is arranged on the isolation layer, and a thin-film resistor which is arranged on specific regions of the isolation layer and of the metallization.
  • the invention further relates to a method of manufacturing a semiconductor arrangement having a thin-film resistor, comprising: a semiconductor substrate, - an isolation layer, which is arranged on the semiconductor substrate, a metallization, which is arranged on the isolation layer, and a thin- film resistor, wherein the thin-film resistor is provided on specific regions of the isolation layer and of the metallization.
  • a photo-etch step comprising the application and patterning of a photosensitive lacquer layer, etching of the isolation layer to produce contact holes to a thin-film resistor and removal of the patterned lacquer layer, can be dispensed with.
  • the method of manufacturing a semiconductor device becomes more economical.
  • the resistance values of the thin-film resistors manufactured by means of this method exhibit a small spread, which can be attributed to the fact that it is not necessary to etch contact holes to the thin-film resistors. Consequently, etching on the resistor bodies does not take place either, and the thickness of the resistor bodies is not changed.
  • a further advantageous embodiment of the method is described in claim 3.
  • Fig. 1 shows a plan view of a semiconductor arrangement in accordance with the invention
  • Fig. 2 is a cross-sectional view of the inventive semiconductor arrangement shown in Fig. 1, taken on the line A-A'
  • Fig. 3 is a plan view of a further semiconductor arrangement in accordance with the invention
  • Fig. 4 is a cross-sectional view of the inventive semiconductor arrangement shown in Fig. 3, taken on the line B-B'.
  • active components such as diodes or transistors are provided on or incorporated in the semiconductor substrate 1 by means of customary processes.
  • Said semiconductor substrate 1 may contain, for example, Si or GaAs.
  • the semiconductor substrate 1 is covered with an isolation layer 2.
  • Said isolation layer 2 may contain, for example, an oxide such as SiO 2 or a nitride such as Si N 4 .
  • contact holes for contacting the active components are etched in the isolation layer 2.
  • a metallization layer containing, for example, Al:Cu, Al:Cu,Si, Al:Si or Cu, is deposited on the isolation layer 2 and in the contact holes.
  • the metallization layer may alternatively comprise a layered structure of, for example, two layers.
  • the first layer, which borders on the isolation layer 2 may contain, for example, titanium, titanium nitride, titanium tungsten or titanium tungsten nitride, and the second layer may contain, for example, Al:Cu, Al:Cu,Si or Al:Si.
  • the metallization layer is patterned by means of customary processes such as wet etching or plasma etching, so that a metallization 3 is obtained which interconnects the active and, if applicable, passive components.
  • the metallization 3 generally is in the form of conductor tracks or stripes.
  • a resistive layer is deposited on the metallization 3 and on the exposed regions of the isolation layer 2.
  • a material which can be deposited such that the edges are properly covered may be, for example, titanium nitride, titanium tungsten or titanium tungsten nitride.
  • the resistive layer is patterned so as to obtain one or more thin- film resistors 4.
  • Fig. 1 and Fig. 2 show a possibility of patterning the thin-film resistor 4.
  • Fig. 1 shows a plan view of a semiconductor arrangement in accordance with the invention.
  • a metallization 3 is present on an isolation layer 2. The Figure does not show the semiconductor substrate 1 with the active components on which the isolation layer 2 is provided.
  • Fig. 2 is a cross-sectional view of the semiconductor arrangement shown in Fig. 1, taken on the line A-A'.
  • the isolation layer 2 is present on the semiconductor substrate 1 which carries the active components (not shown in Fig. 2).
  • the metallization 3 is provided on the isolation layer 2.
  • the thin-film resistor 4 is present on specific regions of the metallization 3 and on specific regions of the isolation layer 2. In this embodiment, the contact surfaces of the thin-film resistor 4 are formed by the overlapping regions on the upper side of the metallization 3 and by the overlapping regions along the inner, vertical edges of the metallization 3.
  • Fig. 2 is a cross-sectional view of the semiconductor arrangement shown in Fig. 1, taken on the line A-A'.
  • the isolation layer 2 is present on the semiconductor substrate 1 which carries the active components (not shown in Fig. 2).
  • the metallization 3 is provided on the isolation layer 2.
  • the thin-film resistor 4 is present on specific regions of the metallization 3 and on specific regions of the isolation
  • Fig. 3 is a plan view of the semiconductor arrangement in accordance with the invention
  • Fig. 4 is a cross-sectional view of the semiconductor arrangement shown in Fig. 3, taken on the line B-B'.
  • the contact surfaces of the thin-film resistor 4 fully cover the metallization 3 used for interconnection purposes.
  • the actual resistor body in this embodiment, is formed only in the areas between two stripe-shaped sections of the metallization 3 where the material of the thin-film resistor 4 borders on the isolation layer 3. To pattern the resistive layer so as to obtain one or more thin-film resistors 4 in accordance with the embodiment of Figs.
  • an etch medium is chosen which attacks neither the material of the metallization 3 nor the material of the isolation layer 2.
  • an etch medium is chosen which must be selective only with respect to the material of the isolation layer 2.
  • a passivation layer (not shown) is provided to protect the metallization 3 and the thin-film resistor(s) 4 from moisture and mechanical loads.
  • the material used in the passivation layer may be, for example, a nitride such as Si 3 N 4 or SiO .
  • PECVD plasma-enhanced chemical vapor deposition
  • ILDs interdielectric layers
  • BCB benzocyclobutene
  • thin-film resistors 4 may be provided at each interconnection level.
  • the resistance value of a thin-film resistor 4 in accordance with any one of the exemplary embodiments can be readily calculated as this value is determined by the width of the resistor body and the distance between the regions of the metallization with which the thin-film resistor 4 demonstrates an overlap.
  • the advantages of the described semiconductor arrangement, wherein the thin- film resistor 4 or the thin-film resistors 4 are provided directly on the metallization 3 used for interconnection purposes, are: a) a photo-etch step can be dispensed with, b) low contact resistance of the thin-film resistor 4 by virtue of large contact surfaces between the thin-film resistor 4 and regions of the metallization 3, c) simple calculation of the resistance value, and d) small spread of the resistance value, which can be attributed to the fact that etching of contact holes to the thin-film resistor 4 does not take place and hence etching on the resistor body does not take place either.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention describes a semiconductor arrangement having a thin-film resistor, said semiconductor arrangement comprising: a semiconductor substrate (1), an isolation layer (29), which is arranged on the semiconductor substrate, a metallization(3), which is arranged on the isolation layer, and a thin-film resistor (4), which is arranged on specific regions of the isolation layer and of the metallization, as well as a method of manufacturing said semiconductor arrangement. The semiconductor arrangement comprising such a thin-film resistor has a low contact resistance. Furthermore, the semiconductor arrangement can be manufactured in a simple and cost-effective manner, which can be attributed to the fact that one etching step can be dispensed with.

Description

Semiconductor arrangement with thin-film resistor
The invention relates to a semiconductor arrangement comprising a thin-film resistor, and to a method of manufacturing a semiconductor arrangement comprising a thin- film resistor. The integration of thin-film resistors on semiconductor substrates enables semiconductor components to be down-sized and manufactured more economically. The manufacture of a resistor, which is a component of an integrated circuit, nowadays generally takes place in the following manner: Firstly, a first isolation layer is applied to a semiconductor substrate. This step was preceded by the incorporation, in known manner, of one or more active components into the semiconductor substrate. A resistive layer is applied to the isolation layer. To pattern said resistive layer, a photosensitive lacquer layer is applied and patterned in accordance with the later pattern of the resistive layer. The patterns of the photosensitive lacquer layer are transferred into the resistive layer by means of etching. After removal of the photosensitive lacquer, the resistive pattern thus obtained as well as the exposed regions of the first isolation layer are covered with a second isolation layer. For contacting a resistor, a further photosensitive lacquer layer is provided onto the second isolation layer and patterned in accordance with the later pattern of the contact holes. After etching and removal of the lacquer layer, contact holes are obtained in the second isolation layer. Besides contact holes to the resistors, also contact holes to the active components are required. In practice it has proved to be difficult, however, to create these contact holes in the same process step as the contact holes to the resistors without causing damage to the substrate and/or the resistive layer, since to form the contact holes to the active components it is necessary to etch through two isolation layers, and to form the contact holes to the resistors only one isolation layer has to be etched through. A further problem may be encountered after etching, during removing the lacquer. Customarily, the lacquer is removed by means of a liquid. Lacquer particles suspended in the liquid, however, may adhere to the substrate and/or the resistive layer and thus cause damage or problems in subsequent process steps. These two things may adversely affect the quality of the semiconductor component.
To preclude, for example, damage to the resistive layer, WO 95/28004 proposes to cover the resistive layer with a conductive protective layer. A drawback of this method is, however, that further process steps, such as deposition of the conductive protective layer and, if necessary, patterning or removing the protective layer, are required. It is therefore an object of the present invention to provide an improved semiconductor arrangement comprising a thin-film resistor, which can be manufactured in a simple and economical manner. In accordance with the invention, this object is achieved by a semiconductor arrangement having a thin-film resistor, comprising: - a semiconductor substrate, an isolation layer, which is arranged on the semiconductor substrate, a metallization, which is arranged on the isolation layer, and a thin-film resistor which is arranged on specific regions of the isolation layer and of the metallization. By virtue of the large contact areas between the thin-film resistor and the metallization, such a semiconductor arrangement has low contact-resistance values. The invention further relates to a method of manufacturing a semiconductor arrangement having a thin-film resistor, comprising: a semiconductor substrate, - an isolation layer, which is arranged on the semiconductor substrate, a metallization, which is arranged on the isolation layer, and a thin- film resistor, wherein the thin-film resistor is provided on specific regions of the isolation layer and of the metallization. With the aid of this method, a photo-etch step comprising the application and patterning of a photosensitive lacquer layer, etching of the isolation layer to produce contact holes to a thin-film resistor and removal of the patterned lacquer layer, can be dispensed with. By virtue thereof, the method of manufacturing a semiconductor device becomes more economical. Furthermore, the resistance values of the thin-film resistors manufactured by means of this method exhibit a small spread, which can be attributed to the fact that it is not necessary to etch contact holes to the thin-film resistors. Consequently, etching on the resistor bodies does not take place either, and the thickness of the resistor bodies is not changed. A further advantageous embodiment of the method is described in claim 3. These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiment(s) described hereinafter.
In the drawings: Fig. 1 shows a plan view of a semiconductor arrangement in accordance with the invention, Fig. 2 is a cross-sectional view of the inventive semiconductor arrangement shown in Fig. 1, taken on the line A-A', Fig. 3 is a plan view of a further semiconductor arrangement in accordance with the invention, and Fig. 4 is a cross-sectional view of the inventive semiconductor arrangement shown in Fig. 3, taken on the line B-B'.
To manufacture a semiconductor arrangement in accordance with the invention, first, active components such as diodes or transistors are provided on or incorporated in the semiconductor substrate 1 by means of customary processes. Said semiconductor substrate 1 may contain, for example, Si or GaAs. Subsequently, the semiconductor substrate 1 is covered with an isolation layer 2. Said isolation layer 2 may contain, for example, an oxide such as SiO2 or a nitride such as Si N4. In the next step, contact holes for contacting the active components are etched in the isolation layer 2. Subsequently a metallization layer containing, for example, Al:Cu, Al:Cu,Si, Al:Si or Cu, is deposited on the isolation layer 2 and in the contact holes. The metallization layer may alternatively comprise a layered structure of, for example, two layers. The first layer, which borders on the isolation layer 2, may contain, for example, titanium, titanium nitride, titanium tungsten or titanium tungsten nitride, and the second layer may contain, for example, Al:Cu, Al:Cu,Si or Al:Si. The metallization layer is patterned by means of customary processes such as wet etching or plasma etching, so that a metallization 3 is obtained which interconnects the active and, if applicable, passive components. The metallization 3 generally is in the form of conductor tracks or stripes. A resistive layer is deposited on the metallization 3 and on the exposed regions of the isolation layer 2. Preferably, use is made of a material which can be deposited such that the edges are properly covered. This material may be, for example, titanium nitride, titanium tungsten or titanium tungsten nitride. Subsequently, the resistive layer is patterned so as to obtain one or more thin- film resistors 4. Fig. 1 and Fig. 2 show a possibility of patterning the thin-film resistor 4. Fig. 1 shows a plan view of a semiconductor arrangement in accordance with the invention. A metallization 3 is present on an isolation layer 2. The Figure does not show the semiconductor substrate 1 with the active components on which the isolation layer 2 is provided. The resistive layer is patterned such that the thin-film resistor 4 obtained demonstrates an overlap, only in small areas, with the metallization 3 used for interconnection purposes . Fig. 2 is a cross-sectional view of the semiconductor arrangement shown in Fig. 1, taken on the line A-A'. The isolation layer 2 is present on the semiconductor substrate 1 which carries the active components (not shown in Fig. 2). The metallization 3 is provided on the isolation layer 2. The thin-film resistor 4 is present on specific regions of the metallization 3 and on specific regions of the isolation layer 2. In this embodiment, the contact surfaces of the thin-film resistor 4 are formed by the overlapping regions on the upper side of the metallization 3 and by the overlapping regions along the inner, vertical edges of the metallization 3. Fig. 3 and Fig. 4 show a further possibility of patterning the thin-film resistor 4. Fig. 3 is a plan view of the semiconductor arrangement in accordance with the invention, and Fig. 4 is a cross-sectional view of the semiconductor arrangement shown in Fig. 3, taken on the line B-B'. In this embodiment, the contact surfaces of the thin-film resistor 4 fully cover the metallization 3 used for interconnection purposes. The actual resistor body, in this embodiment, is formed only in the areas between two stripe-shaped sections of the metallization 3 where the material of the thin-film resistor 4 borders on the isolation layer 3. To pattern the resistive layer so as to obtain one or more thin-film resistors 4 in accordance with the embodiment of Figs. 1 and 2, an etch medium is chosen which attacks neither the material of the metallization 3 nor the material of the isolation layer 2. To pattern the resistive layer so as to obtain one or more thin-film resistors 4 in accordance with the embodiment shown in Figs. 3 and 4, an etch medium is chosen which must be selective only with respect to the material of the isolation layer 2. After patterning of the resistive layer so as to obtain one or more thin-film resistors 4, a passivation layer (not shown) is provided to protect the metallization 3 and the thin-film resistor(s) 4 from moisture and mechanical loads. The material used in the passivation layer may be, for example, a nitride such as Si3N4 or SiO . These materials are preferably provided by means of PECVD (plasma-enhanced chemical vapor deposition). Other planarization oxides in the form of spin-on-glass (SOG)-film or so-termed "interdielectric layers (ILDs)" such as benzocyclobutene (BCB) or polyimide may alternatively be used in the passivation layer. In the case of a plurality of interconnection levels with a plurality of metallizations 3, thin-film resistors 4 may be provided at each interconnection level. The resistance value of a thin-film resistor 4 in accordance with any one of the exemplary embodiments can be readily calculated as this value is determined by the width of the resistor body and the distance between the regions of the metallization with which the thin-film resistor 4 demonstrates an overlap. The advantages of the described semiconductor arrangement, wherein the thin- film resistor 4 or the thin-film resistors 4 are provided directly on the metallization 3 used for interconnection purposes, are: a) a photo-etch step can be dispensed with, b) low contact resistance of the thin-film resistor 4 by virtue of large contact surfaces between the thin-film resistor 4 and regions of the metallization 3, c) simple calculation of the resistance value, and d) small spread of the resistance value, which can be attributed to the fact that etching of contact holes to the thin-film resistor 4 does not take place and hence etching on the resistor body does not take place either.

Claims

CLAIMS:
1. A semiconductor arrangement having a thin-film resistor (4), said semiconductor arrangement comprising: a semiconductor substrate (1), an isolation layer (2), which is arranged on the semiconductor substrate (1), - a metallization (3), which is arranged on the isolation layer (2), and a thin-film resistor (4), which is arranged on specific regions of the isolation layer (2) and of the metallization (3).
2. A method of manufacturing a semiconductor arrangement having a thin-film resistor (4), said semiconductor arrangement comprising: a semiconductor substrate (1), an isolation layer (2), which is arranged on the semiconductor substrate (1), a metallization (3), which is arranged on the isolation layer (2), and a thin-film resistor (4), characterized in that the thin-film resistor (4) is provided on specific regions of the isolation layer (2) and of the metallization (3).
3. A method as claimed in claim 2, characterized in that first a resistive layer is provided on the metallization (3) and on the isolation layer (2), and this resistive layer is subsequently patterned so as to obtain at least one thin-film resistor (4).
PCT/IB2004/051656 2003-09-10 2004-09-01 Semiconductor arrangement with thin-film resistor WO2005024914A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03103344.2 2003-09-10
EP03103344 2003-09-10

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WO2005024914A1 true WO2005024914A1 (en) 2005-03-17

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007091214A1 (en) * 2006-02-10 2007-08-16 Nxp B.V. Semiconductor device and method of manufacturing thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4533935A (en) * 1980-09-04 1985-08-06 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and a method for manufacturing the same
US5403768A (en) * 1992-04-08 1995-04-04 Samsung Electronics Co., Ltd. Manufacturing method of a thin film resistor
US5705436A (en) * 1996-08-26 1998-01-06 Taiwan Semiconductor Manufacturing Company, Ltd Method for forming a poly load resistor
US6365482B1 (en) * 1999-10-28 2002-04-02 Analog Devices, Inc. I.C. thin film resistor stabilization method
EP1294020A2 (en) * 2001-09-14 2003-03-19 Zarlink Semiconductor Limited Improvements in contact resistances in integrated circuits

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4533935A (en) * 1980-09-04 1985-08-06 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and a method for manufacturing the same
US5403768A (en) * 1992-04-08 1995-04-04 Samsung Electronics Co., Ltd. Manufacturing method of a thin film resistor
US5705436A (en) * 1996-08-26 1998-01-06 Taiwan Semiconductor Manufacturing Company, Ltd Method for forming a poly load resistor
US6365482B1 (en) * 1999-10-28 2002-04-02 Analog Devices, Inc. I.C. thin film resistor stabilization method
EP1294020A2 (en) * 2001-09-14 2003-03-19 Zarlink Semiconductor Limited Improvements in contact resistances in integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007091214A1 (en) * 2006-02-10 2007-08-16 Nxp B.V. Semiconductor device and method of manufacturing thereof
US8120146B2 (en) 2006-02-10 2012-02-21 Nxp B.V. Protected semiconductor device and method of manufacturing thereof

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