CN101369568B - 封装结构、封装方法及感光装置 - Google Patents

封装结构、封装方法及感光装置 Download PDF

Info

Publication number
CN101369568B
CN101369568B CN2008100429308A CN200810042930A CN101369568B CN 101369568 B CN101369568 B CN 101369568B CN 2008100429308 A CN2008100429308 A CN 2008100429308A CN 200810042930 A CN200810042930 A CN 200810042930A CN 101369568 B CN101369568 B CN 101369568B
Authority
CN
China
Prior art keywords
substrate
chip
encapsulating structure
weld pad
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2008100429308A
Other languages
English (en)
Other versions
CN101369568A (zh
Inventor
王之奇
俞国庆
邹秋红
王蔚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China Wafer Level CSP Co Ltd
Original Assignee
CHINA WLCSP Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHINA WLCSP Ltd filed Critical CHINA WLCSP Ltd
Priority to CN2008100429308A priority Critical patent/CN101369568B/zh
Publication of CN101369568A publication Critical patent/CN101369568A/zh
Priority to US12/412,778 priority patent/US20100065956A1/en
Application granted granted Critical
Publication of CN101369568B publication Critical patent/CN101369568B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device

Abstract

本申请提供封装结构、封装方法及感光装置。其中，封装结构包括基底、芯片和与芯片上的焊垫形成电连通的焊接凸点，所述焊接凸点位于所述基底上。由于焊接凸点位于基底上，避免现有技术在封装结构的芯片一侧形成凸点时所必须形成的多层覆层结构，从而减少了封装结构的厚度，并提高了封装结构的可靠性。

Description

封装结构、封装方法及感光装置
技术领域
本申请涉及封装结构、形成该封装结构的封装方法以及由该封装结构形成的感光装置。
背景技术
晶圆级芯片尺寸封装(Wafer Level Chip Size Packaging，WLCSP)技术是对整片晶圆进行封装测试后再切割得到单个成品芯片的技术，封装后的芯片尺寸与裸片一致。晶圆级芯片尺寸封装技术改变传统封装如陶瓷无引线芯片载具(Ceramic Leadless Chip Carrier)、有机无引线芯片载具(Organic LeadlessChip Carrier)和数码相机模块式的模式，顺应了市场对微电子产品日益轻、小、短、薄化和低价化要求。经晶圆级芯片尺寸封装技术封装后的芯片尺寸达到了高度微型化，芯片成本随着芯片尺寸的减小和晶圆尺寸的增大而显著降低。晶圆级芯片尺寸封装技术是可以将IC设计、晶圆制造、封装测试、基板制造整合为一体的技术，是当前封装领域的热点和未来发展的趋势。
美国专利申请第US2001018236号公开了Shellcase公司的一种基于晶圆级芯片尺寸封装技术所制造的封装结构及其制造方法。如图1所示，该封装结构包括基底114、基底114上的空腔壁116、焊垫112、包含感光元件100的芯片102以及焊接凸点110，芯片102的第一表面通过焊垫112与基底114上的空腔壁116压合形成空腔120；芯片102的另一表面上形成有树脂层104；树脂层104的另一表面部分覆有玻璃层106；玻璃层106上部分覆有中介金属层108，中介金属层108与焊垫112以及焊接凸点110连接形成电连通。
从图1可知，为了提供支撑及绝缘等功能，现有的封装结构100需要在芯片102形成有光学元件100一面的相对面设置多层覆层，使得封装结构100的厚度增加。另外，焊垫112与中介金属层108的接触面积小，容易形成断路。
上述封装结构的装配示意图如图2所示。封装结构100装配后的整体厚度＝透镜170厚度的一半+透镜170的焦距+感光元件100至焊接凸点110顶端的厚度+PCB电路板的厚度。从图2还可知，为了方便封装结构100的装配，透镜170的直径一般会大于封装结构100中方形基底114的对角线长。
从图2可知，现有的封装结构100在装配后的整体厚度较大，且透镜170的尺寸也较大。再者，现有技术中，还可能需要在芯片120上的焊垫115之外还要设置延伸焊垫(图未示)，使得制造芯片120的晶圆的可利用面积减少。
发明内容
本申请所要解决的技术问题是：如何提高封装结构的稳定性并降低封装结构的厚度。
为解决上述技术问题，本申请提供一种封装结构，包括基底、芯片和与芯片上的焊垫电连通的焊接凸点，所述焊接凸点位于所述基底上。
根据本申请的另一方面，还提供一种封装方法，包括步骤：提供半封装结构，所述半封装结构包括基底和芯片，所述芯片上具有暴露的焊垫；在所述半封装结构的基底一侧形成与所述焊垫电连通的焊接凸点。
根据本申请的又一方面，还提供一种感光装置，还包括镜头和印刷电路板，所述印刷电路板位于所述镜头和所述封装结构之间。
本申请所要求保护的封装结构的技术方案中，焊接凸点位于基底上，避免现有技术在封装结构的芯片一侧形成凸点时所必须形成的多层覆层结构，从而减少了封装结构的厚度。
另外，导电层部分或全部覆盖所述焊垫，使得导电层与焊垫的连接面积增大，从而降低了该处连接的失效概率，提高了封装结构的稳定性。
附图说明
图1为现有技术封装结构示意图；
图2为图1所示封装结构的装配示意图；
图3为本申请封装结构一个实施例的结构示意图；
图4为本申请封装方法一个实施例的流程图；
图5至图11为本申请封装方法的一个实施例中封装结构制造过程的示意图；
图12为本申请封装结构一个实施例的装配示意图。
具体实施方式
本实施例提供一种封装结构以及相应的封装方法，避免现有技术在封装结构的芯片一侧形成凸点时所必须形成的多层覆层结构，从而有效减少封装结构的厚度。
下面以光学传感器芯片的封装为例，结合附图对本申请的具体实施方式进行详细说明。
本申请中封装结构一个实施例的结构示意图如图3所示，该封装结构200包括基底205和与基底205压合的芯片220以及焊接凸点250，而焊接凸点250设于基底205上。为了在封装结构200与其他部件的后续装配过程中，有利于焊接凸点250与印刷电路板的接触，并防止焊接凸点250的脱落，可以将焊接凸点250设置在基底205远离芯片220的表面上。当然，本领域技术人员也知道，在装配需要的情况下，焊接凸点250也可以位于基底205的侧壁上。
芯片220具有功能面202。功能面202上设有需要密封的光学传感器201，以及位于功能面202上光学传感器201外围的焊垫215。焊垫215是光学传感器201内部的电路与光学传感器201之外的电路相连的连接点。为了降低封装结构200的厚度，芯片220功能面202相对的一面可以经过化学或机械减薄工艺处理。减薄工艺是本领域技术人员所熟知的工艺，在此不再赘述。芯片220功能面202的相对面可以只覆有保护层260，用以保护芯片。制造保护层260的材料可以是包括苯并环丁烯、聚酰亚胺和环氧树脂的组合物。与现有技术相比，由于不需要将焊接凸点250设置在封装结构200的芯片220一侧，因此不需要在芯片220功能面的相对面设置用于支撑、绝缘以及保护等作用的多层覆层，从而降低了封装结构200的厚度。
基底205包括基板206和基板206面向光学传感器201的一侧上设置的空腔壁210。空腔壁210是围墙状的闭环结构。空腔壁210与芯片220上的光学传感器201对应设置，空腔壁210所围成的区域覆盖光学传感器201而不覆盖焊垫215。制造空腔壁210的材料可以是环氧树脂。
基底205上的基板206和空腔壁210与芯片220包围形成密闭光学传感器201的腔室，并使得焊垫215位于该腔室之外。
封装结构200还包括导电层240。导电层240的一端完全覆盖焊垫215。与现有技术相比，由于导电层240与焊垫215的接触是以覆盖的方式实现的，而非现有技术中的点接触的方式，因此导电层240与焊垫215的接触更加稳固，可以提高封装结构200的可靠性。当然，本领域技术人员知道，即使导电层240的一端并非完全覆盖焊垫215，而是部分覆盖焊垫215，也可以达到增加导电层240与焊垫215的接触稳定性，以及提高封装结构200可靠性的目的。导电层240的另一端与焊接凸点250的底部直接接触，从而形成与焊接凸点250和焊垫215直接连接的导电层240，从焊接凸点250到焊垫215的电通路。
为了提供对导电层240的保护，在导电层240上还形成有一层掩膜层246。掩膜层246完全覆盖导电层240和焊垫215，并在导电层240与焊接凸点250接触的地方留有通孔(未标注)，通孔的直径与焊接凸点250的径向直径相等或几乎相等，使得掩膜层246即能完全覆盖导电层240，又能暴露焊接凸点250。制造掩膜层246的材料可以是热塑性感光型树脂，具体例如苯并环丁烯、聚酰亚胺以及环氧树脂的组合物。
为了方便在制造过程中一次性沉积导电层240，基板206与芯片220相对的表面同基板206的侧壁具有为锐角的夹角，该夹角具体例如50度、55度、60度、65度、70度、75度、80度。
本领域技术人员知道，对于一般的封装结构，焊接凸点和相应的焊垫可能有多个。在本申请的一个实施例中，焊接凸点250和焊垫215也可以有多个，因此，导电层240具有一定的图形，形成每个焊接凸点250与相应焊垫215之间独立的电信号通路。
导电层240需要具备的最主要的性质是能够导电，因此导电层240可以是金属层，具体例如铝、铝镍合金或黄金等。如果根据封装的需要，导电层240需要额外具备透明的性质，则导电层240的材料可以例如是同时具备导电和透明性质的纳米铟锡金属氧化物(Indium Tin Oxides，ITO)。
由于封装的对象是光学传感器芯片，芯片220上的光学传感器201需要透过基板206获取光学信号，因此，除了提供绝缘和支撑性能以外，基板206还需要额外具有透明的性质。符合这些性质的材料可以例如是玻璃。
当封装对象是光学传感器芯片且导电层240是不透明的金属层时，需要考虑金属层对光学信号的遮挡问题。因此，当导电层240是金属层时，基板206上的焊接凸点215和导电层240在芯片220的功能面202上的正投影与光学传感器201不相交，即分离。同样的，当掩膜层246是不透明的材料时，也需要在基板206上远离芯片220的一侧形成开口，使得光信号可以通过该开口和透明的基板206后到达光学传感器201。
根据本申请的另一个方面，还提供用于制造上述封装结构的封装方法。如图4所示，根据本申请的一个实施例，封装方法包括步骤：
S201，提供基底，包括基板和基板上的环形空腔壁；
S202，提供芯片，所述芯片包括功能面，所述功能面上设有需要密封的光学传感器和位于功能面上器件外围的焊垫；
S203，在环形空腔壁远离基板的一面形成粘合层；
S204，将芯片与基底对应粘合，使得基板、空腔壁和芯片包围形成密封光学传感器的空腔，而焊垫位于空腔之外；
S205，对芯片功能面的相对面进行减薄，并形成保护层；
S206，切割基板至暴露出焊垫，并形成基板侧壁，基板侧壁与基板与芯片相对表面的夹角为锐角，从而形成暴露焊垫的半封装结构；
S207，在半封装结构的基底一侧形成与焊垫连接的导电层，并图形化导电层；
S208，在导电层上形成掩膜层，并图形化掩膜层，形成暴露导电层的掩膜通孔以及暴露光学传感器的开口；
S209，在掩膜通孔内形成与导电层接触的焊接凸点。
图5至图11为本申请封装方法的一个实施例中封装结构制造过程的示意图，下面结合图5至图11对封装方法进行详细说明。
如图5所示，首先执行步骤S201，提供包括基板206和环形空腔壁210的基底205。基底205的具体细节已经在对封装结构200的详细描述中有所阐明，在此不再赘述。
然后执行步骤S202，提供芯片220。芯片220包括功能面202。功能面202上设有需要密封的光学传感器201和位于功能面202上器件201外围的焊垫215。
然后执行步骤S203，在环形空腔壁210远离基板206的一面形成粘合层(图未示)。粘合层既可以实现粘接的作用，又可以起到绝缘和密封的作用，因此粘合层的材料可以是环氧树脂、聚酰亚胺、BCB树脂或BT树脂。
接着执行步骤S204，将芯片220与基底205对应粘合，使得基板206、空腔壁210和芯片220包围形成密封光学传感器201的空腔，而焊垫215位于空腔之外，形成如图6所示的结构。在进行粘合时，芯片220上的光学传感器201对应落入基底205上的空腔壁210所围成的空腔中，而焊垫215被排除在空腔壁之外，从而形成芯片220与基底205夹合光学传感器201的封闭结构。
然后再执行步骤S205，对芯片220功能面202的相对面进行减薄，形成如图7所示的结构。然后在芯片220功能面202的相对面只形成保护层260，从而形成如图8所示的结构。关于减薄工艺和保护层的细节，在对封装结构200的详细描述中有所阐明，在此不再赘述。
然后执行步骤S206，切割基板206，形成基板侧壁，基板侧壁与基板206与芯片220相对表面的夹角α为锐角，夹角α具体例如50度、55度、60度、65度、70度、75度、80度，从而形成如图9所示的暴露焊垫215的半封装结构。在切割的过程中，可以如图9所示，切割掉部分的空腔壁210，也可以完全不切除空腔壁210的任何部分，从而可以避免降低空腔壁210的机械强度。
接着执行步骤S207，在半封装结构的基底205的一侧形成完全覆盖焊垫215的导电层240，并图形化导电层240。形成导电层240和图形化导电层240的工艺已为本领域技术人员所熟知，在此不再赘述。
然后执行步骤S208，在导电层240上形成掩膜层246，并图形化掩膜层246，形成暴露导电层240的掩膜通孔以及暴露光学传感器201的开口，从而形成如图11所示的结构。
最后执行步骤S209，在掩膜通孔内形成与导电层240接触的焊接凸点250，形成如图3所示的封装结构200。
在上述封装结构和封装方法的实施例中，由于基底205具备支撑和绝缘的作用，因此在制造封装结构200的过程中，不需要在基底205一侧形成其他绝缘层或支撑层，从而可以降低封装结构200的厚度。
另外，与现有技术相比，采用上述封装结构和封装方法，导电层240直接与焊垫215连接，因此在芯片220上的焊垫215之外不需要再设置延伸焊垫，因而可以最大化利用制造芯片220的晶圆面积，降低成本。
根据本申请的有一个方面，还提供由上述封装结构组装形成的感光装置，如图12所示。该感光装置300除包括封装结构200以外，还包括镜头270和印刷电路板260。由于在封装结构200中，焊接凸点250位于基底205上，因此印刷电路板260就位于镜头270和封装结构200之间。该感光装置300的厚度＝透镜270厚度的一半+透镜270的焦距+光学传感器201至保护层260的厚度，这与现有技术相比，至少减少了印刷电路板260的厚度以及焊接凸点250的厚度以及原有的芯片220一侧的多层覆层的厚度，也即减小了感光装置300的厚度。另外，透镜270的直径可以只与光学传感器201的外接圆直径相当，与现有技术相比，透镜270的尺寸明显减小。
以上的具体实施方式均是以光学传感器芯片的封装为例，但本发明不限于此，半导体集成电路芯片、热学传感器芯片、力学传感器芯片或微机电元件等器件的封装也可以采用本申请所描述的封装结构和封装方法，同样也能达到降低封装结构厚度的目的。
虽然本发明已以较佳实施例披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (13)

1.一种封装结构，包括基底、芯片和与芯片上的焊垫电连通的焊接凸点，其特征在于：所述焊接凸点位于所述基底远离芯片的表面，还包括与所述焊接凸点与所述焊垫连接的一层导电层，所述导电层部分或全部覆盖所述焊垫。
2.如权利要求1所述的封装结构，其特征在于：制造所述导电层的材料包括金属或ITO。
3.如权利要求1所述的封装结构，其特征在于：所述芯片的功能面上设有需要密封的器件；所述基底包括基板和空腔壁，所述基板、空腔壁和芯片包围形成密封所述器件的空腔，所述焊垫位于所述空腔之外。
4.如权利要求3所述的封装结构，其特征在于：所述器件包括光学传感器，所述焊接凸点和导电层在芯片上的正投影与所述光学传感器分离。
5.如权利要求3所述的封装结构，其特征在于：制造所述基板的材料包括玻璃。
6.如权利要求3所述的封装结构，其特征在于：所述基板与芯片相对的表面同基板的侧壁的夹角为锐角。
7.一种封装方法，其特征在于，包括步骤：
提供半封装结构，所述半封装结构包括基底和芯片，所述芯片上具有暴露的焊垫；
所述焊接凸点形成在所述基底远离芯片的表面；
所述焊垫与焊接凸点的电连通是通过在所述基底上形成与焊垫和焊接凸点连接的导电层来实现；
所述导电层与所述焊垫的连接是通过导电层部分或全部覆盖焊垫而形成的。
8.如权利要求7所述的封装方法，其特征在于：制造所述导电层的材料包括金属或ITO。
9.如权利要求7所述的封装方法，其特征在于，形成所述半封装结构的步骤包括：
提供基底，所述基底包括基板和基板上的环形空腔壁；
提供芯片，所述芯片包括功能面，所述功能面上设有需要密封的器件和位于功能面上器件外围的焊垫；
在环形空腔壁远离基板的一面形成粘合层；
将芯片与基底对应粘合，使得基板、空腔壁和芯片包围形成密封所述器件的空腔，而所述焊垫位于所述空腔之外。
10.如权利要求9所述的封装方法，其特征在于：所述器件包括光学传感器，所述焊接凸点和金属层在芯片上的正投影与所述光学传感器分离。
11.如权利要求9所述的封装方法，其特征在于：所述基板用玻璃制造。
12.如权利要求9所述的封装方法，其特征在于：所述基板与芯片相对表面同基板侧壁的夹角为锐角。
13.一种感光装置，包括如权利要求1所述的封装结构、镜头和印刷电路板，其特征在于：所述印刷电路板与所述封装结构上的凸点连接且位于所述镜头和所述封装结构之间。
CN2008100429308A 2008-09-12 2008-09-12 封装结构、封装方法及感光装置 Active CN101369568B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2008100429308A CN101369568B (zh) 2008-09-12 2008-09-12 封装结构、封装方法及感光装置
US12/412,778 US20100065956A1 (en) 2008-09-12 2009-03-27 Packaging structure, packaging method and photosensitive device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2008100429308A CN101369568B (zh) 2008-09-12 2008-09-12 封装结构、封装方法及感光装置

Publications (2)

Publication Number Publication Date
CN101369568A CN101369568A (zh) 2009-02-18
CN101369568B true CN101369568B (zh) 2010-08-11

Family

ID=40413298

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008100429308A Active CN101369568B (zh) 2008-09-12 2008-09-12 封装结构、封装方法及感光装置

Country Status (2)

Country Link
US (1) US20100065956A1 (zh)
CN (1) CN101369568B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101710581B (zh) * 2009-10-16 2012-12-26 苏州晶方半导体科技股份有限公司 半导体芯片的封装结构及其制造工艺
CN105097862A (zh) * 2015-08-28 2015-11-25 苏州晶方半导体科技股份有限公司 影像传感器封装结构及其封装方法
CN105355641B (zh) * 2015-12-11 2019-02-19 华天科技（昆山）电子有限公司 高像素影像传感芯片的封装结构及封装方法
US9869598B1 (en) 2016-06-24 2018-01-16 Honeywell International Inc. Low cost small force sensor
CN109376726B (zh) * 2018-12-24 2024-04-02 苏州科阳半导体有限公司 一种屏下光学指纹芯片封装结构

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL133453A0 (en) * 1999-12-10 2001-04-30 Shellcase Ltd Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US6972480B2 (en) * 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
KR100608420B1 (ko) * 2004-11-01 2006-08-02 동부일렉트로닉스 주식회사 이미지 센서 칩 패키지 및 그 제조방법
KR100664316B1 (ko) * 2004-12-23 2007-01-04 삼성전자주식회사 이미지 센서 패키지, 고체촬상장치 및 그 제조방법
US7935568B2 (en) * 2006-10-31 2011-05-03 Tessera Technologies Ireland Limited Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US7394152B2 (en) * 2006-11-13 2008-07-01 China Wafer Level Csp Ltd. Wafer level chip size packaged chip device with an N-shape junction inside and method of fabricating the same
US7663213B2 (en) * 2006-11-13 2010-02-16 China Wafer Level Csp Ltd. Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same

Also Published As

Publication number Publication date
CN101369568A (zh) 2009-02-18
US20100065956A1 (en) 2010-03-18

Similar Documents

Publication Publication Date Title
CN101419952B (zh) 晶圆级芯片封装方法及封装结构
US7916212B2 (en) Image sensor package and camera module utilizing the same
US8097895B2 (en) Electronic device package with an optical device
JP2006344978A (ja) Ｌｅｄパッケージ及びその製造方法、並びにそれを利用したｌｅｄアレイモジュール
JP2011146752A (ja) 側面型発光ダイオード及び側面型発光ダイオードの製造方法
CN101866897A (zh) 具有贯通电极的固体摄像器件
CN101369568B (zh) 封装结构、封装方法及感光装置
KR20120032899A (ko) Ｌｅｄ 패키지 및 그 제조방법
WO2018054315A1 (zh) 封装结构以及封装方法
CN102549785A (zh) 发光装置
CN106298699A (zh) 封装结构以及封装方法
JP2014067743A (ja) 撮像装置、該撮像装置を備える内視鏡
TWI384602B (zh) 嵌埋有感光半導體晶片之封裝基板及其製法
CN105355641A (zh) 高像素影像传感芯片的封装结构及封装方法
CN101546739B (zh) 不通过打线即达成电性连接的芯片封装结构及其制作方法
TWI559464B (zh) 封裝模組及其基板結構
CN101996959A (zh) 不通过打线即实现电性连接的芯片封装结构及其制作方法
JP4463194B2 (ja) 固体撮像装置および固体撮像装置の製造方法
CN100517677C (zh) 多芯片封装的导线架、其制造方法及其封装构造
TWI612650B (zh) 電子封裝結構
CN203746835U (zh) 封装结构
TWI360868B (en) Image sensor chip package and camera module using
KR101761853B1 (ko) 발광소자
JP2004282227A (ja) 光モジュール及びその製造方法並びに電子機器
KR101675008B1 (ko) 광전자 모듈 그리고 광전자 모듈을 제조하기 위한 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: SUZHOU WAFER LEVEL CSP LTD.

Free format text: FORMER NAME: CHINA WAFER LEVEL CSP LTD.

CP03 Change of name, title or address

Address after: 215126 Jiangsu province Suzhou Industrial Park Xinglong Street No. 428 Suchun industrial square 11B/C

Patentee after: Suzhou Wafer Level CSP Technology Co., Ltd.

Address before: Suzhou City, Jiangsu province 215126 Industrial Park Suzhou Xinglong Street No. 428 Suchun industrial square 11B/C

Patentee before: China WLCSP Ltd.