CN101346811A - 通过使用外延层减小三维晶体管的外电阻的方法和结构 - Google Patents

通过使用外延层减小三维晶体管的外电阻的方法和结构 Download PDF

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CN101346811A
CN101346811A CNA2006800494382A CN200680049438A CN101346811A CN 101346811 A CN101346811 A CN 101346811A CN A2006800494382 A CNA2006800494382 A CN A2006800494382A CN 200680049438 A CN200680049438 A CN 200680049438A CN 101346811 A CN101346811 A CN 101346811A
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B·S·多伊尔
J·K·布拉斯克
A·马朱姆达
S·达塔
J·卡瓦利罗斯
M·拉多萨夫杰维克
R·S·乔
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Abstract

描述了用替代栅工艺形成的三栅晶体管的制造。在一个实施例中，使用氮化物伪栅，允许直接与伪栅相邻的外延源区和漏区的生长。这减小了外电阻。

Description

通过使用外延层减小三维晶体管的外电阻的方法和结构
技术领域
本发明涉及具有薄沟道区的晶体管的半导体处理领域。
背景技术
互补金属氧化物半导体(CMOS)晶体管的制造趋势是具有小沟道区。在US 2004/0036127中示出了具有减小主体的晶体管的示例，其包括沟道区连同三栅结构。其它小沟道晶体管是在重掺杂衬底上生长的轻掺杂或无掺杂外延层中形成的δ掺杂晶体管。例如参见转让给本申请受让人的、2004年9月29日提交的、申请序号为10/955669的“Metal Gate Transistor with Epitaxial Source and Drain Regions”。
这些器件中一些的一个问题是从源区和漏区的减薄、有时在栅极边缘发生的普遍的高外电阻。其它器件具有引起较高外电阻的类似问题，例如源区和漏区的有限可用截面区域。结合图1来论述这些问题。
附图说明
图1是现有技术晶体管的截面正视图。
图2A是有时称作鳍板的半导体主体和伪栅的透视图。
图2B是通过图2A的剖面线2B-2B截取的图2A的主体和伪栅的截面正视图。
图3示出外延生长之后及第一离子注入工艺期间的图2B的结构。
图4示出制造隔离物之后及第二离子注入步骤之后的图3的结构。
图5示出形成介电层和平面化工艺之后的图4的结构。
图6示出去除伪栅之后的图5的结构。
图7示出形成高k栅绝缘层和金属栅层之后的图6的结构。
具体实施方式
描述一种用于制造CMOS场效应晶体管的工艺以及所得到的晶体管。在以下描述中，阐述了许多具体细节，例如具体尺寸和化学制度，以便提供对本发明的透彻理解。本领域的技术人员会清楚，没有这些具体细节也可实施本发明。在其它情况下，没有详细描述例如净化步骤等众所周知的处理步骤，以免不必要地影响对本发明的理解。
图1示出与小主体晶体管关联的问题。栅结构10示为在具有源区/漏区16的晶体管的沟道区14处穿过半导体主体12。在栅边缘11对半导体主体或鳍板进行减薄。这种减薄是用于定义主体、形成隔离物和净化氧化物的处理的结果。这种处理可减小主体，使得它可以不再具有充分的结晶晶种以支持外延层的生长。在这种处理期间，通常可损失栅边缘处的主体的多达20-50％。除了产生损失，这种处理还引起较高源/漏电阻以及晶体管性能的必然降低。在栅边缘处减薄的问题不仅发生在具有硅-绝缘体(SOI)衬底的三栅结构中，而且发生在某些体硅层和δ掺杂晶体管中。
如图2A所示，在埋入氧化物层(BOX)21上制造半导体主体20。例如，从设置在BOX 21上的单晶硅层制造主体20。SOI衬底是半导体工业众所周知的。举例来说，通过将BOX 21和硅层键合到衬底(未示出)上，然后对硅层平面化以使它比较薄，来制造SOI衬底。形成SOI衬底的其它技术是已知的，例如包括将氧注入硅衬底中以形成埋入氧化物层。还可使用除硅之外的其它半导体材料，例如砷化镓。
例如在BOX 21上穿过主体20形成氮化硅伪栅结构25。在栅结构25与主体20相交的地方定义晶体管的沟道区，这通常是替代栅工艺中的情况。可由其它材料制造伪栅结构，后面将进行论述。
在图2B中，再次示出半导体主体20和氮化硅伪栅结构25，没有BOX 21。图2B的视图一般是通过图2A的剖面线2B-2B截取的。在图2B和其余附图中，未示出BOX 21。以下所述的处理不依赖于主体20制造在BOX 21上。实际上，可从体衬底制造主体20。例如，可从单晶硅衬底或其它半导体衬底有选择地生长主体20。备选地，可通过有选择地蚀刻单晶半导体层以便定义多个主体20来形成主体20。
如图3所示，在主体20上生长外延层27。可生长硅或硅锗或者其它半导体层。重要的是，不在伪栅25上生长所述层27。如前面所述，在一个实施例中，由氮化硅制造伪栅25，以及例如在主体20是硅主体时，外延生长可发生在主体20上，而无需在伪栅25上形成。注意，如果伪栅是多晶硅栅，则某种外延生长将发生在伪栅结构上。这种生长在后续替代栅工艺中不容易去除，并且如果未去除，则将使替代栅短接到源区和漏区。由此，用于伪栅结构的材料选择成，在如图3所示加厚主体时，在该结构上没有外延生长发生。此外，应去除伪栅而没有去除源/漏隔离物，否则，栅极不会在高要求尺寸之内。
这时，发生离子注入步骤，为n沟道晶体管注入n型离子，或者为p型沟道晶体管注入p型离子。线28所示的这个初始注入步骤形成尖或延伸源区和漏区，这是通常使用的。由此，这个注入步骤留下了相对轻掺杂的主体20。
接下来，氮化硅层被保形地沉积在图3的结构上，并用来制造图4所示的隔离物38。可使用普通众所周知的各向异性蚀刻来制造隔离物。在一个实施例中，将用5-13％碳浓度掺杂的碳掺杂氮化物用于隔离物。稍后论述所述的其它隔离物。在形成氮化物层之前，去除主体20上存在的任何氧化物。这种净化工艺是通常减小栅边缘处主体厚度的工艺之一。在隔离物形成之后，通过离子注入35形成源区和漏区30的主要部分。对于n沟道器件，以高达1×1019-1×1020原子/cm3注入剂量来使用砷或磷。对于p沟道器件，将硼注入到相同剂量水平。
以上使用氮化物伪栅和碳掺杂氮化物隔离物。材料的这种组合允许生长外延层，而没有生长在伪栅上，并且允许去除伪栅，而没有蚀刻隔离物。伪栅材料的其它示例包括具有极性键的非晶材料，例如基于CVD的二氧化硅或者碳掺杂氮化硅。对于后一种材料，隔离物可由氧化物制成。在这种情况下，源区/漏区的掺杂有助于改进伪栅与隔离物之间的选择性，或者隔离物被掺杂。
备选地，在形成隔离物38之后，可在外延层27上生长第二外延层，以进一步加厚主体以及源区和漏区，由此进一步减小随后形成的晶体管的外电阻。然后将使主要源区和漏区30上升(未示出)到隔离物38的边缘之上。
对于以上使用第二外延生长的p沟道晶体管，例如，可通过有选择地沉积外延硼(B)掺杂硅或锗浓度高达30％的SiGe来形成源区和漏区。在100sccm的二氯甲硅烷(DCS)、20slm H2、750-800℃、20Torr、150-200sccm HCl、150-200sccm的乙硼烷(B2H6)流量和150-200sccm的GeH4流量的处理条件下，得到了沉积速率为20nm/min、B浓度为1E20cm-3且锗浓度为20％的高掺杂SiGe薄膜。由薄膜中高B浓度引起的0.7-0.9mOhm-cm的低电阻率提供了如下好处：尖源区/漏区中的高电导率，以及由此减小的Rexternal。源区/漏区中的SiGe对沟道施加压缩应变，其又引起增强的移动性和改进的晶体管性能。
对于NMOS晶体管，例如使用在100sccm的DCS、25-50sccm HCl、200-300sccm的、在750℃和20Torr载流子H2气体流量为20slm的1％PH3的处理条件下有选择沉积的原地磷掺杂硅来形成源区/漏区。在沉积薄膜中，得到电阻率为0.4-0.6mOhm-cm的2E20cm-3的磷浓度。
这时在图4的结构上保形地沉积介电层40，如图5所示。这可包括二氧化硅层，其将成为集成电路中的层间电介质(ILD)。可使用低k介电层或牺牲介电层。在任一情况下，层40通常都具有承受平面化工艺如化学机械抛光(CMP)的机械强度。
在处理中的这一点，或者更早，进行退火以部分激活掺杂。
在介电层40的沉积和平面化之后，使用湿法蚀刻去除氮化物伪栅25，留下开口45，如图6所示。还去除剩余的任何伪栅氧化物。湿法蚀刻剂(例如H3PO4)有选择地蚀刻氮化物，而没有附连主体25，或者基本上蚀刻隔离物38。
接下来，在包括主体20中位于开口45内的侧面和上面的暴露表面上形成栅电介质50。在一个实施例中，栅电介质具有高介电常数(k)，例如HfO2或ZrO2等金属氧化物电介质，或者例如PZT或BST等其它高k电介质。可通过诸如原子层沉积(ALD)或者化学汽相沉积(CVD)的任何众所周知的技术来形成栅电介质。备选地，栅电介质可以是生长电介质。例如，栅电介质50可以是用湿法或干法氧化工艺生长到5-50
Figure A20068004943800091
之间的厚度的二氧化硅薄膜。
此后，还如在图7中看到的，在栅介电层50上形成栅电极(金属)层52。栅电极层52可通过适当栅电极材料的毯状沉积来形成。在一个实施例中，栅电极材料包括诸如钨、钽、钛和/或氮化物及它们的合金之类的金属薄膜。对于n沟道晶体管，可使用范围为3.9至4.6eV的功函数。对于p沟道晶体管，可使用范围为4.6至5.2eV的功函数。因此，对于具有n沟道和p沟道两种晶体管的衬底，可能需要使用两个独立的金属沉积工艺。
例如使用CMP对金属层52进行平面化，并且平面化继续，直到至少暴露出介电层40的上表面，如图7所示。
这时使用普通处理来完成图7的晶体管，例如形成到栅极以及源区和漏区的触点。
值得注意的是，在将图7的晶体管与图1的现有技术晶体管相比时，应注意，没有图1所示的减薄11。反而，如图7所示，由于外延生长能够与伪栅对准，因此，主体的横截面在沟道区外的实际上比在沟道区内的更大。这与图1的现有技术图形成鲜明对照，在图1中存在主体超出沟道区的相当大的减薄，这极大地增加了晶体管的外电阻。

Claims (20)

1.一种用于形成场效应晶体管的方法，包括：
由第一材料在半导体主体上形成伪栅；
在所述主体上与所述伪栅对准生长外延半导体层，使得在所述第一材料上没有生长发生；
在所述主体中至少部分与所述伪栅对准形成源区和漏区；以及
用与所述主体绝缘的导电栅替代所述伪栅。
2.如权利要求1所述的方法，其中所述主体是硅主体。
3.如权利要求1所述的方法，其中所述伪栅覆盖所述主体的两个相对侧面和上表面。
4.如权利要求1所述的方法，其中形成所述源区和漏区包括：
与所述伪栅对准掺杂所述主体；
由所选第二材料在所述伪栅的相对侧面上形成隔离物，使得可蚀刻所述第一材料而基本上没有蚀刻所述第二材料；以及
与所述隔离物对准掺杂所述主体。
5.如权利要求1所述的方法，其中替代所述伪栅包括：
用介电材料包围所述伪栅；以及
蚀刻所述伪栅而基本上没有蚀刻所述主体和所述介电材料，由此暴露所述主体中的沟道区。
6.如权利要求5所述的方法，包括：
在所述主体的所述沟道区上形成高k栅电介质；以及
在所述高k栅电介质上形成金属栅。
7.如权利要求6所述的方法，其中所述金属栅的功函数在3.9至5.2eV的范围之间。
8.如权利要求7所述的方法，其中形成所述源区和漏区包括：
与所述伪栅对准掺杂所述主体；
由所选第二材料在所述伪栅的相对侧面上形成隔离物，使得可蚀刻所述第一材料而基本上没有蚀刻所述第二材料；以及
与所述隔离物对准掺杂所述主体。
9.如权利要求4所述的方法，包括：
在形成所述隔离物之后，在所述主体上形成附加外廷生长。
10.如权利要求9所述的方法，其中所述主体包括硅。
11.如权利要求9所述的方法，其中替代所述伪栅包括：
用介电材料包围所述伪栅；以及
蚀刻所述伪栅而基本上没有蚀刻所述介电材料或所述主体，由此暴露所述主体中的沟道区。
12.如权利要求11所述的方法，包括：
在所述主体的所述沟道区上形成高k电介质；以及
在所述高k电介质上形成金属栅。
13.如权利要求12所述的方法，其中所述金属栅的功函数在3.9至5.2eV的范围之间。
14.在使用替代栅工艺形成场效应晶体管时，一种改进包括：
在半导体主体上形成氮化硅牺牲栅；
通过外延生长增大未被所述牺牲栅覆盖的所述半导体主体的尺寸；以及
用介电材料包围所述牺牲栅，使得可蚀刻所述牺牲栅而基本上没有蚀刻所述介电材料或所述主体。
15.如权利要求14所述的工艺，包括：
在所述主体中至少部分与所述牺牲栅对准形成源区和漏区。
16.如权利要求15所述的工艺，其中形成所述源区和漏区包括：
与所述牺牲栅对准掺杂所述主体；
在所述牺牲栅的相对侧面上形成隔离物；以及
与所述隔离物对准掺杂所述主体；
17.如权利要求16所述的工艺，包括：
去除所述牺牲栅而基本上没有去除所述电介质或所述主体，由此定义沟道区；
在所述主体的所述沟道区上形成高k电介质；以及
在所述高k电介质上形成金属栅。
18.一种晶体管，包括：
半导体主体，具有沟道区以及所述沟道区的相对侧面上的源区和漏区，所述主体具有直接与所述沟道区相邻提供更大截面区域的外延区，所述主体的所述更大截面区域包括尖源区和漏区以及主源区和漏区；
高k栅电介质，在所述主体的所述沟道区上；以及
金属栅，设置在所述高k栅电介质上。
19.如权利要求18所述的晶体管，其中所述金属栅的功函数在3.9和5.2eV之间。
20.如权利要求18所述的晶体管，包括：
隔离物，设置在所述主体上的所述尖源区和漏区上。
CNA2006800494382A 2005-12-29 2006-12-18 通过使用外延层减小三维晶体管的外电阻的方法和结构 Pending CN101346811A (zh)

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