CN101339945A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN101339945A
CN101339945A CNA2007101801492A CN200710180149A CN101339945A CN 101339945 A CN101339945 A CN 101339945A CN A2007101801492 A CNA2007101801492 A CN A2007101801492A CN 200710180149 A CN200710180149 A CN 200710180149A CN 101339945 A CN101339945 A CN 101339945A
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CN101339945B (zh
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魏启珊
吴国铭
林怡君
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TSMC China Co Ltd
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Abstract

本发明提供一种半导体装置，包含：半导体衬底；n型杯状结构，自该半导体衬底的上表面延伸至该半导体衬底中，其中该n型杯状结构包含底部其埋藏于该半导体衬底中；p型埋藏层，其位于该n型杯状结构的该底部上，其中该p型埋藏层埋藏于该半导体衬底中；以及高压n型金属氧化物半导体元件，其位于该p型埋藏层上，且位于由该n型杯状结构的侧边所围绕的区域中。借助本发明，易于增加n型与p型埋藏层的杂质浓度，能够施加正的和负的两种源极/漏极至衬底电压而不会有显著的漏电流和/或击穿。

Description

半导体装置
技术领域
本发明涉及高压金属氧化物半导体(high-voltagemetal-oxide-semiconductor，HVNMOS)装置，特别涉及高压金属氧化物半导体装置的隔离结构。
背景技术
高压金属氧化物半导体元件广泛地应用于例如中央处理器电源供应器(CPU power supply)、电源管理系统(power management)、交流/直流转换器(AC/DC converter)等许多电子元件中。
图1显示传统的形成于衬底6上的n型HVMOS(HVMOS)元件2。HVNMOS元件2包含栅极4、位于高压n型阱(high-voltage n-well，HVNW)区8中的漏极区6，以及位于高压p型阱(high-voltage p-well，HVPW)区12中的源极区10。由于浅沟槽隔离(shallow trench isolation，STI)区5将漏极区6与栅极4隔开，故可施加高的漏极至栅极电压(drain-gate voltage)。HVNMOS元件2形成于n型埋藏层(n-type buried layer，NBL)14上，其中n型埋藏层14形成于p型衬底16上。
当传统的HVNMOS元件2使用于某些应用时会遇到障碍。例如，由于功率集成电路(power IC)或驱动集成电路(driver IC)的运行可能包含有施加负电压的操作，故当HVNMOS元件2被用于功率集成电路或驱动集成电路中时，HVNMOS元件2可能会具有负的源极至衬底电压(source-to-substratevoltage)和/或负的漏极至衬底电压(drain-to-substrate voltage)。在这个例子中，会在由p型衬底16与n型埋层14所构成的二极管(diode)18上施加正向偏压。n型埋层14还与高压n型阱区8和N+漏极区6连接。因此，二极管18能够被施加负的漏极至衬底电压而导通。但这会对HVNMOS元件2造成漏电流增加，或击穿电压(breakdown voltage)变小的不利影响。
因此需要一种HVMOS元件，当其被施加正的源极至衬底电压及正的漏极至衬底电压时能够有良好的运转性能，而在被施加负的源极至衬底电压及负的漏极至衬底电压时也能够具有良好的运转性能。
发明内容
为达成上述目的，本发明提供一种半导体装置，包含：半导体衬底；n型杯状结构，其自该半导体衬底的上表面延伸至该半导体衬底中，其中该n型杯状结构包含底部其埋藏于该半导体衬底中；p型埋藏层，其位于该n型杯状结构的该底部上，其中该p型埋藏层埋藏于该半导体衬底中；以及高压n型金属氧化物半导体元件，其位于该p型埋藏层上，且位于由该n型杯状结构的侧边所围绕的区域中。
上述半导体装置中，该n型杯状结构具有四个所述侧边，其中所述侧边各自由该n型杯状结构的该底部实质上向上延伸至该半导体衬底的上表面，且所述侧边各自包含第一部分以及位于该第一部分上的第二部分，其中该第一部分与该第二部分实质上具有不连续的杂质浓度。
上述半导体装置中，该侧边的第一部分的杂质浓度可实质上高于该n型杯状结构的底部的杂质浓度。
上述半导体装置中，该n型杯状结构可具有四个所述侧边，其中所述侧边各自由该n型杯状结构的底部实质上向上延伸至该半导体衬底的上表面，且该n型杯状结构的所述侧边与该底部实质上具有不同的杂质浓度。
上述半导体装置还可包含：高压p型阱区，其位于该p型埋藏层上；高压n型阱区，其位于该p型埋藏层上；栅极介电层，其自该高压p型阱区上延伸至该高压n型阱区上；栅极，其位于该栅极介电层上；源极区，其位于该高压p型阱区内并邻接该栅极；以及漏极区，其位于该高压n型阱区内并邻接该栅极。
上述半导体装置中，该p型埋藏层可完全覆盖该n型杯状结构的底部。
本发明还提供一种半导体装置，包含：半导体衬底；第一高压n型阱区，其位于该半导体衬底内；第二高压n型阱区，其位于该半导体衬底内，其中该第一高压n型阱区与该第二高压n型阱区是平行的；第三高压n型阱区，其位于该第一高压n型阱区与该第二高压n型之间的位置；第一高压p型阱区，其位于该第一高压n型阱区与该第二高压n型之间的位置；第一n型隔离区与第二n型隔离区，其各自位于该第一高压n型阱区与该第二高压n型阱区下方，并各自邻接该第一高压n型阱区与该第二高压n型阱区；n型埋藏层，其连接该第一n型隔离区与该第二n型隔离区；以及p型埋藏层，其位于该n型埋藏层上。
上述半导体装置中，该p型埋藏层可以垂直方向延伸至超过位于该第一高压n型阱区与该第二高压n型阱区之间的区域。
上述半导体装置中，该第一n型隔离区及该第二n型隔离区可实质上具有与该第一高压n型阱区及该第二高压n型阱区不同的杂质浓度。
上述半导体装置中，该第一n型隔离区及该第二n型隔离区可实质上具有与该n型埋藏层不同的杂质浓度。
借助本发明，易于增加n型与p型埋藏层的杂质浓度，能够施加正的和负的两种源极/漏极至衬底电压而不会有显著的漏电流和/或击穿。
附图说明
图1显示传统的高压n型MOS元件。
图2A至图9为本发明的实施例其制造过程中于不同阶段的剖面图。
图10为本发明的实施例的俯视图。
其中，附图标记说明如下：
2～n型HVMOS元件；4～栅极；5～浅沟槽隔离区；6～漏极区；8～高压n型阱区；10～源极区；12～高压p型阱区；14～n型埋层；16～衬底；18～二极管；20～衬底；22～n型埋藏层；24～N-ISO区；26～p型埋藏层；261～p型区；28～n型埋藏层的底表面；30～p型埋藏层的底表面；32～外延层；34～衬底与外延层之间的界面；36～光致抗蚀剂层；38～p型阱区；40～光致抗蚀剂层；42～n型阱区；44～n型阱区；45～浅沟槽隔离区；50～栅极介电层；52～栅极；54～隔离层；58～光致抗蚀剂层；60～P+区；62～光致抗蚀剂层；64～漏极区；66～源极区；68～接触区；70～二极管；72～二极管；100～HVMOS元件；200～HVMOS元件。
具体实施方式
有关各实施例的制造和使用方式如以所述。然而，值得注意的是，本发明所提供的各种可应用的发明概念依具体内文的各种变化据以实施，且在此所讨论的具体实施例仅用来显示具体使用和制造本发明的方法，而不用以限制本发明的范围。
以下透过各种附图及示例说明本发明优选实施例的制造过程。此外，在本发明各种不同的各种实施例和附图中，相同的符号代表相同或类似的元件。
请参考图2A及图2B，提供衬底20，其优选包含例如硅半导体材料，也可使用其他半导体材料如锗化硅(silicon germanium，SiGe)和绝缘层上硅(silicon-on-insulator，SOI)。衬底20优选以p型杂质掺杂。
对衬底20进行注入工艺以形成掺杂层(doped layer)。首先在衬底20上形成光致抗蚀剂层(未显示)并将其图案化。再利用向衬底20内掺杂n型杂质，如磷(phosphorous)、锑(antimony)和/或砷(arsenic)元素的方式来形成n型埋藏层22。在一实施例中，以介于约1014/cm2至约1016/cm2的剂量进行掺杂工艺。接着将光致抗蚀剂层除去。
N型隔离(N-type isolation)区24，也可被称为N-ISO区24，同样是以掺杂的方式形成的，其中所形成的光致抗蚀剂层可用以定义N-ISO区24的范围。图中所示N-ISO区24虽位于两个被隔离开的区域，但在俯视图中，N-ISO区24为环状结构(参考图10)。N-ISO区24实质上至少与n型埋藏层22相邻，且N-ISO区部分区域优选与n型埋藏层22重叠。
p型埋藏层(p-type buried layer，PBL)26也是以掺杂方式形成的，而所掺杂的杂质以包含硼(boron)元素为优选。在一优选实施例中，p型埋藏层26是毯覆式地形成的。p型埋藏层26的掺杂剂量以低于n型埋藏层22的掺杂剂量为优选。在一实施例中，p型埋藏层26的掺杂剂量介于约1013/cm2至约1015/cm2之间。p型埋藏层26所含有的杂质浓度低于N-ISO区24所含有的杂质浓度为优选。在一实施例中，为形成N-ISO区24所使用的掺杂剂量大于为形成p型埋藏层26所使用的掺杂剂量两倍。n型埋藏层22的底表面28以低于p型埋藏层26的底表面30为优选。这可利用调整来达成，且必要时可增加n型埋藏层22的掺杂能量。n型埋藏层22实质上以埋藏至衬底内为优选，如图2B所示。然而，本领域技术人员将可了解，n型埋藏层将往各个方向散布至衬底20表面。因此，如何将所掺杂的杂质集中在如图2B内所示的层状范围内是重要关键。在本例中，可通过任何掺杂顺序形成n型埋藏层22、N-ISO区24以及p型埋藏层26。
图3显示在衬底20上以外延生长(epitaxial growth)的方式形成外延层(epitaxial layer)32。外延层32以如硅半导体之类材料形成为优选，而也可用与衬底20相同或不同的材料形成。图3内的虚线34显示衬底20与外延层32之间的界面。外延层32可以为未掺杂或以p型杂质掺杂，其中杂质优选在外延生长时进行原位(in-situ)掺杂。外延层32的厚度T实质上大于之后所形成的高压p型阱及高压n型阱的厚度。在一实施例中，外延层32的厚度T大于约2nm。
由于外延生长工艺是在高温环境下进行的，n型埋藏层22、N-ISO区24以及p型埋藏层26会往外扩散至外延层32内。由于N-ISO区24的杂质浓度相对较高，扩散的N-ISO区24的上表面实质上高于扩散的n型埋藏层225的上表面。由于n型埋藏层22的扩散长度(diffusion length)小于p型埋藏层26的扩散长度(因此离子的分布更为集中)，还由于n型埋藏层22的掺杂剂量高于p型埋藏层26的掺杂剂量，因此n型埋藏层22的杂质浓度很可能高于p型埋藏层26的杂质浓度。此外，由于硼元素的扩散距离大于n型杂质的扩散距离，p型埋藏层26往外延层32内的扩散范围会深于n型埋藏层22的扩散范围。因此p型埋藏层26存在于n型埋藏层22上。p型埋藏层26也可扩散至低于n型埋藏层22的范围。因此，在p型衬底20与n型埋藏层22之间具有杂质浓度高于衬底20的p型区261。p型埋藏层26的底表面可高于或低于N-ISO区24的底表面。
请参考图4，利用光刻技术来形成并图案化光致抗蚀剂层36。接着进行p型杂质的掺杂工艺以形成p型阱区38，p型阱区38也可被称为高压p型阱(high-voltage p-well)区38。高压p型阱区38可用硼和/或铟(indium)元素进行掺杂工艺。在掺杂工艺后，高压p型阱区38可含有介于约1015/cm3至约1016/cm3的杂质浓度。高压p型阱区38的底部邻接p型埋藏层26。接着除去光致抗蚀剂层36。
请参考图5，利用光刻技术来形成并图案化光致抗蚀剂层40。接着进行n型杂质的掺杂工艺以形成n型阱区42及44，n型阱区42及44也可被称为高压n型阱(high-voltage n-well)区42及44。高压n型阱区42及44可用硼和/或铟元素进行掺杂工艺，而所掺杂的n型杂质可中和在p型埋藏层26(以及外延层32——若其为通过原位掺杂的方式形成的话)中所掺杂的p型杂质，并将所掺杂的区域反转成n型。高压n型阱区42及44与N-ISO区24可含有相同或不同的杂质。在一实施例中，在掺杂工艺后，高压n型阱区42及44可含有介于约1015/cm3至约1016/cm3的净n型杂质浓度(net n-typeimpurity concentration)。高压n型阱区42的底部邻接N-ISO区24。与N-ISO区24相似，虽然图中所示高压n型阱区42位于两个被隔离开的区域，但在俯视图中，高压n型阱区42同样为环状结构(参考图10)。高压n型阱区42以具有与N-ISO区24相同的宽度，且实质上与N-ISO区24共边界为优选。此外，N-ISO区24与高压n型阱区42实质上也可具有不同的宽度。接着除去光致抗蚀剂层40。
N-ISO区24、高压n型阱区42及n型埋藏层22形成杯状结构(tub)。p型埋藏层26位于杯状结构的底部上。此结构可有效地将之后形成于此杯状结构内的HVMOS元件隔离开。
图6显示浅沟槽隔离区45的形成。在一优选实施例中，浅沟槽隔离区45的形成步骤包含：首先在外延层32内形成沟槽，再利用介电材料将沟槽填满，其中介电材料包含二氧化硅(SiO2)或其他以高密度等离子体(high-density plasma，HDP)技术形成的氧化物，接着再进行化学机械研磨(chemical mechanical polish，CMP)工艺将表面平坦化。在其他实施例中，可利用局部氧化隔离技术(local oxidation of silicon，LOCOS)在与浅沟槽隔离区45相同的位置形成场氧化层。形成场氧化层的工艺步骤可包含在高压p型阱区38与高压n型阱区42及44上形成掩模层，再将掩模层图案化以形成开口，接着进行氧化步骤。因此场氧化层是穿过掩模层的开口而形成的。接着除去掩模层。
图7显示栅极介电层(gate dieectric)50、栅极(gate electrode)52及隔离层(spacer)54的形成。由于其工艺为现有技术，故在此不再赘述。在本例中，也可形成轻掺杂源极区(未示出)。栅极52的侧边位于浅沟槽隔离区45上方为优选。
请参考图8，提供光致抗蚀剂层58，并将其图案化。接着进行p型杂质的掺杂工艺以形成P+区60。P+区60以重掺杂至含有高杂质浓度为优选，例如，杂质浓度大于约1020/cm3。在所说明的实施例中，重掺杂表示杂质浓度高于约1020/cm3。然而，本领域技术人员将可了解，相关技术中所指的重掺杂一词依特定的元件种类、技术演进、最小的特征尺寸等而定。因此，在此所说明的名词或用语会随着技术的进步而变，并不局限于所说明的实施例。在p型阱38中的P+区60作为接触区(contact region)。在形成P+区60后，将光致抗蚀剂层58除去。
接着形成光致抗蚀剂层62，并将其图案化，如图9所示。再进行n型杂质的掺杂工艺以形成漏极区64、源极区66及接触区68。以重掺杂n型杂质为优选。在掺杂工艺结束后，将光致抗蚀剂层62除去。本领域技术人员将可了解，N+区、P+区以及栅极结构的形成顺序仅为设计上选择的问题。
最后形成两个HVMOS元件100及200。HVMOS元件100的源极区66及栅极52优选各自与HVMOS元件200的源极区66及栅极52连接，因此HVMOS元件100及200可作为一个单一的元件。HVMOS元件一般可包含一组以上由HVMOS元件100及200所形成的组合，其中每个组合一般被称为一个柱脚(leg)。本领域技术人员将可了解，在杯状结构中可形成HVNMOS元件的一个或多个柱脚，其中杯状结构由n型埋藏层22、N-ISO区24及高压n型阱区42形成。
图10示出图9中所示结构的俯视图。为求简明，仅示出高压p型阱区38、高压n型阱区42及44及栅极52。图10显示高压n型阱区42与N-ISO区24形成环状结构，此环状结构包围高压p型阱区38与高压n型阱区44。因此，形成于高压n型阱区(环状结构)42内的HVMOS元件被电性绝缘(electrically isolated)。
请再参考图9，要注意的是，p型衬底20、n型埋藏层22与p型埋藏层26形成两个二极管70与72，其中二极管70与72面对面(face-to-face)相连接。因此，无论源极至衬底电压或漏极至衬底电压均为正偏压或负偏压，二极管70与72其中之一均将为反向偏压(reverse biased)。
本发明的实施例具有一些有利的特征。例如，通过本发明实施例所形成的HVMOS元件能够被施以正的和负的两种源极/漏极至衬底电压，而不会有明显的漏电流和/或早期击穿(early breakdown)。由于n型埋藏层22与p型埋藏层26的形成工艺(参考图9)的进行早于高压p型阱区38与高压n型阱区42及44的形成工艺(高压p型阱区38与高压n型阱区42及44的掺杂工艺是在外延层32的形成工艺之后进行的)，因此易于增加n型埋藏层22与p型埋藏层26的杂质浓度。在一实施例中，n型埋藏层22可含有高至约1018/cm3或甚至更高的杂质浓度。p型埋藏层26可含有高于约1016/cm3的杂质浓度。因此，包含以n型埋藏层22或p型埋藏层26作为基极(base)的寄生双极晶体管(parasitic bipolar transistor)的基极可具有高杂质浓度。寄生双极晶体管中的一个例子是以衬底20、n型埋藏层22与p型埋藏层26形成的。由于基极具有高杂质浓度，基极电阻降低，基极电压也相应性地降低。因此寄生双极晶体管变得更难以导通。
虽然本发明已以优选实施例公开如上，然而其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，应可做一定的改动与修改，因此本发明的保护范围应以所附权利要求为准。

Claims (10)

1.一种半导体装置，包含：
半导体衬底；
n型杯状结构，其自该半导体衬底的上表面延伸至该半导体衬底中，其中该n型杯状结构包含埋藏于该半导体衬底中的底部；
p型埋藏层，其位于该n型杯状结构的该底部上，其中该p型埋藏层埋藏于该半导体衬底中；以及
高压n型金属氧化物半导体元件，其位于该p型埋藏层上，且位于由该n型杯状结构的侧边所围绕的区域中。
2.如权利要求1所述的半导体装置，其中该n型杯状结构具有四个所述侧边，其中所述侧边各自由该n型杯状结构的该底部实质上向上延伸至该半导体衬底的该上表面，且所述侧边各自包含第一部分以及位于该第一部分上的第二部分，其中该第一部分与该第二部分实质上具有不连续的杂质浓度。
3.如权利要求2所述的半导体装置，其中该侧边的第一部分的杂质浓度实质上高于该n型杯状结构的底部的杂质浓度。
4.如权利要求1所述的半导体装置，其中该n型杯状结构具有四个所述侧边，其中所述侧边各自由该n型杯状结构的该底部实质上向上延伸至该半导体衬底的该上表面，且该n型杯状结构的所述侧边与该底部实质上具有不同的杂质浓度。
5.如权利要求1所述的半导体装置，还包含：
高压p型阱区，其位于该p型埋藏层上；
高压n型阱区，其位于该p型埋藏层上；
栅极介电层，其自该高压p型阱区上延伸至该高压n型阱区上；
栅极，其位于该栅极介电层上；
源极区，其位于该高压p型阱区内并邻接该栅极；以及
漏极区，其位于该高压n型阱区内并邻接该栅极。
6.如权利要求1所述的半导体装置，其中该p型埋藏层完全覆盖该n型杯状结构的该底部。
7.一种半导体装置，包含：
半导体衬底；
第一高压n型阱区，其位于该半导体衬底内；
第二高压n型阱区，其位于该半导体衬底内，其中该第一高压n型阱区与该第二高压n型阱区是平行的；
第三高压n型阱区，其位于该第一高压n型阱区与该第二高压n型之间的位置；
第一高压p型阱区，其位于该第一高压n型阱区与该第二高压n型之间的位置；
第一n型隔离区与第二n型隔离区，其各自位于该第一高压n型阱区与该第二高压n型阱区的下方，并各自邻接该第一高压n型阱区与该第二高压n型阱区；
n型埋藏层，其连接该第一n型隔离区与该第二n型隔离区；以及
p型埋藏层，其位于该n型埋藏层上。
8.如权利要求7所述的半导体装置，其中该p型埋藏层以垂直方向延伸至超过位于该第一高压n型阱区与该第二高压n型阱区之间的区域。
9.如权利要求7所述的半导体装置，其中该第一n型隔离区及该第二n型隔离区实质上具有与该第一高压n型阱区及该第二高压n型阱区不同的杂质浓度。
10.如权利要求7所述的半导体装置，其中该第一n型隔离区及该第二n型隔离区实质上具有与该n型埋藏层不同的杂质浓度。
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US7843002B2 (en) 2010-11-30

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