CN101335298B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101335298B
CN101335298B CN200810129324XA CN200810129324A CN101335298B CN 101335298 B CN101335298 B CN 101335298B CN 200810129324X A CN200810129324X A CN 200810129324XA CN 200810129324 A CN200810129324 A CN 200810129324A CN 101335298 B CN101335298 B CN 101335298B
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CN101335298A (zh
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金知泓
张德基
张炳琸
朴盛羲
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DB HiTek Co Ltd
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Abstract

公开了一种半导体器件。该半导体器件包括：第二导电半导体衬底；在半导体衬底上的栅电极；在栅电极的相对的两侧形成的第一导电漂移区；在第一导电漂移区中形成的源区或者漏区；以及形成在栅电极与漏区之间的漂移区中的STI区。位于STI区的下部处的漂移区具有杂质浓度在向下的方向上减少、然后增加并且再次减少的掺杂分布。本发明能够改进击穿电压特性，防止碰撞电离。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法。
背景技术
随着已经小尺寸地制造半导体器件，高电压器件的尺寸也已经逐渐地减小。
具体而言，高电压器件无论其尺寸如何都必须执行相同性能。另外，有必要提供与低电压器件的制造工艺兼容的制造方法。
由于快速跳回(snapback)现象而在高电压器件中可能出现击穿现象。
具体而言，如果增加向高电压晶体管的漏极施加的电压，则电子从其源极移向漏极。因此，在位于漏极方向上的间隔件的下部周围可能出现碰撞电离。
随着碰撞电离出现，空穴从位于漏极方向上的间隔件的下部朝着衬底移动，使得电流流过衬底。因此，从漏极流向源极的电流量骤然增加，引起快速跳回现象。从而使BV(击穿电压)特性变坏。
发明内容
本发明实施例涉及一种半导体器件及其制造方法。
本发明实施例涉及一种具有改进的击穿电压特性的半导体器件及其制造方法。
本发明实施例涉及一种能够防止出现撞击电离的半导体器件及其制造方法。
根据一个实施例的一种半导体器件包括：第二导电半导体衬底；栅电极，在半导体衬底上的；第一导电漂移区，形成在栅电极的相对的两侧处；源区或者漏区，形成在第一导电漂移区中；以及STI区，形成在位于栅电极与漏区之间的漂移区中。位于STI区的下部处的漂移区具有杂质浓度在向下方向上减少、然后增加并且再次减少的掺杂分布。
根据本发明一个实施例的一种用于制造半导体器件的方法包括以下步骤：以第一能量将第一导电杂质注入第二导电半导体衬底中，由此在第二导电半导体衬底中形成第一杂质区；以第二能量将第一导电杂质注入第二导电半导体衬底中，由此在第二导电半导体衬底中形成第二杂质区；对半导体衬底进行热处理以通过分别扩散第一和第二杂质区来形成第一导电漂移区；在第二导电半导体衬底上形成栅电极；通过将高浓度的第一导电杂质注入漂移区中，在第一导电漂移区中形成源区或者漏区；以及通过有选择地蚀刻栅电极与漏区之间的第一导电漂移区来形成用绝缘材料填充的STI区。
本发明能够改进击穿电压特性，防止碰撞电离。
附图说明
图1是图示了根据一个实施例的半导体器件的截面图；
图2是图示了根据一个实施例的半导体器件中漂移区的掺杂分布的曲线图；
图3至图8是图示了根据一个实施例的用于制造半导体器件的方法的截面图；
图9是图示了根据一个实施例的半导体器件的开态击穿电压(on-breakdown voltage)特征的曲线图；以及
图10和图11是图示了在一个实施例的半导体器件中漂移驱动工艺的特性随时间变化的曲线图。
具体实施方式
下文将参照附图来描述根据实施例的半导体器件及其制造方法。
图1是图示了根据一个实施例的半导体器件的截面图。
参照图1，包含N型杂质的漂移区20形成于P型半导体衬底10中，而包含高浓度N型杂质的源区30或者漏区40形成于漂移区20中。
然后，栅电极50形成于漂移区20之间。栅电极50包括栅绝缘层51、栅多晶硅52和间隔件53。
漂移区20水平地形成于栅电极50以下。漂移区20具有以下掺杂分布，其中杂质浓度在从半导体衬底10的表面向下的方向上逐渐地增加、然后减少并且再次逐渐地增加、然后减少。
通过在沟槽中填充绝缘材料来形成的STI(浅沟槽隔离)区60形成在栅电极50与源区30之间的漂移区20中。另外，同样的STI区60形成在栅电极50与漏区40之间的漂移区20中。
漂移区20使在栅电极50与漏区40之间的电场强度减小。
漂移区20必须具有足够宽度使得漂移区20可以增加栅电极50与漏区40之间的间隔。然而，由于必须以小尺寸制造半导体器件、在栅极与漏极之间的电流因漂移区20而减少、并且栅极电压增加，所以必须减小漂移区20的宽度。
根据该实施例，漂移区20的宽度减少而STI区60分别形成于漂移区20中。
STI区60形成于各漂移区20中，使得漂移区20的宽度可以减少而在栅电极50与漏区40之间的电场强度也可以减少。
同时，作为功率器件的特征的SOA(安全工作区)取决于当在栅电极50、源区30和半导体衬底10接地的状态下增加向漏区40施加的电压时所测得的击穿电压以及当在源区30和半导体衬底10接地而向栅电极50施加工作电压的状态下增加向漏区40施加的电压时所测得的开态击穿电压(BVon)。
击穿电压和接通击穿电压这两个特性根据漂移区20的掺杂分布而可能造成交替换位的现象(trade-off phenomenon)。
根据该实施例，独立地控制击穿电压和开态击穿电压这两个特性。具体而言，持续地维持漂移区20的掺杂浓度以使击穿电压特性恒定，并且改变漂移区20的掺杂分布以改进开态击穿电压特性。
图2是图示了在根据该实施例的半导体器件中漂移区在从STI区的下表面向下的方向上的掺杂分布的曲线图。
如图2中所示，漂移区20具有以下掺杂分布，其中杂质浓度在从与STI区60的下表面相接触的漂移区20开始沿深度方向上逐渐地减少、然后增加并且再次减少。
根据该实施例，当形成漂移区20时，在同一杂质剂量之下执行两步杂质注入。具体而言，分别以500KeV的注入能量和180KeV的注入能量来注入P离子，然后使P离子受到热处理工艺。
因此，漂移区20具有如图2中所示的掺杂分布。
同时，在STI区60形成于漂移区20中的半导体器件中，最强电场形成于与漏区40相邻的STI区60的下部61中。
在这样的状态下，随着电压施加到漏区40，电子经由STI区60的下部61从源区30朝着漏区40流动。因此，在与漏区40相邻的STI区60的下部61中可能出现撞击电离。
然而，在根据该实施例的半导体器件中，漂移区20具有如图2中所示的掺杂分布。因此，可以通过在从STI区60的下部61的深度方向上移位电子的移动路径来分布电子，使得可以防止出现撞击电离和快速跳回现象。
图3至图8是图示了根据该实施例的用于制造半导体器件的方法的截面图。
参照图3，在半导体衬底10上形成掩模层11。然后，P离子以400Kev至600KeV的注入能量注入到半导体衬底10中，由此形成第一杂质区21。根据该实施例，以500KeV的注入能量将P离子注入到半导体衬底10中。
参照图4，通过使用掩模层11以130KeV至230KeV的注入能量将P离子注入到半导体衬底10中，由此形成第二杂质区22。根据该实施例，以180KeV的注入能量将P离子注入到半导体衬底10中。
参照图5，执行漂移驱动工艺以去除掩模层11并且对半导体衬底10进行热处理，然后使第一杂质区21和第二杂质区22中包含的杂质扩散，由此形成漂移区20。
这时，执行漂移驱动工艺40分钟至50分钟。根据该实施例，执行漂移驱动工艺45分钟。
参照图6，有选择地去除各漂移区20的一部分，然后在漂移区20中填充绝缘材料，由此在漂移区20中形成STI区60。
参照图7，在漂移区20之间形成栅电极50，其中栅电极50包括栅极绝缘层51、栅极多晶硅52和间隔件53。
参照图8，将高浓度P离子注入到漂移区20中，由此在漂移区20中形成源区30或者漏区40。
图9是图示了根据该实施例的半导体器件的开态击穿电压特性的曲线图。
在图9中，水平轴代表漏电压VD而竖直轴代表漏电流ID。
图9示出了当形成漂移区20时执行两步杂质注入的第一情况与当形成漂移区20时执行一步杂质注入的第二情况的比较。
在执行一步杂质注入的情况下，当栅电压VG为32V时，如果漏电压VD大于38V，则漏电流骤然增加，这称为“快速跳回现象”。
图10和图11是图示了在该实施例的半导体器件中漂移驱动工艺的特性根据时间变化的曲线图。
图10示出了执行漂移驱动过程30分钟的情况，而图11示出了执行漂移驱动过程45分钟的情况。
参照图10和图11，在执行漂移驱动过程30分钟的情况下，当漏电压VD为38V时出现结击穿，使得可能出现沟道粘合。
然而，在执行漂移驱动过程45分钟的情况下，虽然漏电压VD大于40V，但是没有出现快速跳回现象。这代表了：在增加结之后，通过增加漂移驱动工艺的时间来增加击穿裕度，从而提高击穿电压特性。
该实施例涉及击穿电压特性改进的半导体器件及其制造方法。
该实施例涉及能够防止出现撞击电离的半导体器件及其制造方法。
在本说明书中提到的“一个实施例”、“实施例”、“示例性实施例”等，都意味着结合实施例所描述的特定的特征、结构、或特性被包含在本发明的至少一个实施例中。在本说明书各处出现的这些词语并不一定都指同一个实施例。此外，当结合任一实施例来描述特定的特征、结构、或特性时，则认为其落入本领域技术人员可以结合其它的实施例来实施这些特征、结构或特性的范围内。
虽然以上参考本发明的多个示例性实施例而对实施例进行了描述，但应理解的是，本领域人员可以导出落在此公开文件的原理的精神和范围内的许多其它改型和实施例。更具体地说，在此公开文件、附图以及所附权利要求书的范围内，能够对组件和/或附件组合排列中的排列进行各种变更与改型。除了组件和/或排列的变更与改型之外，本发明的其他应用对本领域技术人员而言也是显而易见的。

Claims (10)

1.一种半导体器件，包括：
第二导电半导体衬底；
栅电极，位于所述半导体衬底上；
第一导电漂移区，形成在所述栅电极的相对的两侧处；
源区和漏区，分别形成在所述第一导电漂移区中；以及
第一STI区，形成在所述栅电极和所述源区之间的所述漂移区中，以及第二STI区，形成在所述栅电极与所述漏区之间的所述漂移区中，
其中位于所述第一STI区和第二STI区的下部处的所述漂移区具有杂质浓度在向下的方向上减少、然后增加并且再次减少的掺杂分布。
2.如权利要求1所述的半导体器件，其中所述杂质包括P离子。
3.如权利要求1所述的半导体器件，其中所述杂质在所述栅电极以下水平地注入。
4.一种用于制造半导体器件的方法，所述方法包括以下步骤：
以第一能量将第一导电杂质注入第二导电半导体衬底中，由此在所述第二导电半导体衬底中形成第一杂质区；
以第二能量将所述第一导电杂质注入所述第二导电半导体衬底中，由此在所述第二导电半导体衬底中形成第二杂质区；
对所述半导体衬底进行热处理以通过分别扩散所述第一杂质区和所述第二杂质区来形成第一导电漂移区；
在所述第二导电半导体衬底上形成栅电极；
通过将高浓度的所述第一导电杂质注入所述漂移区中，在所述第一导电漂移区中分别形成源区和漏区；以及
通过有选择地蚀刻所述栅电极与所述漏区之间的所述第一导电漂移区、并且有选择地蚀刻所述栅电极与所述源区之间的所述第一导电漂移区，来形成用绝缘材料填充的两个STI区。
5.如权利要求4所述的方法，其中所述第一能量为400KeV至600KeV。
6.如权利要求4所述的方法，其中所述第二能量为130KeV至230KeV。
7.如权利要求4所述的方法，其中将所述热处理执行40分钟至50分钟。
8.如权利要求4所述的方法，其中位于所述两个STI区的下部处的所述漂移区具有杂质浓度在向下方向上减少、然后增加并且再次减少的掺杂分布。
9.如权利要求4所述的方法，其中所述杂质包括P离子。
10.如权利要求4所述的方法，其中所述杂质在所述栅电极以下水平地注入。
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