CN101296569A - 印刷电路板及其制造方法 - Google Patents
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Abstract
本发明公开了一种印刷电路板及一种制造印刷电路板的方法。制造印刷电路板的方法包括:通过依次堆叠绝缘层和电路图案层使得预定厚度的局部区域中只堆叠有绝缘层而形成多层板;以及去除多层板的局部区域中的绝缘层。通过使用该方法,可以制造出适于微型模块的印刷电路板。
Description
相关申请交叉参考
本申请要求于2007年4月27日向韩国知识产权局提交的第10-2007-0041536号韩国专利申请的权益,其公开内容全部结合于此以供参考。
技术领域
本发明涉及一种制造印刷电路板的方法。
背景技术
伴随电子器件微型化的趋势,旨在降低印刷电路板厚度的研究一直在进行。常规方法包括朝向减小夹层材料的厚度以使印刷电路板微型化的发展。然而,这可能需要在每一层上进行硬度加强操作,以补偿由于板中的夹层材料厚度减小而造成的硬度降低。此外还可能存在电流中阻抗改变的问题,以及在保证层与层之间的绝缘距离方面的问题。
发明内容
本发明一方面是提供确保硬度并且适于微型电子器件的一种印刷电路板及其制造方法。
本发明的一个方面提供一种制造印刷电路板的方法,该方法包括:通过交替堆叠电路图案层和绝缘层使得预定厚度的局部区域中只堆叠有绝缘层而形成多层板;以及从多层板的局部区域中去除绝缘层。
去除多层板的局部区域的绝缘层可以采用机械方法来完成,其中机械方法可以使用铣床来完成。
另外,去除多层板的局部区域的绝缘层的操作可以包括用机械方法去除预定厚度的一部分,以及用激光器去除预定厚度的剩余部分,从而露出电路图案层。这里,激光器举例来说可以是二氧化碳激光器。
本发明的另一个方面提供一种印刷电路板,该印刷电路板包括:第一多层板,由至少一层绝缘层和至少一层电路图案层构成;以及第二多层板,具有只堆叠在第一板表面的局部区域中的至少一层绝缘层和至少一层电路图案层。
本发明的其他方面及优点将在下列的描述中部分地阐述,并且通过该描述部分地变得显而易见,或者可以通过实践本发明而获知。
附图说明
图1是示出根据本发明实施例的制造印刷电路板的流程图。
图2A、图2B、图2C、图2D和图2E显示了示出根据本发明实施例的制造印刷电路板的工艺图。
图3A是根据本发明另一实施例的印刷电路板的透视图。
图3B是根据本发明另一实施例的第一多层板的透视图。
具体实施方式
下面将参考附图详细描述根据本发明某些实施例的印刷电路板及其制造方法,附图中,不管图号如何,那些相同或相应的部件由相同的参考标号表示,并且省略重复描述。
图1是示出根据本发明实施例的制造印刷电路板的流程图,图2A至图2E是显示了示出根据本发明实施例的制造印刷电路板的工艺图(以截面图描述)。图2中示出了多层板20、绝缘层21、电路图案层22、局部区域23、预定厚度24,和印刷电路板200。
图1的操作S11可包括交替堆叠电路图案层和绝缘层,其中在预定厚度的局部区域中只堆叠绝缘层,这可与图2A中描述的工序相一致。
由于交替堆叠绝缘层21和电路图案层22,可以形成如图2A所示的多层板20。此堆叠工艺可以通过在绝缘层21上依次堆叠电路图案层22来完成,或者通过共同堆叠其中电路图案层22已经形成在绝缘层21的表面上的多块板来完成。绝缘层21可以采用包括聚酯胶片(prepreg)的多种电气材料中的任一种,而电路图案层22可以使用多种已知方法的任一种来形成,诸如通过在绝缘层21上应用加成法或者通过在覆铜箔层压板上应用减成法而在绝缘层21上形成电路图案层22。
在堆叠过程中,多层板20可以被制成为只有绝缘层21堆叠在局部区域23内,如图2A所示。可以只用绝缘层21堆叠局部区域23直至预定厚度24。因此,在预定厚度24的局部区域23中可以没有电路图案层22,如图2A所示。局部区域23可能是在后续工艺中将被去除的部分,所以,由金属制成的电路图案层22可以不在这里形成,以方便去除工艺。
根据该实施例的局部区域23是指从多层板20上方看到的相应区域(图2描述为截面图),并且可是在后续工艺中要被去除的部分,从而局部区域23中的多层板20的厚度将由于被去除的量而变得更薄。因此,当将印刷电路板200结合在电子器件(未示出)中时,该局部区域23可以是可安置元件以确定该电子器件的总厚度的区域。在这种情况下,即使元件很厚,元件的从印刷电路板200的表面突出的量也至少减小了局部区域23的预定厚度24那么多。
根据该实施例的预定厚度24是指考虑到元件的厚度而将要去除的部分。在设计印刷电路板时,考虑到要去除预定厚度,可以只用绝缘层21来堆叠预定厚度24。
图1的操作S12可包括去除多层板的局部区域中的绝缘层,这可与在图2B和图2C中描述的工序一致。
图2B示出用机械方法去除厚度等于预定厚度24的局部厚度24a的绝缘层21。不去除所有预定厚度24的一个原因可能是,当使用机械方法(即铣床)去除绝缘层21时,电路图案层22的厚度可能太薄(大约9至18μm)而无法用铣床来操作直到露出电路图案层22为止,从而有损坏电路图案层22的风险。换言之,在不破坏电路图案层22的情况下去除绝缘层21可能超出了铣床的操作公差。
因此,在某些情况下,并不是所有的预定厚度24都可以通过机械方法被去除直到露出电路图案层22为止。然而,如果有可能在不损坏电路图案层22的情况下去除与预定厚度24相一致的所有绝缘层21(例如通过使用高精密设备),则可以只使用机械方法完成该工艺。该工艺的实施可以形成诸如图2C所示的多层板20。从图2C可以看出,与剩余厚度24b相一致的绝缘层21被留下。
如果只用如图2B所示的工艺就将绝缘层21去除到足够的厚度,并且安置在局部区域23中的元件不需要与电路图案层22电连接,那么图2B中的工艺就可能足够了。然而,如果想要去除与局部区域23的预定厚度24相一致的所有绝缘层21使得电路图案层22露出,那么可以实施如图2C所示的工艺。
图2C所示的工艺可以是采用激光器去除剩余厚度24b。在使用机械方法去除预定厚度24的局部厚度24a后,所剩下的厚度24b可以使用精密激光器来去除。该激光器可以是二氧化碳激光器。此工艺的结果是,完成其中至少一层电路图案层22被露出的印刷电路板200,如图2D所示。
然后,可进一步包括安装元件的操作,如图2E所示。在将元件25安装到与局部区域23相对应的位置中的情况下,不管元件的厚度如何,由于局部区域23的预定厚度24将被去除,因此模块的总厚度不会显著增加。图2E示出元件25如何可以具有比预定厚度24小的厚度,从而不会露出印刷电路板200的表面。
图3A是根据本发明另一实施例的印刷电路板的透视图,图3B是根据本发明另一实施例的第一多层板的透视图。图3A和3B中示出了印刷电路板30、第一多层板30a、第二多层板30b、绝缘层31a和31b、电路图案层32a和32b、电路图案33a和33b、剩余区域34,和局部区域35。
第一多层板30a可以构造为具有交替堆叠的绝缘层31a和电路图案层32a。第一多层板30a可以通过共同堆叠形成,或者可以具有依次堆叠的绝缘层31a和电路图案层32a。
第二多层板30b可以是只堆叠在第一多层板30a的局部区域35中的结构,其中绝缘层31b和电路图案层32b交替堆叠。由于第二多层板30b可以只堆叠在第一多层板30a的局部区域35中,所以在剩余区域34中可以没有第二多层板30b的部分。因此,印刷电路板30的厚度在与第一多层板30a的剩余区域34相对应的部分处可以较薄。
元件可以安装在第一多层板30a的该剩余区域34中。而且,第一多层板30a的电路图案33a可以和该元件电连接。可以考虑该元件要安装的位置而形成第一多层板30a的剩余区域34。当该元件(未示出)以这种方式安装在第一多层板30a的剩余区域34中时,即使元件的厚度可能很大,也可以降低模块的总厚度。
如上所述,本发明的某些实施例可以提供确保硬度且适合微型电子器件的印刷电路板。
尽管已经结合具体实施例详细描述了本发明的精神,但是这些实施例仅用于示意性目的而并非限制本发明。应该理解,在不背离本发明的范围和精神的情况下,本领域的技术人员可以对这些实施例进行改变或修改。
Claims (6)
1.一种制造印刷电路板的方法,该方法包括:
通过交替堆叠至少一层电路图案层和至少一层绝缘层使得预定厚度的局部区域中只堆叠有绝缘层而形成多层板;以及
去除所述多层板的所述局部区域的绝缘层。
2.根据权利要求1所述的方法,其中,所述去除步骤通过机械方法完成。
3.根据权利要求2所述的方法,其中,所述机械方法使用铣床来完成。
4.根据权利要求1所述的方法,其中,所述去除步骤包括:
通过机械方法去除所述预定厚度的一部分;以及
使用激光器去除所述预定厚度的剩余部分,以使电路图案层露出。
5.根据权利要求4所述的方法,其中,所述激光器是二氧化碳激光器。
6.一种印刷电路板,包括:
第一多层板,由至少一层绝缘层和至少一层电路图案层构成;以及
第二多层板,具有只堆叠在所述第一多层板的表面的局部区域中的至少一层绝缘层和至少一层电路图案层。
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CN103814629A (zh) * | 2011-06-21 | 2014-05-21 | 施韦策电子公司 | 电子组件及其制造方法 |
CN112038243A (zh) * | 2020-09-10 | 2020-12-04 | 英华达(上海)科技有限公司 | 集成电路封装方法 |
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DE102012203318A1 (de) * | 2011-12-22 | 2013-06-27 | Rohde & Schwarz Gmbh & Co. Kg | Verfahren zum Freilegen einer Schicht einer Leiterplatte und entsprechend freigelegte Leiterplatte |
US9648744B2 (en) * | 2012-07-24 | 2017-05-09 | Apple Inc. | Ejectable component assemblies in electronic devices |
CN203072246U (zh) * | 2012-12-31 | 2013-07-17 | 奥特斯(中国)有限公司 | 用于生产印制电路板的半成品 |
EP3075006A1 (de) | 2013-11-27 | 2016-10-05 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Leiterplattenstruktur |
AT515101B1 (de) | 2013-12-12 | 2015-06-15 | Austria Tech & System Tech | Verfahren zum Einbetten einer Komponente in eine Leiterplatte |
US11523520B2 (en) | 2014-02-27 | 2022-12-06 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for making contact with a component embedded in a printed circuit board |
AT515447B1 (de) | 2014-02-27 | 2019-10-15 | At & S Austria Tech & Systemtechnik Ag | Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte |
KR101720264B1 (ko) | 2015-09-04 | 2017-04-03 | 대덕전자 주식회사 | 회로기판 제조방법 |
CN109848567A (zh) * | 2019-01-30 | 2019-06-07 | 无锡深南电路有限公司 | 一种封装基板的镭射铣边设备和方法 |
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Cited By (4)
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CN103814629A (zh) * | 2011-06-21 | 2014-05-21 | 施韦策电子公司 | 电子组件及其制造方法 |
CN103814629B (zh) * | 2011-06-21 | 2017-08-22 | 施韦策电子公司 | 电子组件及其制造方法 |
CN112038243A (zh) * | 2020-09-10 | 2020-12-04 | 英华达(上海)科技有限公司 | 集成电路封装方法 |
CN112038243B (zh) * | 2020-09-10 | 2022-11-04 | 英华达(上海)科技有限公司 | 集成电路封装方法 |
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KR100885899B1 (ko) | 2009-02-26 |
CN101296569B (zh) | 2011-09-21 |
KR20080096278A (ko) | 2008-10-30 |
US7665206B2 (en) | 2010-02-23 |
JP2008277732A (ja) | 2008-11-13 |
US20080264687A1 (en) | 2008-10-30 |
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