CN101290887A - 半导体器件的制作方法 - Google Patents

半导体器件的制作方法 Download PDF

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CN101290887A
CN101290887A CNA2007100398108A CN200710039810A CN101290887A CN 101290887 A CN101290887 A CN 101290887A CN A2007100398108 A CNA2007100398108 A CN A2007100398108A CN 200710039810 A CN200710039810 A CN 200710039810A CN 101290887 A CN101290887 A CN 101290887A
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尹德源
廖奇泊
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

一种半导体器件的制作方法，包括下列步骤：提供包含栅极、源极和漏极的半导体衬底，其中栅极包含位于半导体衬底上的栅介电层；在半导体衬底上形成腐蚀阻挡层；对半导体衬底进行氢退火。经过上述步骤，降低栅介电层与半导体衬底之间界面能级，提高半导体器件可靠性。

Description

半导体器件的制作方法
技术领域
本发明涉及半导体器件的制作方法，尤其涉及用氢退火工艺制作半导体器件。
背景技术
为了提高金属配线相互的电气连接特性以及硅衬底与金属配线的电气连接特性、提高器件的特性和可靠性、提高制造时的成品率而进行氢退火。在半导体器件的制造中，氢退火是非常重要的工艺，例如，在动态随机存储器(Dynamic Random-Access Memory，DRAM)中，器件层间绝缘层或栅介电层中的氧化硅与半导体衬底界面附近的硅之间存在悬空键，而导致层间绝缘层或栅介电层与半导体衬底之间存在界面能级，通过该界面能级使漏电流从扩散层流向半导体衬底，而使DRAM的器件特性恶化。在氢退火中，向界面提供氢，通过氢使悬空键终结，而能够降低界面能级。
现有在半导体器件制作过程中进行氢退火的方法如图1所示，在半导体衬底100上形成栅介电层103，形成栅介电层103的方法为热氧化法，栅介电层103的材料为氧化硅；在栅介电层103上形成多晶硅层104；然后，在多晶硅层104上形成抗反射层105，在抗反射层105上形成第一光刻胶层(未图示)，经过曝光及显影工艺，定义后续栅极图形；以第一光刻胶层为掩膜，沿栅极图形依次刻蚀抗反射层105、多晶硅层104和栅介电层103至露出半导体衬底100，形成栅极106。
如图2所示，以栅极106为掩膜，在栅极106两侧的半导体衬底100中注入离子，形成轻掺杂漏极108；接着在栅极106两侧形成间隙壁114，与栅极106构成栅极结构；继续以栅极结构为掩膜，在半导体衬底100中注入离子，形成源极/漏极118。
如图3所示，以化学气相沉积法在栅极106、间隙壁114以及源极/漏极118上形成腐蚀阻挡层120；用化学气相沉积法在腐蚀阻挡层120上沉积层间绝缘层122，用于器件间的隔离；在层间绝缘层122上形成光刻胶层(未图示)，经过曝光显影工艺，形成用以定义后续接触孔的图形；以光刻胶层为掩膜，沿接触孔的图形，蚀刻栅极106上的层间绝缘层122及腐蚀阻挡层120至露出抗反射层105，或蚀刻源极/漏极118处的层间绝缘层122及腐蚀阻挡层120至露出半导体衬底100，形成接触孔121。
如图4所示，去除光刻胶层；用高密度等离子体化学气相沉积法在层间绝缘层122及接触孔内表面沉积扩散阻挡层123，防止后续沉积的金属扩散至层间绝缘层122中；用化学气相沉积法扩散阻挡层123上形成金属钨层，且金属钨层填充满接触孔；用化学机械研磨法研磨扩散阻挡层123和金属钨层至露出层间绝缘层122，形成钨插塞124。
然后，将半导体衬底100放入加热炉内，通入氢气进行退火，使栅介电层103中的氧化硅与半导体衬底100界面附近的硅的悬空键125终结，降低界面能级，防止后续漏电流进行半导体衬底100。
但是，近年来，随着半导体器件的细微化、高密度化以及多层化的发展，并且随着新的多层构造、电极材料、配线材料以及绝缘材料的采用，通过氢退火而使氢充分地扩散到所希望的界面变得困难起来。因此，必须延长退火时间或者提高退火温度。但是，如果延长退火时间就会带来降低生产能力的问题；而退火温度过高时，会使金属配线材料引起尖峰和小丘现象，导致可靠性降低的问题。为解决上述问题申请号为99125424的中国专利申请提出在不同的温度下对带有半导体器件的半导体衬底进行氢退火，以使氢充分地扩散至所希望的界面。
然而，需要调节不同温度，步骤繁琐；同时，由于氢要经过层间绝缘层和腐蚀阻挡层才能扩散至半导体衬底，扩散路径较长，氢仍不能完全扩散至半导体衬底，栅介电层与半导体衬底之间依然存在界面能级，进而导致后续漏电流进入半导体衬底，使半导体器件可靠性降低。
发明内容
本发明解决的问题是提供一种半导体器件的制作方法，降低栅介电层与半导体衬底之间的界面能级，避免漏电流流向半导体衬底，并简化步骤。
为解决上述问题，本发明提供一种半导体器件的制作方法，包括下列步骤：提供包含栅极、源极和漏极的半导体衬底，其中栅极包含位于半导体衬底上的栅介电层；在半导体衬底上形成腐蚀阻挡层；对半导体衬底进行氢退火。
所述氢退火的温度为400℃～500℃。
所述氢退火的时间为20分钟～30分钟。
所述腐蚀阻挡层的材料为氮氧化硅。
所述腐蚀阻挡层的厚度为300埃～500埃。
本发明提供一种半导体器件的制作方法，其特征在于，包括下列步骤：提供包含栅极、源极和漏极的半导体衬底，其中栅极包含位于半导体衬底上的栅介电层；在半导体衬底上形成腐蚀阻挡层；对半导体衬底进行氢退火；在腐蚀阻挡层上形成层间绝缘层，且层间绝缘层覆盖栅级；在层间绝缘层中形成金属插塞。
所述氢退火的温度为400℃～500℃。
所述氢退火的时间为20分钟～30分钟。
与现有技术相比，本发明具有以下优点：本发明在形成腐蚀阻挡层后就进行氢退火，氢只需通过腐蚀阻挡层就可扩散至半导体衬底中，氢可完全扩散至半导体衬底中，使栅介电层的氧化硅与半导体衬底界面附近的硅的悬空键终结，栅介电层与半导体衬底之间的界面能级降低，进而使后续漏电流不进入半导体衬底，提高半导体器件可靠性，并且本发明不需要在不同温度下退火，使工艺步骤简化。
附图说明
图1至图4是现有在半导体器件制作过程中进行氢退火的结构示意图；
图5是本发明在半导体器件制作过程中进行氢退火的第一实施例流程图；
图6是本发明在半导体器件制作过程中进行氢退火的第二实施例流程图；
图7至图12是本发明在半导体器件制作过程中进行氢退火的一个实施例结构示意图。
具体实施方式
本发明在形成腐蚀阻挡层后就进行氢退火，氢只需通过腐蚀阻挡层就可扩散至半导体衬底中，氢可完全扩散至半导体衬底中，使栅介电层的氧化硅与半导体衬底界面附近的硅的悬空键终结，栅介电层与半导体衬底之间的界面能级降低，进而使后续漏电流不进入半导体衬底，提高半导体器件可靠性，并且本发明不需要在不同温度下退火，使工艺步骤简化。为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图5是本发明在半导体器件制作过程中进行氢退火的第一实施例流程图。如图5所示，执行步骤S101，提供包含栅极、源极和漏极的半导体衬底，其中栅极包含位于半导体衬底上的栅介电层；执行步骤S102，在半导体衬底上形成腐蚀阻挡层；执行步骤S103，对半导体衬底进行氢退火。
图6是本发明在半导体器件制作过程中进行氢退火的第二实施例流程图。如图5所示，执行步骤S201，提供包含栅极、源极和漏极的半导体衬底，其中栅极包含位于半导体衬底上的栅介电层；执行步骤S202，在半导体衬底上形成腐蚀阻挡层；执行步骤S203，对半导体衬底进行氢退火；执行步骤S204，在腐蚀阻挡层上形成绝缘层，且绝缘层覆盖栅级；执行步骤S205，在绝缘层中形成金属插塞。
图7至图12是本发明在半导体器件制作过程中进行氢退火的一个实施例结构示意图。如图7所示，用热氧化法在半导体衬底200上形成栅介电层203，栅介电层203的材料为氧化硅；然后用化学气相沉积法在栅介电层203上形成多晶硅层204；再于多晶硅层204上用化学气相沉积法形成抗反射层205，本实施例中，所述抗反射层205的材料为氮化硅，用于后续蚀刻过程中保护下面的多晶硅层；在抗反射层205上形成第一光刻胶层(未图示)，经过曝光及显影工艺，定义后续栅极图形；以第一光刻胶层为掩膜，沿栅极图形依次刻蚀抗反射层205、多晶硅层204和栅介电层203至露出半导体衬底200，形成栅极206。
如图8所示，用灰化法去除第一光刻胶层；以栅极206为掩膜，在栅极206两侧的半导体衬底200中注入离子，形成轻掺杂漏极208。
本实施例中，如果是PMOS则在半导体衬底200中注入p型离子，形成轻掺杂漏极208，例如硼离子；如果是NMOS则在半导体衬底200中注入n型离子，形成轻掺杂漏极208，例如磷离子。
如图9所示，接着用高密度等离子体化学气相沉积法在栅极206两侧形成间隙壁214，与栅极206构成栅极结构；继续以栅极结构为掩膜，在半导体衬底200中注入离子，形成源极/漏极218。
本实施例中如果是PMOS则在半导体衬底200中注入p型离子，形成源极/漏极218，例如硼离子；如果是NMOS则在半导体衬底200中注入n型离子，形成源极/漏极218，例如磷离子。
如图10所示，以化学气相沉积法在栅极206、间隙壁214以及源极/漏极218上形成厚度为300埃～500埃的腐蚀阻挡层220，用以后续蚀刻过程中保护腐蚀阻挡层220下面的膜层，所述腐蚀阻挡层220的材料为氮氧化硅或氮氧化硅和氮化硅的组合，通过沉积腐蚀阻挡层200由于应力作用，使栅介电层203与半导体衬底200界面的缺陷呈现出来；然后，将半导体衬底200放入加热炉内，通入氢气进行退火，使栅介电层203中的氧化硅与半导体衬底200界面附近的硅的悬空键225终结，降低界面能级。
本实施例中，所述氢退火的温度为400℃～500℃，具体温度例如400℃、420℃、440℃、460℃、480℃或500℃等。
所述氢退火的时间为20分钟～30分钟，具体退火时间例如20分钟、22分钟、24分钟、26分钟、28分钟或30分钟等。
本实施例中，腐蚀阻挡层220的厚度具体例如300埃、320埃、340埃、360埃、380埃、400埃、420埃、440埃、460埃、480埃或500埃等。
如图11所示，用化学气相沉积法在腐蚀阻挡层220上沉积厚度为8000埃～12000埃的层间绝缘层222，用于器件间的隔离，所述层间绝缘层222的材料为氧化硅；在层间绝缘层222上形成第二光刻胶层(未图示)，经过曝光显影工艺，形成用以定义后续接触孔的图形；以第二光刻胶层为掩膜，沿接触孔的图形，蚀刻栅极206上的层间绝缘层222及腐蚀阻挡层220至露出抗反射层205，或蚀刻源极/漏极218处的层间绝缘层222及腐蚀阻挡层220至露出半导体衬底200，形成接触孔221。
本实施例中，层间绝缘层222的厚度具体例如8000埃、8500埃、9000埃、9500埃、10000埃、10500埃、11000埃、11500埃或12000埃等。
如图12所示，灰化法去除第二光刻胶层；用高密度等离子体化学气相沉积法在层间绝缘层222及接触孔内表面沉积扩散阻挡层223，防止后续沉积的金属扩散至层间绝缘层222中，所述扩散阻挡层223的材料为钛和氮化钛；用化学气相沉积法扩散阻挡层223上形成金属钨层，且金属钨层填充满接触孔；用化学机械研磨法研磨扩散阻挡层223和金属钨层至露出层间绝缘层222，形成钨插塞224。
本发明虽然以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以做出可能的变动和修改，因此本发明的保护范围应当以本发明权利要求所界定的范围为准。

Claims (8)

1.一种半导体器件的制作方法，其特征在于，包括下列步骤：
提供包含栅极、源极和漏极的半导体衬底，其中栅极包含位于半导体衬底上的栅介电层；
在半导体衬底上形成腐蚀阻挡层；
对半导体衬底进行氢退火。
2.根据权利要求1所述半导体器件的制作方法，其特征在于：所述氢退火的温度为400℃～500℃。
3.根据权利要求2所述半导体器件的制作方法，其特征在于：所述氢退火的时间为20分钟～30分钟。
4.根据权利要求1所述半导体器件的制作方法，其特征在于：所述腐蚀阻挡层的材料为氮氧化硅。
5.根据权利要求4所述半导体器件的制作方法，其特征在于：所述腐蚀阻挡层的厚度为300埃～500埃。
6.一种半导体器件的制作方法，其特征在于，包括下列步骤：
提供包含栅极、源极和漏极的半导体衬底，其中栅极包含位于半导体衬底上的栅介电层；
在半导体衬底上形成腐蚀阻挡层；
对半导体衬底进行氢退火；
在腐蚀阻挡层上形成层间绝缘层，且层间绝缘层覆盖栅级；
在层间绝缘层中形成金属插塞。
7.根据权利要求6所述半导体器件的制作方法，其特征在于：所述氢退火的温度为400℃～500℃。
8.根据权利要求7所述半导体器件的制作方法，其特征在于：所述氢退火的时间为20分钟～30分钟。
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