TW412862B - Method for fabricating semiconductor integrated circuit device - Google Patents

Method for fabricating semiconductor integrated circuit device Download PDF

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Publication number
TW412862B
TW412862B TW087109184A TW87109184A TW412862B TW 412862 B TW412862 B TW 412862B TW 087109184 A TW087109184 A TW 087109184A TW 87109184 A TW87109184 A TW 87109184A TW 412862 B TW412862 B TW 412862B
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Taiwan
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film
manufacturing
integrated circuit
insulating film
circuit device
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TW087109184A
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Chinese (zh)
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Makoto Yoshida
Naofumi Ohashi
Yoshitaka Takaki
Isamu Asano
Takahiro Kumauchi
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention is capable of leveling the insulator film on the gate electrodes based on the microgap without degrading the characteristic of the MISFET. The present method comprises forming an SOG film by spin-coating over the gate electrode 14A (word line WL) of a memory cell selecting MISFET Qs and the gate electrodes 14B, 14C of a peripheral circuit in a DRAM, sintering the SOG film 24 by heat treatment at 800 DEG C for about 1 min, and leveling a silicon oxide film 25 deposited thereon by CMP, thus improving the performance of filling the microgap between the gate electrodes 14A (word lines WL) themselves while leveling the insulator film on the gate electrodes 14B, 14C.

Description

412862 A7 ____B7五、發明説明（彳) (本發明所臈之技術領域） 本發明係有關於半導體積體電路裝置之製造技術，特 別係有is於一種應用在具有Μ I SFET ( Metal Insulator Semiconductor Field Effect Transistor )之半導體積體電路 的有效的技術。 (習知技術） D R A M ( Dynamic Random Access Memory )的記憶 格係被配置在呈矩陣狀配列在半導體積體基枚之主面的多 個字元線與多個位元線的交點，而由1個資料儲存用電容 元件與串聯於此的1個記億格選擇用Μ I S F E T所構成 。記憶格選擇用Μ I S F Ε Τ係被形成在周圔爲元件分離 領域所包圍的活性領域，而至要由閘絕緣膜，與字元線一 體被構成的閘極，以及構成源極、汲極的一對的半導體積 體領域所構成。位元線被配置在記憶格選擇用 MI SFET的上部，而與爲在其延伸方向相鄰的2個記 憶格選擇用Μ I S F Ε Τ所共用的源極，汲極的其中一個 在電氣上相連接。資料儲存用電容元件，同樣地被配置在 記憶格選擇用MISFET的上部，而與上述源極，汲極 的另一者在電氣上相連接。 ， 如上所述，D RAM的記億格，則將位元線與資料儲 存用電容元件配置在字元線的上部。更者，在該記憶格的 上部則通常配置有多層的A 1配線。因此，在記憶體陣列 的領域内，會因爲該些電容元件的電極d配線而發生段差 (誚先閲讀背面之注意事項再填艿本頁) 訂 本紙张尺度通用中留囤家標埤（CNS ) Λ4規格（210X297公釐） -4- 412862 A7 _B7 五、發明説明ς ) 。又連在形成有記億體陣列之領域（記憶體陣列）與周邊 電路領域之間，也會發生幾乎相當於資料儲存用電容元件 之高度段差- 但是當在如此的段差上形成配線時，則在光石印處理 時，曝光的焦點會發生偏差，且在段差部會發生蝕刻殘留 現象，因此無法精度良好地形成配線，而發生短路或是斷 路等的不良情形。因此，爲了要解決該些問題，使下層配 線與上層配線絕緣之層間絕緣膜變爲平坦的技術則不可缺 少。 在配線過程中，爲使因爲有無A 1配線而產生之凹凸 變爲平坦，一般乃使用S 0 G ( Spin On Glass )膜，而爲 了使因爲Μ I S F E T的閘極所產生之凹凸變爲平坦，一 般乃使用 BPSG ( Boron doped phospho silicate Glass ) 膜- 炒漭部中"梂^扃兵Η消含竹社印51 <請先閲讀背面之注意事項再填寫本頁) 特開平9 — 6 4 3 0 3號公報則揭露一在位元線的上 部配匱資料儲存用電容元件的COB ( Capacitor Over Bitline )構造的DRAM。該公報中所載的DRAM ·位 在位元線與其上部之位元線之間的絕緣膜，以及位在位元 線與其上部之資料儲存用電容元件之間的絕緣膜•則分別 藉著由B P S G膜而構成以使絕緣膜變爲、平坦"又，該 DRAM，藉著以氧化矽膜，SOG膜以及氧化矽膜等3 層膜來構成位在資料儲存用電容元件與其上部之A 1配線 之間的絕緣膜，試圖減低因爲資料儲存用電容元件間的凹 部所造成_的段差。 本紙張尺度递用中國困家標埤（CNS > Μ規格（210X297公釐） -5- 412862 A7 B7_ 五、發明説明（3 ) (#先閲讀背面之注意事項再填寫本頁) 又，在特開平9 一 4 5 7 6 6號公報中所記載的 DRAM，則使用含有高濃度（1 3莫耳％左右）B (硼 )之具#高的reflow特性的B P S G膜，而可以緩和位在 記憶體陣列與周邊電路領域之邊界領域的急陡的段差。 (本發明所要解決的課題） 本發明人乃針對使用B P S G膜或是S 0G膜的絕緣 膜的平坦化技術加以檢討如下。 在DRAM的製造過程中，當在半導體基板上形成記 憶格選擇用MISFET以及週邊電路的MISFET( η通道型MISFET以及p通道型MISFET)後， 更在該些的上部堆積包含了 B P S G膜的絕緣膜。之後， 則在氮等的惰性氣體環境中•在8 5 0〜9 0 〇°C下，對 半導體基板實施1 0〜2 0分鐘左右的熱處理，藉由使 BPSG膜軟化流動（reflow )，可以藉由BPSG膜來 掩埋記憶格之閘極（字元線）之間》又，之後，藉著以濕 蝕刻或是乾蝕刻對包含該B P S G膜的絕緣膜實施平坦蝕 刻（etch back )，除了更可以改善絕緣膜的平坦性外，也 可以減小絕緣膜的厚度•而在以後的過程中，可以減低在 該絕緣膜所形成之接觸孔的縱橫比。 但是對於2 5 6M位元以後的DRAM，構成記憶格 之記億格選擇用MI SFET的閘長度成爲〇 . 25//m 以下，且相鄰之閘極（字元線）彼此的間隔則與此相等， 或在此以下，即使是讓B P S G膜在高溫下長時間地軟化 v * . 本紙張尺度珀扣中國g家標準（（，NS ) A4规格（210X297公藿） -6- 經系部中ί):椋ί?-局只工消1合竹社印來 __412862 b7_五、發明説明（4 ) ί； 流動·也很難完全埋住閘極（字元線）之間，而會殘留在 位在字元線之間的Β Θ S G膜中在以後的過程，雖然在 B P s b膜形成多個接觸孔，而在該接觸孔內形成導體層 ，但是如上所述，由於上述的孔隙，因此會有在接觸孔內 的導體層會彼此短路的問題。 又，B P S G膜的平坦蝕刻過程，因爲在形成膜時之 膜厚的變動或蝕刻速度的變動的關係，因此在實施平坦蝕 刻後，很難確保膜厚的均一性，且難以減低接觸孔的縱橫 比。 又，在形成上述微細的MISFET後，因爲 BPSG膜的軟化流動（refl〇w )的關係，因此當進行長 時間的熱處理時，則在源極，汲極中的雜货會擴散到基板 •而無法實現淺接合。 更者，2 5 6M位以後的DRAM，爲了要減低閘極 的寄生電阻，則必須採用使用包含金屬層之低電阻導電材 料的閘極加工製程。而可以被當作該種的低電阻閘極材料 則是一在多晶矽膜之上積層髙熔點金屬膜的所謂的多金屬 (polymetal )。由於多金屬的面電阻低到2 Ω/□左右* 不只可以當作閘極材料使用，也可以當作配線材料來使用 。高熔點金屬，則可以使用，即使是在β 0 0 t以下的低 溫製程，也能顯示出良好的低電阻性，且電子遷移耐性髙 的W，Mo，Ti 等。 但是，當在具有上述之多金屬構造之閘極的 MI SFET之上部堆積BPSG膜，而進行高溫，長時 {谇先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度通州中國园家標埤（CNS ) Λ4規格（2丨0Χ297公釐） 412862 A7 _B7 五、發明説明（5 )' 間的軟化流動（reflow )時，則會有高熔點金靨變差’或 是高熔點金屬與多晶矽膜發生反應，而形成高電阻的金屬 矽化物層的崗題。 因此，對於如2 5 0M位元以後的DRAM般，使用 閘極彼此之間隔在0 . 25/zm以下的MI SFET，而 構成電路的裝置而言，爲了要確保位在閘極之上部的絕緣 膜的平坦性•則變得無法使用B P S G膜。 本發明之同時在於提供一種在不使Μ 1 S F E T的特 性變差的情況下，可以使依微細的間隔而形成之位在電極 配線之上部的絕緣膜變爲平坦的技術。 又本發明之目的在於供一種在以絕緣膜來掩埋依微細 的間隔而形成的電極配線之間時，可以防止發生孔隙的技 術。 又本發明之目的在於防止形成於絕緣膜之通孔內的導 體層不會在通孔之間互相造成短路。 本發明之上述以及其他的目的與新的特徴，則可由本 說明書之記載以及所附圖面而明白。 (解決課題的手段） 在本案所揭露的發明中，若是簡單地說明代表例的槪 . \ 要內容則如下。 (1 )、本發明之半導體積體電路裝置之製造方法， 其主要係一被配置在沿著半導體基板之主面的第1方向而 延伸存在的多個字元線與沿著第2方向而延伸存在的多個 * 本紙張尺度i4用中國國家標肀{ CNS ) Λ4現格（2丨0X297公釐） (请先閲讀背面之注意事項再填寫本頁) 訂 -8- 纣"·部中决梂箄扃兵工消费合作釭印^ 41286,. at ___B7 五、發明説明（6 ) ' 位元線的交點，包含一具有由備有與上述字元線一體被形 成的閘極的記憶格選擰用Μ I S F E T與串聯於此之資料 儲存用it容元件所構成之記憶格的D R AM的半導體積體 電路裝置之製造方法，其特徵在於： (a ) 當在半導體基板的主面上堆積第1導電膜後 ’對_h述第1導電膜實施圖案，而形成成爲記億格選擇用 Μ I S F ET之閘極的字元線的過程及； (b ) 在以SOG膜來被覆上述字元線之間後，對 上述S 0 G膜實施熱處理的過程· (2 )、本發明之半導體積體電路裝匱之製造方法， 上述S 0 G膜的被覆與熱處理乃分別分成多次的過程來進 行。 (3 )、本發明之半導體稹體電路裝置之製造方法， 在上述過程（b)之後，在上述SOG膜的上述堆積第1 氧化矽膜，藉著至少以CMP法對上述第1氧化矽膜實施 硏磨•而使其表面變爲平坦。 (4)、本發明之半導體積體電路裝置之製造方法， 在上述電極配線的上部形成氮化矽膜，在以CMP法對上 述第1氧化矽膜以及SOG膜實施硏磨之際，將上述氮化 矽膜當作阻止膜來使用。 、 (5 )、本發明之半導體積體電路裝置之製造方法， 在以上述CMP法而硏磨的上述第1氧化矽膜的上部堆積 第2氧化矽膜。 (6 )、本發明之半導體積體電路裝置之製造方法· 、* . 本紙張尺度適用中S®家標净（（，NS ) Λ4規格（2IOX297公釐} (請先閱讀背面之注意事項再填寫本頁) 訂 -9- 412862 at B7 _ · ί。； — 五、發明説明（7 )' 藉著以CMP法來硏磨S 0G膜，而使其表面變得平坦。 {邡先閲讀背面之注意事項再填寫本頁) (7 )、本發明之半導體稹體電路裝置之製造方法· 在上述ί|極配線的上部形成氮化矽膜，在以CMP法來硏 磨上述S 0 G膜之際，將上述氮化矽膜當作阻止膜來使用 〇 (8 )、本發明半導體積體電路裝置之製造方法，在 以上述CMP法而硏磨的上述S 0 G膜的上部堆稹第1氧 化矽膜。 (9)、本發明之半導體積體電路裝置之製造方法， 上述第1導電膜至少包含金屬膜。 (1 0 )、本發明之半導體積體電路裝置之製造方法 ，上述第1導電膜係由多晶矽膜，由堆積在其上部的WN 膜或T i N膜所形成的障壁層，以及堆積在其上部的W膜 所形成》 (1 1 )、本發明之半導體積體電路裝置之製造方法 ，上述SOG膜的熱處理條件爲800 eC，1分鐘左右。 (1 2)、本發明之半導體積體電路裝置之製造方法 ，上述互相鄰接之上述字元線彼此的間隔爲由光石印之解 析極限所決定的最小尺寸左右· (1 3 )、本發明之半導體積體電路裝置之製造方法 % ，以來源氣體利用臭氧與TEOS的電漿CVD法來堆積 上述第1氧化矽膜。 (1 4 )、本發明之半導體積體電路裝置之製造方法 *在對包含上述字元線之上部的上述S;0 G膜的絕緣膜實 本紙張尺度適用中國囤家標埤（（>15)六4規格（210><297公釐> -10- .½¾•部中次枒準局OCJ·.消灸合竹ii印3i 412862 at ___B7___ 五、發明说明（8 ) 施乾蝕刻而形成連接孔後，利用包含氟酸的洗淨液來淸洗 上述連接孔的內部。_ (i 5 )、本發明之半導體積體電路裝置之製造方法 ，其主要係一被配置在沿著半導體基板之主面的第1方向 而延伸存在的多個字元線與沿著第2方向而延伸存在的多 個位元線的交點，包含一具有由備有與上述字元線一體被 形成的閘極的記億格選擇用Μ I S F E T與串聯於此之資 料儲存用電容元件所構成之記億格的D RAM的半導體積 體電路裝置之製造方法，其特徴在於： (a ) 在半導體基板的主面形成記憶格選擇用 MI SFET的過程； (b) 當在上述記憶格選擇用MISFET的上部 堆積第1絕緣膜後，對上述第1絕緣膜實施開孔，在上述 記憶格選擇用Μ I S F ET之源極，汲極之其中一個的上 部形成第1接觸孔，而在另一個的上部形成第2接觸孔的 過程： (c) 當在上述第1絕緣膜的上部堆積第1導電膜 後，藉著對上述第1導電膜實施圖案，形成經由上述第1 接皤孔在電氣上與上述記憶格選擇用Μ I S F Ε Τ之源極 ，汲極的其中一個連接的位元線的過程及/ (d ) 在以SOG膜來被覆上述位元線之間後*對 上述S 0 G膜實施熱處理。 (1 6 )、本發明之半導體積體電路裝置之製造方法 ，上述S O G膜的被覆與熱處理分別分成多次的過程來進 >> - . 本紙張尺度边用中國囷家揉啤（（，NS)A4現格（2IOX297公瘦} <先閲讀背面之注.意事項再填*?本莨) ,ϊτ -11 - 41286¾ A7五、發明説明（9 ) 行- ^ ( 1 7 )、本發朗之半導體積體電路裝置之製造方法 ，藉著it上述第1導電膜實施圖案，予以同時形成上述位 元線與周邊電路的第1層配線。 (1 8 )、本發明之半導體積體電路裝置，其主要係 一具有多個由第1ΜΙSFET與串聯於此之資料儲存用 電容元件所構成的記憶格的記憶體陣列以及由多個第2 Μ I S F Ε Τ所構成之周邊電路的半導體積體電路裝置之 製造方法，其特徵在於： C a ) 在半導體基板上形成第1MI SFET的閘 極與第2MISFET的閘極的過程： (b ) 在位於上述第1MI SFET之閘極之兩端 的上述半導體基板表面形成用於構成上述第1 Μ I S F Ε T之源極，汲極的第1半導體領域，而在位於 上述第2ΜΙSFET之閘極之兩端的上述半導體基板表 面形成用於構成上述第2M I S F Ε T之源極，汲極的第 2半導體領域的過程： (c ) 如覆蓋上述第1，第2MI SFET般地形 成第1絕緣膜的過程： (d ) 在上述第1絕緣膜形成可讓上述第1 MI SFET之上述第1半導體領域露出的第1開孔的過 程；· (e ) 在上述第1開孔選擇性地形成多晶矽膜的過 程；— (妍先閲讀背面之注意事項再填寫本頁) 本紙張尺度通用中囡囷家標準（（、NS ) Λ4規格（2丨0X297公釐）. -12- 412862 at __ B7_ 五、發明説明（1() ) 〇 (f) 在上述多晶矽膜上形成第2絕緣膜的過程； (g ) 在上述第2絕緣膜形成第2開孔，而讓上述 多晶矽k露出的過程； (h ) 在上述第1 ，第2絕緣膜形成第3開孔’而 讓上述第2M I S F E T之上述第半導體領域露出的過程 及： (i ) 在上述第2，第3開孔內堆積導體層的過程 而使上述第2開孔與上述第3開孔以不同的過程形成 〇 (1 9 )、本發明之半導體積體電路裝置之製造方法 ，其主要係一具有被形成在半導體基板上的第1 Μ I S F E T的半導體積體電路裝置之製造方法，其特徵 在於： (a) 經由第1絕緣膜在半導體基板上形成成爲第 1MI SFET之閘極的第1導體層的過程； (b ) 在位於上述第1導電膜之兩端的上述半導體 基板表面形成可當作上述第1MISFET之源極，汲極 來使用之第1以及第2半導體領域的過程； (c ) 如覆蓋上述第1MI SFET般地塗佈第2 絕緣膜，而對上述第2絕緣膜實施熱處理的過程： (d ) 在上述第1絕緣膜形成可讓上述第1 Μ I SFET的第1半導體領域露出的第1開口以及可讓 上述第2半導體領域霣出的第2開口的過程及； 、* j 本紙張尺度珀州中S®家標準（C'NS >Λ4坑格（210X297公釐） (对先閱讀背面之注意事項再填寫本I) 訂 ^! -13- 412862 A7 B7 五、發明説明（）’ 11 (e ) 在上述第1以及第2開口形成第2導體層的 過程。 (2 0 )、本發明之半導體積體電路裝置之製造方法 ，在上述過程（d)與（e )之間更具有（f )以氟酸來 淸洗上述第1以及第2開口的過程。 (2 1 )、本發明之半導體積體電路裝置之製造方法 ，在上述過程（c )與（d )之間更具有（g )以機械地 以及化學地來硏磨上述第2絕緣膜的過程* (2 2 )、本發明之半導體積體電路裝置之製造方法 ，在上述過程（c)與（d)之間更具有（h)在上述第 2絕緣膜上堆積第3絕緣膜，而以機械地以及化學地來硏 磨上述第3絕緣膜的過程。 (2 3 )、本發明之半導體積體電路裝置之製造方法 ，其主要係一具有被形成在半導體基板上的第1 Μ I S F E T的半導體積體電路裝置之製造方法，其特徵 在於： (a ) 經由第1絕緣膜在半導體基板上形成成爲第 1MI SFET之閘極的第1導體層的過程： (b ) 在位於上述第1導電膜之兩端的上述半導體 基板表面形成可當作上述第1M I S FJE T之源極，汲極 來使用之第1以及第2半導體領域的過程： (c ) 如覆蓋上述第1MI SFET般地塗佈第2 絕緣膜，而對上述第2絕緣膜實施熱處理的過程； (d ) 在上述第1絕緣膜形成可謀上述第1 * . 本紙乐尺度进用中SS家標中（ΓΝ5}Λ4規格（2丨0X297公釐） |_^_丨 t--Γ---------訂-------蛛- (锖先聞讀背面之注意事項再填寫本頁) M沪部屮央標-t局OCJ.消开合竹社印絮 -14- 4128G, at __B7_ 五、發明説明（12 )' MISFET的第1半導體領域的第1開口的過程： (e) 在上述第1開口形成第2導體曆的過程； (f ) 在上述第2導體層上形成第3絕緣膜的過程412862 A7 ____B7 V. Description of the invention (彳) (Technical field covered by the present invention) The present invention relates to the manufacturing technology of semiconductor integrated circuit devices, and particularly relates to an application in a semiconductor device Effective Transistor technology. (Conventional Technology) The memory cell system of DRAM (Dynamic Random Access Memory) is arranged at the intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix on a main surface of a semiconductor integrated circuit. A data storage capacitor element and a gis grid selection MOSFET are connected in series. The memory cell selection M ISF ΕΤ system is formed in the active area surrounded by the field of element separation, and the gate to be formed by the gate insulation film and the word line is integrated, and one of the source and drain is formed. Constituted in the field of semiconductor integrated circuits. The bit line is arranged on the upper part of the memory cell selection MI SFET, and the source shared by the two memory cell selection M ISF Ε Τ adjacent to the extending direction of the bit line is electrically connected to one of the drain electrodes. connection. The data storage capacitor element is similarly arranged above the memory cell selection MISFET, and is electrically connected to the other source and drain. As mentioned above, in the case of the DRAM's gigabyte, the bit line and the data storage capacitor element are arranged on the upper part of the word line. Furthermore, multiple layers of A 1 wiring are usually arranged on the upper part of the memory cell. Therefore, in the field of memory arrays, step differences will occur due to the wiring of the electrodes d of these capacitive elements (诮 read the precautions on the back before filling this page) ) Λ4 specification (210X297mm) -4- 412862 A7 _B7 V. Description of the invention ς). Even between the area where the memory array is formed (memory array) and the area of peripheral circuits, a height step almost equivalent to that of a data storage capacitor element occurs. However, when wiring is formed on such a step, During the light lithography process, the focus of the exposure will be deviated, and the residual phenomenon of etching will occur at the stepped portion. Therefore, the wiring cannot be formed with high accuracy, and short circuits or open circuits occur. Therefore, in order to solve these problems, a technique for flattening the interlayer insulating film between the lower wiring and the upper wiring is indispensable. In the wiring process, in order to flatten the unevenness caused by the presence or absence of A 1 wiring, an S 0 G (Spin On Glass) film is generally used, and in order to flatten the unevenness caused by the gate of the M ISFET, Generally, a BPSG (Boron doped phospho silicate Glass) film is used-fried 漭 部 中 " 梂 ^ 扃 兵 Η 消 含 竹 社 印 51 < Please read the notes on the back before filling this page) JP 9-9 6 4 No. 3 03 discloses a DRAM having a COB (Capacitor Over Bitline) structure in which a capacitor element for data storage is arranged on a bit line. The DRAM contained in the bulletin is the insulating film between the bit line and the bit line above it, and the insulating film between the bit line and the data storage capacitor element above it. The BPSG film is formed so that the insulating film becomes flat. "The DRAM is composed of a three-layer film such as a silicon oxide film, an SOG film, and a silicon oxide film. The insulating film between the wires is intended to reduce the step difference caused by the recesses between the data storage capacitor elements. The standard of this paper is Chinese standard (CNS > M size (210X297mm) -5- 412862 A7 B7_ V. Description of the invention (3) (#Read the precautions on the back before filling this page) Also, in The DRAM described in Japanese Patent Application Laid-Open No. 9- 4 5 7 6 6 uses a BPSG film with a high reflow characteristic containing a high concentration (about 13 mol%) B (boron), which can relax the location The steep step between the memory array and the peripheral circuit boundary area. (Problems to be Solved by the Invention) The inventors reviewed the planarization technology of an insulating film using a BPSG film or a SOG film as follows. In DRAM In the manufacturing process, when a MISFET for memory cell selection and a MISFET for peripheral circuits (n-channel MISFET and p-channel MISFET) are formed on a semiconductor substrate, an insulating film including a BPSG film is deposited on top of these. In an inert gas environment such as nitrogen, the semiconductor substrate is subjected to a heat treatment for about 10 to 20 minutes at 850 to 900 ° C. By softening and reflowing the BPSG film, it can be borrowed. Buried by BPSG film Between grid gates (character lines), and then, by wet etching or dry etching, the insulating film including the BPSG film is etched back (etch back), in addition to improving the flatness of the insulating film In addition, the thickness of the insulating film can also be reduced. • In the later process, the aspect ratio of the contact holes formed in the insulating film can be reduced. The gate length of the MI SFET for grid selection is less than or equal to 0.25 // m, and the interval between adjacent gates (word lines) is equal to this, or below, even if the BPSG film is made to grow at a high temperature. Time to soften v *. This paper is standard Chinese standard ((, NS) A4 (210X297 gong) -6- Department of Economics Department): 椋 ί?来 _412862 b7_ V. Description of the invention (4) ί; It is also difficult to completely bury the gate (character line) between the flow, and it will remain in the B Θ SG film located between the character lines. In subsequent processes, although a plurality of contact holes are formed in the BP sb film, and a conductor layer is formed in the contact holes, As described above, due to the pores described above, there is a problem that the conductive layers in the contact holes are short-circuited to each other. In addition, in the flat etching process of the BPSG film, the thickness of the BPSG film is changed or the etching speed is changed. Therefore, it is difficult to ensure the uniformity of the film thickness and to reduce the aspect ratio of the contact hole after the flat etching is performed. Moreover, after the above-mentioned fine MISFET is formed, the softening flow (refl0w) of the BPSG film Therefore, when the heat treatment is performed for a long time, sundries at the source and the drain diffuse to the substrate, and shallow bonding cannot be achieved. Furthermore, in order to reduce the parasitic resistance of the gate, DRAMs after 25.6M bits must use a gate processing process using a low-resistance conductive material including a metal layer. The low-resistance gate material that can be regarded as this kind of material is a so-called polymetal, which is a layer of a plutonium melting metal film on a polycrystalline silicon film. Since the sheet resistance of polymetals is as low as about 2 Ω / □ *, it can be used not only as a gate material, but also as a wiring material. High-melting-point metals can be used. Even in low-temperature processes below β 0 0 t, W, Mo, Ti, etc., which exhibit good low resistance and have high electron migration resistance. However, when the BPSG film is deposited on the upper part of the MI SFET with the above-mentioned multi-metal structure gate, and the temperature is high, it will take a long time (谇 Please read the precautions on the back before filling this page)埤 (CNS) Λ4 specification (2 丨 0 × 297 mm) 412862 A7 _B7 V. Description of the invention (5) When the softening flow (reflow) between '5', there will be high melting point gold 靥 'or high melting point metal and polycrystalline silicon The film reacts to form a high-resistance metal silicide layer. Therefore, devices such as DRAMs with a capacity of more than 250 Mbits that use MI SFETs whose gates are spaced at less than 0.25 / zm are used to ensure the insulation located above the gates. Film flatness • It becomes impossible to use BPSG film. The present invention also provides a technology capable of flattening an insulating film formed on an upper portion of an electrode wiring formed at fine intervals without deteriorating the characteristics of M 1 S F E T. Another object of the present invention is to provide a technique capable of preventing voids from occurring when electrode wirings formed at fine intervals are buried with an insulating film. Another object of the present invention is to prevent the conductor layers formed in the through holes of the insulating film from causing short circuits between the through holes. The above and other objects and new features of the present invention will be apparent from the description of the present specification and the attached drawings. (Means for Solving the Problem) Among the inventions disclosed in this case, if the representative examples are briefly explained, the main contents are as follows. (1) The method for manufacturing a semiconductor integrated circuit device according to the present invention is mainly arranged in a plurality of word lines extending along a first direction of a main surface of a semiconductor substrate and along a second direction. Existing multiple * This paper size i4 uses the Chinese national standard {CNS) Λ4 is present (2 丨 0X297 mm) (Please read the precautions on the back before filling this page) Order-8- 纣 " · 部Seal of the Sino-Military War Industry Consumption Cooperation ^ 41286 ,. at ___B7 V. Description of the Invention (6) 'The intersection of the bit lines contains a memory with gates formed integrally with the word lines A method for manufacturing a semiconductor integrated circuit device of a DR AM using a memory cell composed of a M ISFET and a memory cell connected in series with an it capacity element for data storage is characterized in that: (a) when it is on the main surface of a semiconductor substrate After the first conductive film is deposited, a process of patterning the first conductive film described above to form a character line that is selected as a gate electrode of M ISF ET and (b) the SOG film is used to cover the above The process of heat-treating the above S 0 G film after the word lines. (2) A method for producing a semiconductor apparatus of the present invention Kui integrated circuit, the above-described heat treatment the coating film is the S 0 G are divided into a plurality of times to carry out the process. (3) In the method for manufacturing a semiconductor body circuit device of the present invention, after the above-mentioned process (b), a first silicon oxide film is deposited on the above-mentioned SOG film, and the first silicon oxide film is formed by at least a CMP method. Honing • Makes the surface flat. (4) In the method of manufacturing a semiconductor integrated circuit device of the present invention, a silicon nitride film is formed on the electrode wiring, and when the first silicon oxide film and the SOG film are honed by the CMP method, the above The silicon nitride film is used as a barrier film. (5) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, a second silicon oxide film is deposited on the upper portion of the first silicon oxide film which has been honed by the CMP method. (6) The manufacturing method of the semiconductor integrated circuit device of the present invention, *. This paper is applicable to S® family standard net ((, NS) Λ4 specifications (2IOX297 mm) (Please read the precautions on the back before (Fill in this page) Order-9- 412862 at B7 _ · ί .; — V. Description of the invention (7) 'By honing the S 0G film by the CMP method, the surface becomes flat. {邡 Read the back first (Please note this page before filling in this page) (7). Manufacturing method of the semiconductor body circuit device of the present invention · A silicon nitride film is formed on the above electrode wiring, and the S 0 G film is polished by the CMP method In this case, the silicon nitride film is used as a barrier film. (8) The method for manufacturing a semiconductor integrated circuit device of the present invention is stacked on the upper part of the S 0 G film polished by the CMP method. 1 silicon oxide film. (9) The method for manufacturing a semiconductor integrated circuit device according to the present invention, wherein the first conductive film includes at least a metal film. (1 0), The method for manufacturing a semiconductor integrated circuit device according to the present invention, the first 1Conductive film is formed by polycrystalline silicon film, WN film or T i N film deposited on top of it (1 1), the method for manufacturing a semiconductor integrated circuit device of the present invention, wherein the heat treatment conditions of the above-mentioned SOG film are 800 eC, about 1 minute. (1 2), In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the interval between the word lines adjacent to each other is about the minimum size determined by the analysis limit of the light lithography. (1 3) The semiconductor integrated circuit device according to the present invention The manufacturing method is%, and the above-mentioned first silicon oxide film is deposited by a plasma CVD method using ozone and TEOS as a source gas. (14) The manufacturing method of the semiconductor integrated circuit device of the present invention * The upper part of the above S; 0 G film insulation film actual paper size is applicable to Chinese storehouse standard ((> 15) six 4 specifications (210 > < 297 mm > -10-.½¾ ••)桠 准 局 OCJ · .Moxibustion Hezhu iiyin 3i 412862 at ___B7___ V. Description of the invention (8) After the connection holes are formed by dry etching, the inside of the connection holes is rinsed with a cleaning solution containing fluoric acid. (i 5), the semiconductor integrated circuit device of the present invention The manufacturing method mainly comprises an intersection of a plurality of word lines extending along a first direction along a main surface of a semiconductor substrate and a plurality of bit lines extending along a second direction. Manufacture of a semiconductor integrated circuit device having a gigabyte selection M ISFET provided with a gate electrode integrally formed with the above-mentioned word line and a D RAM composed of gigabytes of D RAM and a data storage capacitor connected in series. A method comprising: (a) a process of forming a memory cell selection MI SFET on a main surface of a semiconductor substrate; (b) depositing a first insulating film on the memory cell selection MISFET, and then insulating the first insulation The membrane is perforated. The process of selecting the source of M ISF ET in the memory cell, forming a first contact hole on the upper part of one of the drain electrodes and forming a second contact hole on the other part: (c) When the After the first conductive film is deposited on the first insulating film, a pattern is formed on the first conductive film to form a source of the M ISF Ε for electrical selection with the memory cell through the first connection hole. One of the drains The process of connecting the bit lines and / (d) After the space between the bit lines is covered with a SOG film, the S 0 G film is heat-treated. (16) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the coating and heat treatment of the above-mentioned SOG film are divided into multiple processes, respectively. ≫ > , NS) A4 (2IOX297 public thin) < Read the note on the back. Fill in the notes and then fill in the *? Ben 莨), ϊτ -11-41286¾ A7 V. Description of the invention (9) Line-^ (1 7), According to the method for manufacturing a semiconductor integrated circuit device of the present invention, by patterning the first conductive film described above, it is possible to form the bit line and the first layer wiring of the peripheral circuit at the same time. (18) The semiconductor product of the present invention A body circuit device, which is mainly a semiconductor having a memory array composed of a memory cell composed of a 1 MIT SFET and a data storage capacitor element connected in series therewith, and a peripheral circuit composed of a plurality of 2 MH ISF ET A method for manufacturing an integrated circuit device, comprising: C a) a process of forming a gate of a first MI SFET and a gate of a second MISFET on a semiconductor substrate: (b) at two ends of the gate of the first MI SFET The semiconductor substrate surface is formed for The source of the 1M ISF ET and the first semiconductor field of the drain, and the semiconductor substrate located on both ends of the gate of the 2M IFET is formed on the surface of the semiconductor substrate for forming the source of the 2M ISF ET. In the second semiconductor field: (c) forming the first insulating film as if covering the first and second MI SFETs: (d) forming the first insulating film on the first MI SFET The process of the first opening exposed in the first semiconductor field; (e) The process of selectively forming a polycrystalline silicon film in the first opening;-(Yan first read the precautions on the back before filling this page) This paper is universal China Standard ((, NS) Λ4 specification (2 丨 0X297 mm). -12- 412862 at __ B7_ V. Description of the invention (1 ()) 〇 (f) Form a second insulating film on the above polycrystalline silicon film (G) forming a second opening in the second insulating film, and exposing the polycrystalline silicon k; (h) forming a third opening in the first, second insulating film, and letting the second 2M The process of the above-mentioned semiconductor field of the ISFET and: (i) the above-mentioned second The process of stacking the conductor layers in the third opening causes the second opening and the third opening to be formed in different processes. (19) The method for manufacturing a semiconductor integrated circuit device of the present invention is mainly a A method for manufacturing a semiconductor integrated circuit device having a 1 MH ISFET formed on a semiconductor substrate, comprising: (a) forming a first conductor on a semiconductor substrate as a gate of a first MI SFET through a first insulating film; Layer process; (b) forming processes of the first and second semiconductor fields that can be used as the source and drain of the first MISFET on the surface of the semiconductor substrate located at both ends of the first conductive film; (c) The process of coating the second insulating film as if covering the first MI SFET, and heat-treating the second insulating film: (d) forming the first semiconductor film in the first semiconductor field that allows the first M I SFET The process of the exposed first opening and the second opening that allows the above-mentioned second semiconductor field to escape; and * j This paper size is the standard of the S® house in Perth (C'NS > Λ 4 pit (210X297 mm) (Note on the back of the first read This then fill I) set ^! -13- 412862 A7 B7 V. invention is described in () '11 (e) in the above process the second opening forming a second conductive layer, the first and. (2) The method for manufacturing a semiconductor integrated circuit device according to the present invention further includes (f) a process of washing the first and second openings with fluoric acid between the processes (d) and (e). (2 1) The method for manufacturing a semiconductor integrated circuit device of the present invention further includes (g) a process of honing the second insulating film mechanically and chemically between the processes (c) and (d). * (2 2) The method for manufacturing a semiconductor integrated circuit device of the present invention, further comprising (h) stacking a third insulating film on the second insulating film between the processes (c) and (d), and The process of honing the third insulating film mechanically and chemically. (2 3) The method for manufacturing a semiconductor integrated circuit device of the present invention is mainly a method for manufacturing a semiconductor integrated circuit device having a 1 M ISFET formed on a semiconductor substrate, which is characterized by: (a) The process of forming the first conductor layer on the semiconductor substrate through the first insulating film to become the gate of the first MI SFET: (b) forming on the surface of the semiconductor substrate at both ends of the first conductive film can be regarded as the first M IS The process of the first and second semiconductor fields using the source and sink of the FJE T: (c) The process of coating the second insulating film as if covering the first MI SFET and heat-treating the second insulating film ; (D) In the formation of the above-mentioned first insulating film, the above-mentioned first * can be achieved. In the SS family standard used in this paper music standard (ΓΝ5) Λ4 specification (2 丨 0X297 mm) | _ ^ _ 丨 t--Γ- -------- Order ------- Spider- (I read the notes on the back first and then fill out this page) M Shanghai Department Central Standard -T Bureau OCJ.Xiaokaihe Bamboo Club Print -14- 4128G, at __B7_ V. Description of the Invention (12) The process of the first opening in the first semiconductor field of the MISFET: (e) In the above first opening shape Forming a second conductor calendar; (f) forming a third insulating film on the second conductor layer;

I (g ) 在上述第3絕緣膜上形成第3導體層的過程 t (h) 在上述第3導體層上塗佈第4絕緣膜，而對 上述第4絕緣膜實施第2熱處理的過程； (i) 在上述第4絕緣膜形成第2開口，可讓上述 第3導體層的一部分露出的過程；及 (j) 在上述第2開口內形成第4導體層的過程； 而上述第1熱處理溫度較上述第2熱處理溫度爲高· (2 4 ).本發明之半導體積體電路裝置之製造方法 ，上述第3以及第4導體層則堆積鋁層。 (2 5 )、本發明之半導體積體電路裝置之製造方法 ，在上述過程（d )與（e )之間更具有（k )以氟酸來 淸洗上述第1開口之半導體基板表面的過程· (2 6 )，本發明之半導體積體電路裝置之製造方法 ，在上述過程（c )與（d )之間更具有以機械地以及化 學地來硏磨上述第2絕緣膜的過程β 、 (2 7 )、本發明之半導體積體電路裝置之製造方法 ，在上述過程（c )與（d )之間更具有（m)在上述第 2絕綠膜上堆積第5絕緣膜，而以機械地以及化學地來硏 磨上述第'5絕緣膜的過程。 本紙伕尺度谪用中國围家標毕（rNS M4規格（2丨0X297公釐） {对先閏讀背面之注意事項再填寫本頁) 訂 -15- 412862 *ί·ϊ&‘部中决梂ί?·局月工消於合作社印 A7 B7_五、發明说明（13 ) (2 8 )、本發明之半導體積體電路裝置之製造方法 ，更具有在上述第3導體層與上述第4絕緣層之間形成第 6絕緣，而在上述第4絕緣膜與上述第4導體膜之間形 成第7絕緣膜的過程。 發明之實施形態 以下請參照圖面詳細地說明本發明的實施形態。此外 ，所有說明實施形態的圖，對於具有相同功能的構件則附 加相同的符號，且省略其反覆的說明* (實施形態） 第1圖係形成本實施形態之DRAM的半導體晶片的 整體平面圖。如圖所示，在由單晶矽所形成的半導體晶片 1 A的主面上·則沿著X方向（半導體晶片1 A的長邊方 向）以及Y方向（半導體晶片1A的短邊方向），將多個 記憶體陣列MA R Y配置成矩陣狀。在沿著X方向彼此相 鄰之記憶體陣列MA R Y之間則配置有作爲周邊電路的感 測放大器S A。在半導體晶片1 A之主面的中央部則配置 有作爲周邊電路的字元驅動器WD，資料線選擇電路等的 控制電路，以及输出入電路，接合墊（bpuding pad )等。 第2圖係表上述DRAM的等效電路圖。如圖所示， 該DRAM的記億體陣列（MARY)係由被配置成矩陣 狀的多個字元線WL (WLn — 1，WLn，WLn + l ……）與多個位元線以及被配置在該些之交點的多個記憶 s . (請先聞讀背面之注意Ϋ項再填本頁) 訂 .* 本紙张尺度適中固S家標率《CNS ) Λ4規格（210X297公t > -16- 412862 A7 B7 五、發明説明（14 ) 格（MC )所構成。用於記憶1位元的資料的1個記憶格 係由1個資料儲存用電容元件c與被串聯在此的1個記憶 格選擇lill SFETQs所構成。記億格選擇用 Μ I S F ETQ s的源極，汲極的其中一個在電氣上與資 料儲存用電容元件C連接，而另一個在電氣上則與位元線 B L連接。字元線WL的一端則被連接到作爲周邊電路的 字元驅動器WD，而位元線BL的一端則被連接到作爲周 邊電路的感測放大器S Α。 接著請參照第3圖〜第4 4圖，依據過程的順序來說 明如上所構成之DRAM之製造方法的一例。 首先，如第3圖所示*對ρ型，且電阻率爲1 0Ω cm左右的半導體基板1，在8 5 °C左右下實施濕氧化， 在形成膜厚薄到1 0 nm左右的氧化矽膜2後，藉由 C V D ( Chemical Vapor Deposition )法，在該氧化政膜 2 的上部堆積膜厚約1 4 0 nm的氮化矽膜3。氧化矽膜2 則是爲了要緩和在以後的過程當針對被埋入在元件分離溝 之內部的氧化矽膜實施燒結時等加諸在基數上的應力而被 形成。由於氮化矽膜3具有難以被氧化的性質•因此可以 當作防止位於其下部（活性領域）之基板表面發生氧化的 掩罩來使用。 \ 接著，如第4圖所示•以光阻膜4作爲掩罩*對氮化 矽膜3，氧化矽膜2以及半導體基板1實施乾蝕刻，藉此 ，在元件分離領域的半導體基板1形成深度約3 0 0 -400 n m左右的溝5a ·在形成溝5.a時，則以光阻膜 ·，f t 本紙张尺度进州中因园家標守（f’NSM4坑格（210Χ297公釐） (锖先Μ讀背面之注項存填邦本頁) 訂 -i<r_ · -17- A7 B7 412862 五、發明说明（15 ) 先 閲 讀 背 面 之 注 意 事 項 再 填 % 本 頁 4作爲掩罩，對氮化矽膜3實施乾蝕刻，接著在除去光阻 膜4後，以氮化矽膜3作爲掩罩，而對氧化矽膜2以及半 導體基實施乾蝕刻。 接著，在除去光阻膜4後，如第5圖所示，爲了要除 去因爲上述蝕刻而在溝5 a的內壁所發生的損傷層，乃使 半導體基板，在8 5 0〜9 0 0 °C左右下實施濕氧化，而 在溝5 a的內壁形成膜厚薄到1 〇 〇 nm左右的氧化矽膜 6 〇 訂 接著•如第6圖所示，當在半導體基板1上堆積膜厚 爲3 0 0 0〜4 0 t^nm左右的氧化矽膜7後，藉著使半 導體基板1在1 0 0 0°C左右下實施乾氧化，而進行使被 埋入在溝5 a之氧化矽膜7的膜質獲得改善的燒結處理。 氧化矽膜7則是藉由例如以臭氧（0 3 )與T E 0 S作爲來 源氣體的熱C V D法而堆積。 MM部中央樣聿扃U3:J.消費合作社印裝 接著•如第7圖所示，當在氧化矽膜7的上部，藉由 CVD法堆積膜厚約1 4 0 nm左右的氮化矽膜8後，如 第8圖所示，以光阻膜9作爲掩罩，對氮化矽膜8實施乾 蝕刻，藉此|氮化矽膜8只會殘留在如在記憶體陣列與周 邊電路領域之邊界部般之面積相對較寬的溝5 a的上部。 殘留在溝5 a之上部的氮化矽膜8，則_爲了要防止在接 下來的過程，藉由CMP法而化學地且機械地使氧化矽膜 7變爲平坦之際，面積相對較寬之溝5 a的內部的氧化矽 膜7會較面積相對較窄之溝5 a的內部的氧化矽膜7被硏 磨較深的現象而被形。以下，所謂的CJyiP法係指利用包 本紙张尺度適用中國囷家標隼（ΓΝ5)Λ4現格（210X297公釐） -18- 412862 A7 _B7_____五、發明説明（16 ) 含二氧化矽的藥液，而化學地且機械地對晶圓實施硏磨的 方法。 接#，在除去光阻膜9後，如第9圖所示，藉由以氮 化矽膜3，8作爲阻止膜的CMP法對氧化矽膜7實施硏 磨，而殘留在溝5 a的內部，藉此而形成元件分離溝5 * 接著，在藉由利用熱磷酸的濕蝕刻而除去氮化矽膜 3 . 8後，如第10圖所示，將η型雜質，例如P (磷） 的離子打入用於形成記憶格之領域（記億體陣列）的半導 體基板1上而形成η型半導體領域1 0，而將ρ型雜質， 例如Β (硼）的離子打入記憶體陣列與周邊電路領域的一 部分（形成η通道型Μ I SFET的領域）而形成ρ型阱 1 I ，將η型雜質，例如Ρ (磷）的離子打入周邊電路領 域的其他部份（形成Ρ通道型Μ I S F Ε； Τ的領域）而形 成η型阱1 2。又接著該注入離子，則將用於調整 MISFET之閱値電壓的雜質，例如BF2(氟化硼）的 離子打入P型阱1 1以及η型阱1 2。n型半導體領域 1 0則是爲了要防止雜訊（noise )自輸出入電路等經由半 導體基板1而侵入記億體陣列的P型阱1 1而被形成》 接著在使用H F (氟酸）系的淸洗液而除去ρ型阱 1 1以及η型阱1 2之各表面的氧化矽膜2後，則使半導 體基餐1在8 5 Ot左右下實施濕氧化，而在ρ型阱1 1 以及η型阱1 2的各表面形成膜厚7 nm左右之淸潔的閘 氧化膜1 3。 雖然未特別加以限定，但是在形成A述閘氧化膜1 3 本紙張尺度通用中國g家標_ ( CNS ) ( 2IOx297^t ) ~~ {婧先聞讀背面之注意事項再填寫本頁) -19· 41^863 A7 ____B7______ 五、發明说明（17〉" {銪先閲讀背面之注^#.項再填寫本頁) 後’也可以藉由使半導體基板1在NO (氧化氮）或1^2〇 (氧化亞氮）環境下食施熱處理，而使氮偏析於閘氧化膜 13與半導體基板1的界面（氧氮化處理），當閘氧化膜 1 3薄到7 nm左右時，因爲與半導體基板1的熱膨脹係 數差•會使得在兩者之界面所產生之應力變得顯著，而誘 導熱載子（hot carrier )的發生•但由於偏折於與半導體基 板1之界面的氮會使得該應力獲得緩和，因此上述氧氮化 處理可以提升該極薄之閘氧化膜1 3 信屬性。 行漭.V中次疗淖局貝工消费合作a印" 接著，如第1 1圖所示*在閘氧化膜1 3的上部形成 閘極1 4 A，1 4 B，1 4 C。閘極1 4 A則構成記憶格 選擇用Μ I S F E T的一部分，而在活性領域以外的領域 則當作字元線WL來使用，該閘極1 4Α (字元線WL) 的寬度，亦即，閘長度則是以在可以抑制記憶格選擇用 Μ I S F Ε Τ的短通道效果，而將閾値電壓確保在一定値 以上之容許範園內的最小尺寸（例如0 . 24#ιη)所構 成·又相鄰之閘極1 4A (字元線）彼此的間隔，則是以 由光石印之解析極限所決定之最小尺寸（例如0 . 2 2 只m)而構成。閘極1 4 B以及閘極1 4 C則構成周邊電 路之η通道型MI SFET以及p通道型MI SFET的 各自一部分* , 閘極14Α (字元線WL)以及閘極14Β，14C ，則是藉由C V D法在半導體基板1上堆積經摻雜有例如 Ρ (磷）等的η型雜質而膜厚約7 0 nm左右的多晶矽膜 ，接著則藉由噴濺法在其上部堆積膜厚岸5 0 n m左右的 本紙張尺度適用中國S家栋肀（) Λ4^ ( 2丨0X297公漦> -20- 經來部中次梂淖局ocJ.i/if合竹ii印褽 41^86^ B7 五、發明説明（18 ) WN膜與膜厚爲1 5〇 nm左右的W膜，更者當在其上部 藉由CVD法堆積膜厚爲1 5.0 nm左右的氮化矽膜1 5 後，以光阻膜1 6作爲掩罩，對該些膜實施圔案而形成。 WN膜則當作一用於防止在高溫熱處理時，W膜與多晶矽 膜會發生反應，而在兩者的界面形成髙電阻的金靥矽化物 厝的障壁層來使用*障壁餍，除了WN膜以外，也可以使 用T i N膜等。 當閘極1 4A (字元線WL)的一部分以低電阻的金 屬（W)而構成時，由於其面電阻可以減低到2〜2 . 5 Ω/□左右，因此可以減低字元線的延遲情形。又由於即 使閘極14 (字元線WL)不利用A1配線等來打底，也 可以減低字元線WL的延遲情形，因此被形成在記憶格之 上部的配線層的數目可以減少1層。 接著，在除去光阻膜1 6後，使用氟酸等的蝕刻液來 除去殘留在半導體基板1之表面的乾蝕刻殘渣或最光1且劑 殘渣。當進行該濕蝕刻時，在閘極14A(字元線WL) 以及閘極14B，14C之下部以外之領域的閘氧化膜 1 3被削去的同時，由於在閘極側壁下部的閘氧化膜1 3 也呈等方性地被蝕刻，而產生undercut，因此會導致閘氧 化膜1 3的耐壓能力降低。在此，藉著使半導體基板1在I (g) a process of forming a third conductive layer on the third insulating film t (h) a process of applying a fourth insulating film on the third conductive layer, and performing a second heat treatment on the fourth insulating film; (i) a process of forming a second opening in the fourth insulating film to expose a part of the third conductor layer; and (j) a process of forming a fourth conductor layer in the second opening; and the first heat treatment The temperature is higher than the second heat treatment temperature. (2 4). In the method for manufacturing a semiconductor integrated circuit device of the present invention, an aluminum layer is deposited on the third and fourth conductor layers. (2 5) In the method for manufacturing a semiconductor integrated circuit device of the present invention, between the above processes (d) and (e), there is (k) a process of washing the surface of the semiconductor substrate with the first opening with fluoric acid (2 6) The method for manufacturing a semiconductor integrated circuit device according to the present invention further includes a process of honing the second insulating film mechanically and chemically between the processes (c) and (d) β, (2 7) The method for manufacturing a semiconductor integrated circuit device of the present invention further includes (m) a fifth insulating film deposited on the second green insulating film between the processes (c) and (d), and The process of honing the above-mentioned 5th insulating film mechanically and chemically. The size of this paper is in Chinese standard (rNS M4 specification (2 丨 0X297mm) {read the precautions on the back before filling this page) Order-15- 412862 * ί · ϊ & ί? · Baoyue Industrial Co., Ltd. printed in the cooperative A7 B7_V. Description of the invention (13) (2 8), the method of manufacturing the semiconductor integrated circuit device of the present invention, further has the above-mentioned third conductor layer and the above-mentioned fourth insulation A process of forming a sixth insulation between the layers and forming a seventh insulation film between the fourth insulation film and the fourth conductor film. Embodiments of the Invention Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, for all diagrams illustrating the embodiment, the same reference numerals are attached to members having the same function, and repeated descriptions are omitted. (Embodiment) FIG. 1 is an overall plan view of a semiconductor wafer forming the DRAM of this embodiment. As shown in the figure, on the main surface of the semiconductor wafer 1 A formed of single crystal silicon, along the X direction (long side direction of the semiconductor wafer 1 A) and the Y direction (short side direction of the semiconductor wafer 1A), A plurality of memory arrays MA RY are arranged in a matrix. Between the memory arrays MARY adjacent to each other in the X direction, a sense amplifier SA is provided as a peripheral circuit. In the central portion of the main surface of the semiconductor wafer 1A, a control circuit such as a character driver WD, a data line selection circuit, and the like, an input / output circuit, a bpuding pad, and the like are arranged as peripheral circuits. Fig. 2 is an equivalent circuit diagram of the above-mentioned DRAM. As shown in the figure, the DRAM memory array (MARY) of the DRAM is composed of a plurality of word lines WL (WLn — 1, WLn, WLn + l, ...) and a plurality of bit lines and Multiple memories s arranged at the intersections of these. (Please read the notes on the back before filling this page) Order. * The paper size is moderate and the S standard is "CNS" Λ4 specification (210X297 male t > -16- 412862 A7 B7 V. Description of Invention (14) Cell (MC). A memory cell for storing 1-bit data consists of a data storage capacitor element c and a 1 connected in series here. Each memory cell is composed of lll SFETQs. The memory cell is selected to use the source of Μ ISF ETQ s. One of the drains is electrically connected to the capacitor C for data storage, and the other is electrically connected to the bit line. BL is connected. One end of the word line WL is connected to the word driver WD, which is a peripheral circuit, and one end of the bit line BL is connected to the sense amplifier S A, which is a peripheral circuit. Please refer to FIG. 3 ~ Fig. 44 illustrates an example of a method for manufacturing a DRAM constructed as described above according to the order of the processes. As shown in Fig. 3 * For a ρ-type semiconductor substrate 1 with a resistivity of about 10 Ω cm, wet oxidation is performed at about 8 5 ° C. After forming a silicon oxide film 2 with a film thickness of about 10 nm By CVD (Chemical Vapor Deposition) method, a silicon nitride film 3 with a thickness of about 140 nm is deposited on the oxide film 2. The silicon oxide film 2 is intended to ease the process in the future. The silicon oxide film buried inside the element separation trench is formed by applying stress on the base when sintering or the like. Since the silicon nitride film 3 has a property of being difficult to be oxidized, it can be used as a protection against the lower part (active Field) mask used for oxidation on the substrate surface. \ Next, as shown in Figure 4 • Using the photoresist film 4 as a mask * Dry-etching the silicon nitride film 3, the silicon oxide film 2 and the semiconductor substrate 1 Therefore, a groove 5a having a depth of about 300-400 nm is formed in the semiconductor substrate 1 in the field of element separation. When the groove 5.a is formed, a photoresist film is used. House standard guard (f'NSM4 pit grid (210 × 297 mm) (read the first Please fill in this page) Order -i < r_ · -17- A7 B7 412862 V. Description of the invention (15) Read the precautions on the back before filling in% This page 4 is used as a mask to dry the silicon nitride film 3 After etching, the photoresist film 4 is removed, and then the silicon nitride film 3 is used as a mask to dry-etch the silicon oxide film 2 and the semiconductor substrate. Next, after the photoresist film 4 is removed, as shown in FIG. 5 In order to remove the damage layer that occurred on the inner wall of the trench 5 a due to the above-mentioned etching, the semiconductor substrate was wet-oxidized at about 8 500 to 900 ° C, and the inner wall of the trench 5 a A silicon oxide film with a film thickness of about 100 nm is formed. As shown in FIG. 6, when a silicon oxide film with a film thickness of about 3 0 0 to 4 0 t ^ nm is deposited on the semiconductor substrate 1. After 7, a sintering process is performed to improve the film quality of the silicon oxide film 7 buried in the trench 5 a by performing dry oxidation at about 1000 ° C. on the semiconductor substrate 1. The silicon oxide film 7 is deposited by a thermal C V D method using, for example, ozone (0 3) and T E 0 S as source gases. Central sample of MM: U3: J. Printing by consumer cooperatives • As shown in Figure 7, when a silicon nitride film is deposited on the silicon oxide film 7 by a CVD method to a thickness of about 140 nm After 8, as shown in FIG. 8, the silicon nitride film 8 is dry-etched with the photoresist film 9 as a mask, whereby the silicon nitride film 8 will only remain in areas such as memory arrays and peripheral circuits. The upper part of the groove 5 a having a relatively wide area like a boundary portion. The silicon nitride film 8 remaining on the upper part of the trench 5 a is relatively wide in order to prevent the silicon oxide film 7 from being flattened chemically and mechanically by the CMP method in the following process. The silicon oxide film 7 inside the trench 5 a is relatively deeper than the silicon oxide film 7 inside the trench 5 a and is relatively shaped. In the following, the so-called CJyiP method refers to the application of Chinese paper standard (ΓΝ5) Λ4 (210X297 mm) in the standard of coated paper. -18- 412862 A7 _B7_____ V. Description of the invention (16) Medicine containing silicon dioxide Liquid and chemically and mechanically honing the wafer. After the photoresist film 9 is removed, as shown in FIG. 9, the silicon oxide film 7 is honed by the CMP method using the silicon nitride films 3 and 8 as a blocking film, and remains in the trench 5 a. Inside, an element separation trench 5 is formed by this. Next, after removing the silicon nitride film 3.8 by wet etching using hot phosphoric acid, as shown in FIG. 10, an n-type impurity such as P (phosphorus) is removed. Ions are inserted into the semiconductor substrate 1 used to form a memory cell (a memory array) to form an n-type semiconductor field 10, and ions of a p-type impurity such as B (boron) are injected into the memory array and Part of the peripheral circuit area (the area where the n-channel type M I SFET is formed) forms a p-type well 1 I, and ions of n-type impurities, such as P (phosphorus), are driven into other parts of the peripheral circuit area (the P-channel type is formed). M ISF E; T field) and n-type wells 12 are formed. Following the implanted ions, impurities for adjusting the read voltage of the MISFET, such as BF2 (boron fluoride) ions, are driven into the P-type well 11 and the n-type well 12. The n-type semiconductor field 10 is formed in order to prevent noise (noise) from entering and exiting the circuit through the semiconductor substrate 1 and penetrating into the P-type well 11 of the memory array. Next, HF (fluoric acid) systems are used. After the silicon oxide film 2 on each surface of the p-type well 11 and the n-type well 12 is removed by using a washing solution, the semiconductor substrate 1 is subjected to wet oxidation at about 8 5 Ot, and the p-type well 1 1 A clean gate oxide film 13 having a thickness of about 7 nm is formed on each surface of the n-type well 12. Although it is not particularly limited, the A-size gate oxide film is formed on the paper. The paper size is in accordance with the Chinese g standard _ (CNS) (2IOx297 ^ t) ~~ {Jing first read the precautions on the back before filling this page)- 19 · 41 ^ 863 A7 ____B7______ 5. Description of the invention (17> " {铕 Read the note on the back ^ #. And then fill out this page) after the 'can also be used to make the semiconductor substrate 1 in NO (nitrogen oxide) or 1 ^ 2〇 (nitrogen oxide) environment heat treatment, so that nitrogen segregation at the interface between the gate oxide film 13 and the semiconductor substrate 1 (oxynitriding process), when the gate oxide film 13 is thin to about 7 nm, because The difference in thermal expansion coefficient from the semiconductor substrate 1 will make the stress generated at the interface between them significant, and induce the occurrence of hot carriers. However, the nitrogen biased at the interface with the semiconductor substrate 1 will As a result, the stress is alleviated, so the above-mentioned oxynitriding treatment can improve the signal properties of the extremely thin gate oxide film 1 3. Line.V. Intermediate Therapeutic Bureau, Shellfish Consumer Cooperative Cooperation, India " Then, as shown in Figure 11 *, gates 1 4 A, 1 4 B, and 1 4 C are formed on the gate oxide film 13. The gate 1 4 A constitutes a part of the M ISFET for memory cell selection, and is used as a word line WL in areas other than the active area. The width of the gate 1 4A (word line WL), that is, The gate length is formed by the short channel effect that can suppress the selection of M ISF Ε Τ for memory cells, and the minimum size (such as 0. 24 # ιη) in which the threshold voltage is kept within a certain allowable range. The distance between the adjacent gates 1 4A (character lines) is formed by the minimum size (for example, 0.2 2 m) determined by the analytical limit of the light lithography. Gate 1 4 B and gate 1 4 C constitute respective parts of the η-channel type MI SFET and the p-channel type MI SFET of the peripheral circuit *, the gate 14A (word line WL) and the gates 14B, 14C are A polycrystalline silicon film doped with an n-type impurity such as P (phosphorus) and having a film thickness of about 70 nm is deposited on the semiconductor substrate 1 by a CVD method, and then a film thickness is deposited on the semiconductor substrate 1 by a sputtering method. This paper scale around 0 nm is suitable for Chinese Sjiadong 肀 () Λ4 ^ (2 丨 0X297 public 漦 > -20- Ministry of Economic Affairs, Ministry of Economy and Trade, ocJ.i / if 合 竹 ii 印 褽 41 ^ 86 ^ B7 V. Description of the invention (18) After the WN film and the W film having a thickness of about 150 nm, the silicon nitride film 15 having a thickness of about 1 5.0 nm is deposited on the upper part by a CVD method. The photoresist film 16 is used as a mask to form these films. The WN film is used to prevent the W film and the polycrystalline silicon film from reacting at the high temperature heat treatment, and is formed at the interface between the two. For the barrier layer of gold, silicide, and resistance, a barrier layer is used. In addition to a WN film, a T i N film can also be used. When the gate electrode is part of 4A (word line WL) When it is made of a low-resistance metal (W), its surface resistance can be reduced to about 2 to 2.5 Ω / □, so the delay of the word line can be reduced. Also, even though the gate 14 (word line WL) Without using A1 wiring or the like as a primer, the delay of the word line WL can also be reduced, so the number of wiring layers formed on the upper part of the memory cell can be reduced by one layer. Next, after removing the photoresist film 16, use An etching solution such as hydrofluoric acid is used to remove the dry etching residues or the most light residues remaining on the surface of the semiconductor substrate 1. When performing this wet etching, the gate electrode 14A (word line WL) and the gate electrodes 14B, 14C When the gate oxide film 1 3 in the area other than the lower part is cut off, the gate oxide film 1 3 in the lower part of the gate side wall is also etched isotropically, resulting in an undercut, which will cause the gate oxide film 1 3 The withstand voltage of the semiconductor substrate 1 is reduced.

V 9 0 0t左右下氧化，可以改善被削去之閘氧化膜之膜的 '-W. &quot; -— 一— 品質。 接著，如第12圖所示，將p型雜質，例如B(砸） 的離子注入到η型阱1 2，而在閘極c之兩側的η型 本紙張尺度適用中國囷家標肀（CNS ) Λ4*1格（210X297公釐） (請先閏讀背面之注意事項再填坑本頁) 訂 -21 - 杜浐部中次榡準局RJ·消资合作.批印繁 412863 J；五、發明説明（19 ) 阱12形成p_型半導體領域17。又，將η型雜質，例如 P (¼¾的離子注入Ρ型阱1 1，而在閘極1 4 Β之兩側 的P型阱1 1形成η —型半導體領域18，在閘極14A之 兩側的Ρ型阱1 1形成η型半導體領域1 9。藉此|在記 憶體陣列形成記憶格選擇用MI SFETQs。 接著，如第1 3圖所示，當藉由CMP法在半導體基 板1上堆積膜厚爲5 0〜1 0 0 nm左右的氮化矽膜2 0 後，如第1 4圖所示，以光阻膜2 1來覆蓋記億體陣列的 氮化矽膜20|藉由對周邊電路領域的氮化矽膜20實施 異方性蝕刻，在閘極14B，14C的側壁形成側壁間隔 層2 0 a。該蝕刻爲了要使被埋入到閘氧化膜1 3以及元 件分離溝5的氧化矽膜7的削去量達到最少•乃使用可以 使氮化矽膜2 0相對於氧化矽膜的蝕刻速率變大的蝕刻氣 體。又•爲了要使在閘極14B，14C上的氮化矽膜 1 5的削去量達到最少，必須要使過蝕刻（overetching ) 置侷限在最小限度* 接著在除去光阻膜2 1後，如第1 5圖所示，將ρ型 雜質，例如B (硼）的離子注入周邊電路領域的η型阱 1 2，而形成ρ通道型MI SFET之ρ+型半導體領域 22 (源極，汲極），將λ型雜質，例萍As (砷）的離 子注入到周邊電路領域的P型阱11，而形成η通道型 MISFET的η+型半導體領域2 3‘（源極，汲極），藉 此，在周邊電路領域形成Ρ通道型MISFETQp以及 η 通道型 Μ I S F E T Q η。 (对先閏請背面之注意事項再填寫本頁) 本紙張尺度適Λ中國囤家標枣（CNS M4規格（2IOX297公嫠） -22 - .¾¾-部中央榡if-局iaiJ-消贫合竹.杜印聚 412862 at __ 五、發明説明（2())&quot; 接著，如第1 6圓所示，在藉由旋轉被覆將膜厚爲 3 0 0 nm左右之爲液狀之絕緣物質的斧OG ( Spin On Glass )膜2 4塗佈在半導體基板1上後，使半導體基板1 在8 0 0 t下進行I分鐘的熱處寧，而對SOG膜24實 施燒結。通常的S 0G膜的熱處理，爲了要去除溶媒’乃 在4 0 0°C左右下進行*但是，在該過程中，爲了要改善 S 0 G膜的品質，乃在更高的溫享下進行。 第1 7圖係表S OG膜之濕蝕刻量與熱處理溫度之相 關性的說明圖•例如當著眼於利用氟酸/過氧化氫混合液 的6 0秒的濕蝕刻（□記號的圖形）時，可知當未實施熱 處理時（沒有退火），則會被蝕刻3 0 0 A，而成爲依電 漿CVD法而堆積之氧化矽膜（PTEOS) (30A左 右）的1 0倍，而藉由在8 0 0 °C下實施1分鐘的熱處理 ，蝕刻量會被減低到1 7 0 A左右。又即使是利用氟酸/ 氟化銨混合液（6 H F )來進行濕蝕刻時，藉由在8 0 0 °C下實施1分鐘的熱處理，可以得到同樣的效果。 又，由於SOG膜24的reflow性較BPSG膜爲高 ，而且微細的配線之間有優越的間隙塡充（gap fill )性， 因此，可以良好地埋入到被微細化到光石印之解析限度左 右爲止的閘極14A(字元線WL)彼此的間隙內。更者 ί ，由於SOG膜24，即使不實施對於BPSG膜而言爲 必要的高溫，長時間的熱處理|也可以得到高的軟化流動 (reflow )特性，因此可以抑制在記憶格選擇用 MI SFETQs之源極，汲極，或是在周邊電路之 s f _ 本紙張尺度通州中國囷家榇率《（，NS &gt; Λ4規格（2丨0X297公釐） (#先Μ讀背面之注意事項再填寫本頁) 訂 -23- 412862 A7 B7 五、發明説明（21 ) (婧先閱讀背面之注意事項再填寫本頁) MI SFET (η通道型MI SFETQn，p通道型 MI SFETQp)之源極，汲極中所包含之雜質的擴散 ，而達到滲接合的效果，且由於可以抑制構成閘極1 4A (字元線WL)以及閘極1 4B，1 4C的金屬（W膜） 在熱處理時發生氧化，因此可以提高構成DRAM之記憶 格以及周邊電路之Μ I S F E T的性能。 接著，如第1 8圇所示，當在S 0 G膜2 4的上部堆 積膜厚爲6 0 0 nm左右的氧化矽膜2 5後，藉由CMP 法對該氧化矽膜2 5實施硏磨，而使其表面變得平坦。氧 化矽膜2 5，則是根據例如利用臭氧（0 3 )與T E 0 S作 爲來源氣體的電漿CVD法而堆積。 如此般，本實施形態，即使是在剛在閘極1 4A (字 元線WL)以及閘極14B，14C的上部形成膜替：，&amp; 可以塗佈平坦性良好的S O G膜2 4，更者，則藉由 CMP法使堆稹在其上部的氧化矽膜2 5變得平坦。藉此 ，除了可以提升閘極14A(字元線WL)彼此之微細間 隙間的間隙塡充性外，也可以使閘極14A (字元線WL )以及閘極14B，14C之上部的絕緣膜變爲平坦。又 由於不實施高溫。長時間的熱處理，因此可以防止構成記 億格以及周邊電路之Μ I S F E T的特性發生惡化，而能 夠提髙性能。 接著，如第1 9圖所示，在氧化矽膜2 5的上部堆稹 膜厚爲1 0 0 nm左右的氧化矽膜2 6。該氧化矽膜2 6 則爲了要修補在藉由CMP法而硏磨時月f產生之上述氧化 ----^ r , 本紙張尺度通川中國S家橾卒（CNS ) Λ4%格（210X297公蘑） -24- 抒來·部中次梂ί?-&gt;ί9ΚΙίί消免合作社印裝 412862 A7 __ B7 _五、發明説明&amp; ) 矽膜2 5之表面之微細傷_痕而堆積•氧化矽膜2 6，則藉 由利用例如臭氧（〇3)與T E 0 S作爲來源氣體的電漿 CVD&amp;而堆積，在氧化矽膜2 5的上部，也可以取代上 述氧化矽膜2 6，而改堆積PSG ( Phospho Silicate Glass )膜等。 接著，如第2 0圖所示I藉由以光阻膜2 7作爲掩罩 的乾蝕刻來除去位在記億格選擇用MISFETQn之η 型半導體領域1 9 (源極，汲極）的上部的氧化矽膜2 6 ，2 5以及SOG膜》該蝕刻是在使氧化矽膜26，25 以及S 0 G膜2 4相對於氮化矽膜2 0的蝕刻速率變大的 條件下進行，而使得覆蓋η型半導體領域1 9或元件分離 溝5的上部的氧化矽膜2 0完全不會被除去。 接著，如第2 1圖所示，藉由以上述光阻膜2 7作爲 掩罩的乾蝕刻來除去位在記憶格選擇MISFETQn之 η型半導體領域1 9 (源極，汲極）的上部的氮化矽膜 1 5與閘氧化膜1 3，而在η型半導體領域1 9 (源極· 汲極）的其中一個的上部形成接觸孔2 8，而在另一個的 上部形成接觸孔29· 該蝕刻是在使氮化矽膜1 5相對於氧化矽膜（在閘氧 化膜1 3以及元件分離溝5內的氧化矽Ρ7 )的蝕刻速率 變大的條件下進行，而使得η型半導體領域1 9或是元件 分離溝5不會被切削太深。又該蝕刻是在使氮化矽膜15 呈異方性地被蝕刻的條件下進行•而使得氮化矽膜1 5殘 留在閘極1 4Α (字元線WL )的側壁_。藉此，具有直徑 本紙張尺度適用中圉國家揉枣（（：奶）厶^«^(2丨〇父297公釐了 . .-i IiTI—--- {#先閲婧背面之注意事項再填湾本頁) -25- 412862 at _B7_ 五、發明説明（23 ) (对先聞靖背面之注意事項再填鸿本頁) 微細到光石印之解析極限以下的接觸孔2 8，2 9，則相 對於閘極14A (字先線WL)呈自我整合地被形成。在 使接觸^128，29相對於閘極14A (字元線WL)呈 自我整合地形成時•也可以事先對氮化矽膜1 5實施異方 性蝕刻，而在閘極1 4A (字元線WL )的側壁形成側壁 間隔層。 接著在除去光阻膜2 7後，使用氟酸+氟化銨混合液 等的蝕刻液，來除去露出在接觸孔2 8，29之底部的基 板表面的乾蝕刻殘渣以及自然氧化膜等》此時，雖然露出 於接觸孔28，2 9之側壁的SOG膜24也被暴露在蝕 刻液中，但是如上所述，由於SOG膜藉__H8 0 0 °C左 右 &lt;的高溫下賁施燒結，可以減低相對於氟酸系的蝕刻液的 —- . 蝕刻速率，因此，接觸孔2 8，2 9的側壁不會因爲該濕 蝕刻處理被大幅地切削（undercut )。藉此，可以確實地 防止在接下來的過程中被埋入到接觸孔2 8，2 9之內部 的插塞（plug )彼此發生短路。 接著，如第22圖所示，在接觸孔28 · 29的內部 形成插塞30 ·該插塞30，係在藉由CVD法，在氧化 矽膜2 6的上部堆積路摻雜了 η型雜質（例如P (磷）） 的多晶矽膜後，藉由CMP法對該多晶尹膜進行硏磨’而 殘留在接觸孔28，2 9的內部而形成。 接著，如第2 3圖所示，當在氣也矽膜2 6的上部堆 積膜厚爲200nm左右的氧化矽膜31後，在800t 左右對半導體基板1實施熱處理。氧化#膜3 1則是藉由 本紙張尺度速中SS家標肀（rNS ) ( 2】0Χ297公釐） -26- 抒米部中吹桴-1'局兵工消资合作社印製 412862 at _B7___ 五、發明説明（24 )、 例如以臭氧（〇3)與TEO S作爲來源氣體的電漿CVD 法來堆積。又，藉由該熱處理，在構成插塞3 0之多晶矽 膜中的η型雜質，會自接觸孔28，29的底部擴散到記 億格選擇用MI SFETQs的η型半導體領域19 (源 極，汲極），而降低η型半導體領域19的電阻* 接著，如第2 4圖所示•藉由以光阻膜3 2作爲掩罩 的乾蝕刻，來除去位在上述接觸孔2 8之上部的氧化矽膜 3 1，而讓插塞30的表面露出。接著，在除去光阻膜 3 2後，如第2 5圖所示，藉由以光阻膜3 3作爲掩罩的 乾蝕刻，來除去周邊電路領域的氧化矽膜3 1，2 6， 25，SOG膜24以及閘氧化膜13，而在η通道型 MI SFETQn的η+型半導體領域23 (源極，汲極） 的上部形成接觸孔3 4，3 5，且在Ρ通道型 MI SFETQp的ρ+型半導體領域22 (源極，汲極 )的上部形成接觸孔36，37。 如上所述，藉由將除去記憶體陣列的氧化矽膜3 1， 而讓插塞露出的蝕刻以及在周邊電路領域形成接觸孔3 4 〜3 7的蝕刻以個別的過程來進行，可以防止在形成深的 接觸孔3 4〜3 7之際插塞3 0被切削。讓插塞3 0的表 面露出的蝕刻與形成接觸孔3 4〜3 7的蝕刻，也可以根 \ 據與上述相反的順序來進行。 接著，在除去光阻膜3 3後，與在第2 1圖所述者同 樣地，利用氟酸+氟化銨混合液來淸洗基板表面。SOG 膜2 4則是在高溫下被燒結，藉由該淸诜過程不會大幅地 本紙張尺度珀用中囷國家揉肀（CNS ) Λ4現格（210X297公釐） (請先閲讀背面之注^^項再填寫本頁) 訂 iA丨， -27- 412862 A7 B7 五、發明説明&amp; ) {銪先W讀背面之注意事項再填转本頁) 切削（undercut )。如第26圖所示’在氧化矽膜3 1的 上部形成位元線BL舆周邊電路的第1層配線3 8 ’ 3 9 。在形k位元線BL以及第1層配線38，39時，首先 ，藉由噴濺法，在氧化矽膜3 1的上部堆積膜厚爲5 0 nm左右的T i膜，而在8 0 0艺左右，對半導體基板1 實施熱處理*接著，則藉由噴濺法，在T i膜的上部堆積 膜厚爲5 0 nm左右的T i膜，更者，在藉由C VD法， 在其上部堆積膜厚爲1 5 0 nm左右的W膜與膜厚度爲 2 0 0 nm左右的氮化矽膜4 0後，以光阻膜4 1作爲掩 罩，對該些膜實施圖案》 當在氧化矽膜3 1的上部堆稹T i膜後，藉由在 8 0 OeC左右對半導體基板1實施熱處理，T i膜與S i 基板會發生反應，而在η通道型MISFETQn的n+型 半導體領域（源極，汲極）的表面與P通道型 MISFETQp的p+型半導體領域22 (源極，汲極） 的表面形成低電阻的T i S i 2層4 2。雖然未圖示，此時 ，也在被埋入到接觸孔2 8之插塞3 0的表面形成 T i S i 2層42。藉此，可以減低被連接到n+型半導 體領域2 3以及P +型半導體領域2 2的配線（位元線 BL，第1層配線38，39)的接觸電阻。又由於藉由 \ 將位元線B L設成由W膜/T i N膜/T i膜所構成，可 以使其面電阻減少到2 Ω/□以下，因此可以提高資料的 讀取速度以及寫入速度，且位元線B L與周邊電路之第1 層配線3 8，39可以在一個過程中同胯被形成。更者， % * _ 本紙張尺度通用中國围家榡率（CNS) A4規格（2丨0x297公着） -28- #fM部中次標準局兵^消^合作社印&quot; 412862 A? _B7五、發明説明&lt;26 ) 當將周邊電路之第1層配線（3 8，3 9 )由與位元線 B L同一層的配線而構成時，則與由形成在記憶格之上層 的A 1命線構成第1層配線的情形相比較，由於可以減低 用於連接周邊電路之MISFET(η通道型 MI SFETQn，ρ 通道型MI SFETQp)與第 1 層配線之接觸孔（3 4〜3 7 )的縱橫比（aspect )，而 提高第1層配線的連接信賴性· 位元線B L，爲了要儘可能地減低在與相鄰之位元線 B L之間所形成的寄生電容，而提高資料的讀取速度以及 寫入速度，乃將其間隔設成較其寬度爲長*位元線B L的 間隔例如爲0 . 24//m，而其寬度例如爲0 . 22//m 〇 接著，在除去光阻膜4 1後，如第2 7圖所示，在位 元線BL的側壁與第1層配線3 8，39的側壁則形成側 壁間隔層43。側壁間隔層43，在藉由CVD法，在位 元線BL以及第1層配線38，3 9的上部堆稹氮化矽膜 後，對該氮化矽膜實施異方性蝕刻而形成。 接著，如第2 8匾所示，藉由旋轉被覆，在位元線 BL以及第1層配線38，39的上部塗佈膜厚爲300 nm左右的SOG膜44。接著，在8p〇°C下|將半導 體基板1進行1分鐘左右的熱處理，而對SOG膜44實 施燒結，藉此，可以減低SOG膜44相對於氟酸系之蝕 刻液的蝕刻速度。 S 0_ G膜的reflow特性較B P S G辱爲高，而在微細 (請先閱讀背面之注意事項再填寫本頁) 訂 -! 本紙張尺度洎用中國囷家標準（CNS)A4規格（210X297公釐） -29-Oxidation at about V 9 0 0t can improve the '-W. &Quot; -—-quality of the film of the gate oxide film that has been cut off. Next, as shown in FIG. 12, ions of a p-type impurity, such as B (smash), are implanted into the n-type well 12 and the n-type paper dimensions on both sides of the gate c are in accordance with Chinese standard 囷 ( CNS) Λ4 * 1 grid (210X297 mm) (Please read the notes on the back before filling in this page) Order -21-RJ · Huawei Cooperation of the Ministry of Economy and Social Sciences, Ministry of Economic Affairs. 5. Description of the invention (19) The well 12 forms a p-type semiconductor field 17. In addition, n-type impurities, such as P (¼) ions, are implanted into the P-type well 1 1, and the P-type wells 1 1 on both sides of the gate 1 4 B form an n-type semiconductor field 18, and two of the gate 14A The P-type wells 11 on the side form the n-type semiconductor field 19. Thereby, the MI SFETQs for memory cell selection are formed in the memory array. Next, as shown in FIG. 13, when the CMP method is used on the semiconductor substrate 1 After depositing a silicon nitride film 20 having a film thickness of about 50 to 100 nm, as shown in FIG. 14, a silicon nitride film 20 of a billion-body array is covered with a photoresist film 21 | Anisotropic etching is performed on the silicon nitride film 20 in the peripheral circuit area, and sidewall spacers 20 a are formed on the sidewalls of the gates 14B and 14C. This etching is to be buried in the gate oxide film 13 and the element separation trench. The amount of silicon oxide film 7 removed is minimized. • An etching gas that can increase the etching rate of silicon nitride film 20 relative to the silicon oxide film is used. Also, in order to make the gate electrodes 14B and 14C The removal amount of the silicon nitride film 15 is minimized, and the overetching must be limited to a minimum. * After removing the photoresist film 21, such as As shown in FIG. 15, ions of a p-type impurity such as B (boron) are implanted into the n-type well 12 in the peripheral circuit field to form a p-channel type MI SFET in the p + -type semiconductor field 22 (source, drain). ), Implanting λ-type impurities, such as As (arsenic) ions, into the P-type well 11 in the peripheral circuit field to form the η + type semiconductor field 2 3 ′ (source, drain) of the η-channel MISFET. Therefore, P-channel MISFETQp and η-channel M ISFETQ η are formed in the field of peripheral circuits. (Please note on the back side before filling out this page) This paper is suitable for Chinese jujube standard (CNS M4 specification (2IOX297)嫠) -22-.¾¾- 部 中 榡 if- 局 iaiJ- 消 消 合 竹. 杜 印 聚 412862 at __ V. Description of the Invention (2 ()) &quot; Then, as shown in the 16th circle, borrowing After spin coating, an axe OG (Spin On Glass) film 2 of a liquid insulating material having a thickness of about 300 nm is coated on the semiconductor substrate 1, and then the semiconductor substrate 1 is processed at 800 t. The heat treatment is performed for one minute, and the SOG film 24 is sintered. In order to remove the solvent, the heat treatment of the conventional SOG film is performed at 400 °. C is performed at about C *. However, in this process, in order to improve the quality of the S 0 G film, it is performed at a higher temperature. Figure 17 shows the correlation between the wet etching amount of the SOG film and the heat treatment temperature. Explanatory diagram of properties • For example, when focusing on 60-second wet etching using a hydrofluoric acid / hydrogen peroxide mixed solution (the pattern of the mark □), it can be seen that when heat treatment is not performed (without annealing), it will be etched 30 0 A, which is 10 times the silicon oxide film (PTEOS) (about 30A) deposited by plasma CVD, and by performing heat treatment at 800 ° C for 1 minute, the amount of etching will be reduced to About 1 70 A. Even when wet etching is performed using a hydrofluoric acid / ammonium fluoride mixed solution (6 H F), the same effect can be obtained by performing a heat treatment at 800 ° C for 1 minute. In addition, the SOG film 24 has a higher reflow property than a BPSG film, and has excellent gap fill properties between fine wirings. Therefore, it can be buried well to the limit of fine-grained light lithography. The left and right gates 14A (word lines WL) are in a gap between each other. Furthermore, because of the SOG film 24, even if the high temperature necessary for the BPSG film is not applied, the heat treatment for a long time can obtain high softening flow (reflow) characteristics, so it is possible to suppress the use of MI SFETQs in the memory cell selection. Source, drain, or sf of the peripheral circuit _ This paper is scaled by Tongzhou China's home appliance rate "(, NS &gt; Λ4 specification (2 丨 0X297 mm) (# 先 ＭRead the precautions on the back before filling in this Page) Order-23- 412862 A7 B7 V. Description of the invention (21) (Jing first read the precautions on the back before filling out this page) MI SFET (η channel type MI SFETQn, p channel type MI SFETQp) source and drain The diffusion of the impurities contained in it achieves the effect of infiltration bonding, and because the metal (W film) constituting the gates 1 4A (word line WL) and the gates 1 4B, 1 4C is oxidized during heat treatment, Therefore, it is possible to improve the performance of the M ISFET constituting the memory cell of the DRAM and the peripheral circuits. Next, as shown in FIG. 18 (a), when a silicon oxide film having a thickness of about 600 nm is deposited on the upper part of the S 0 G film 24. After 25, the silicon oxide film 25 is honed by the CMP method. The surface is made flat. The silicon oxide film 25 is deposited by, for example, a plasma CVD method using ozone (0 3) and TE 0 S as source gases. As such, in this embodiment, Films are formed on the gates 1 4A (word lines WL) and gates 14B and 14C: &amp; The SOG film 2 4 with good flatness can be coated, and the stack is deposited by CMP method. The upper silicon oxide film 25 becomes flat. In this way, in addition to improving the gap between the fine gaps of the gate electrodes 14A (word line WL), the gate 14A (word line WL) can also be improved. ) And the gates 14B and 14C are flat. The insulation film is not high temperature. Long-term heat treatment can prevent deterioration of the characteristics of the M ISFETs that constitute the memory cells and peripheral circuits, and improve the performance. Next, as shown in FIG. 19, a silicon oxide film 26 having a film thickness of about 100 nm is stacked on the silicon oxide film 25. The silicon oxide film 2 6 is repaired by CMP in order to be repaired. The above-mentioned oxidation produced by the moon f when honed by law ---- ^ r (CNS) Λ4% grid (210X297 male mushrooms) -24- Shulai · Ministry of the Ministry of Justice 梂?-&Gt; ί9ΚΙίί Dispelled and exempted cooperatives printed 412862 A7 __ B7 _V. Description of the invention &) The surface of the silicon film 25 The fine flaws and scars are deposited. The silicon oxide film 26 is deposited by plasma CVD &amp; using, for example, ozone (〇3) and TE 0 S as source gases, and may be deposited on the silicon oxide film 25. Instead of the above silicon oxide film 26, a PSG (Phospho Silicate Glass) film or the like is deposited instead. Next, as shown in FIG. 20, the upper part of the n-type semiconductor region 19 (source, drain) located in the MOSFETQn for selection MISFETQn is removed by dry etching using a photoresist film 27 as a mask. The silicon oxide films 26, 25, and SOG film are etched under the condition that the etching rate of the silicon oxide films 26, 25 and the S 0 G film 2 4 is larger than that of the silicon nitride film 20, and This prevents the silicon oxide film 20 covering the n-type semiconductor region 19 or the upper part of the element separation trench 5 from being completely removed. Next, as shown in FIG. 21, the upper part of the n-type semiconductor region 19 (source, drain) located in the memory cell selection MISFETQn is removed by dry etching using the above-mentioned photoresist film 27 as a mask. A silicon nitride film 15 and a gate oxide film 13 are formed in the upper part of one of the n-type semiconductor fields 19 (source and drain), and a contact hole 28 is formed in the upper part of the other, and a contact hole 29 is formed in the upper part of the other. This etching is performed under the condition that the etching rate of the silicon nitride film 15 with respect to the silicon oxide film (the silicon oxide film P7 in the gate oxide film 13 and the element separation trench 5) is increased, thereby making the n-type semiconductor field 19 or the component separation groove 5 will not be cut too deep. This etching is performed under the condition that the silicon nitride film 15 is anisotropically etched so that the silicon nitride film 15 remains on the sidewall of the gate electrode 14A (word line WL). With this, the paper size with diameter of this paper is suitable for Chinese and Korean countries to rub jujube ((: milk) 厶 ^ «^ (2 丨 〇 Father 297 mm. .-I IiTI ——--- {# 先 读 NOTES on the back Refill this page) -25- 412862 at _B7_ V. Description of the Invention (23) (Notes on the back of Wenjing Jing and refill this page) Contact holes fine to the resolution limit of light lithography 2 8, 2 9 , It is formed in a self-integrated manner with respect to the gate electrode 14A (word line WL). When the contacts ^ 128, 29 are formed in a self-integrated manner with respect to the gate electrode 14A (word line WL). The siliconized film 15 is anisotropically etched, and a sidewall spacer is formed on the side wall of the gate electrode 14A (word line WL). Next, after removing the photoresist film 27, a mixed solution of hydrofluoric acid + ammonium fluoride is used. To remove dry etching residues and natural oxide films on the substrate surface exposed on the bottom of the contact holes 28, 29. At this time, although the SOG film 24 exposed on the sidewalls of the contact holes 28, 29 is also exposed. In the etching solution, as described above, since the SOG film is sintered at a high temperature of about __H8 0 0 ° C <lt; The etching rate of the acid-based etching solution. Therefore, the sidewalls of the contact holes 28, 29 will not be undercut because of this wet etching process. This can reliably prevent the next process. The plugs embedded in the contact holes 28, 29 are short-circuited with each other. Then, as shown in FIG. 22, a plug 30 is formed inside the contact hole 28. 29. The plug 30 After the polycrystalline silicon film doped with n-type impurities (such as P (phosphorus)) is deposited on the upper part of the silicon oxide film 26 by CVD, the polycrystalline silicon film is honed by the CMP method. It remains inside the contact holes 28, 29. Next, as shown in FIG. 23, when the silicon oxide film 31 having a film thickness of about 200 nm is deposited on the top of the silicon film 26, it is about 800t. The semiconductor substrate 1 is subjected to heat treatment. The oxide #film 3 1 is based on the SS family standard (rNS) (2) 0 × 297 mm in this paper scale. Printed by a cooperative 412862 at _B7___ V. Description of the invention (24), for example, plasma using ozone (〇3) and TEO S as source gases The CVD method is used to deposit the η-type impurities in the polycrystalline silicon film constituting the plug 30 by this heat treatment, and diffuse from the bottoms of the contact holes 28 and 29 to the η-type semiconductor field of the MI SFETQs for selection. 19 (source, drain), and reduce the resistance of the n-type semiconductor field 19 * Next, as shown in FIG. 24 • Dry contact with the photoresist film 32 as a mask to remove the above-mentioned contact The silicon oxide film 31 on the upper part of the hole 2 8 exposes the surface of the plug 30. Next, after removing the photoresist film 32, as shown in FIG. 25, the silicon oxide film 3 in the peripheral circuit area is removed by dry etching using the photoresist film 3 3 as a mask, as shown in FIG. 25. The SOG film 24 and the gate oxide film 13 form contact holes 3 4, 3 5 in the upper part of the n + -type semiconductor region 23 (source, drain) of the n-channel type MI SFETQn. Contact holes 36 and 37 are formed in the upper part of the p + -type semiconductor region 22 (source, drain). As described above, by removing the silicon oxide film 31 of the memory array, the etching for exposing the plug and the etching for forming the contact holes 3 4 to 37 in the peripheral circuit area are performed in separate processes, which can prevent the When deep contact holes 3 4 to 37 are formed, the plug 30 is cut. The etching for exposing the surface of the plug 30 and the etching for forming the contact holes 3 4 to 37 may be performed in the reverse order to the above. Next, after removing the photoresist film 33, the surface of the substrate was washed with a mixed solution of hydrofluoric acid + ammonium fluoride in the same manner as described in FIG. 21. The SOG film 2 4 is sintered at high temperature. This process will not greatly increase the size of the paper. CNS Λ4 grid (210X297 mm) (please read the note on the back first) ^^ item and then fill out this page) Order iA 丨, -27- 412862 A7 B7 V. Description of the invention &) {铕 Read the precautions on the back before filling in this page) Undercut. As shown in FIG. 26, 'the bit line BL and the first layer wiring 3 8' of the peripheral circuit are formed on the silicon oxide film 31. When the k-bit line BL and the first-layer wirings 38 and 39 are formed, first, a Ti film having a film thickness of about 50 nm is deposited on the upper portion of the silicon oxide film 31 by a sputtering method, and at 80 ° The semiconductor substrate 1 is subjected to heat treatment at about 0 ° *. Then, a Ti film having a thickness of about 50 nm is deposited on the upper portion of the Ti film by a sputtering method. Furthermore, the C VD method is used in A W film having a film thickness of about 150 nm and a silicon nitride film 40 having a film thickness of about 200 nm are deposited on the upper part, and a photoresist film 41 is used as a mask to pattern these films. After the Ti film is stacked on the silicon oxide film 31, the semiconductor substrate 1 is heat-treated at about 80 OeC. The Ti film and the Si substrate react, and the n + type semiconductor of the n-channel type MISFETQn The surface of the field (source, drain) and the surface of the p + -type semiconductor region 22 (source, drain) of the P-channel type MISFETQp form a low-resistance Ti 2 layer 4 2. Although not shown, a T i S i 2 layer 42 is also formed on the surface of the plug 30 buried in the contact hole 28 at this time. This can reduce the contact resistance of the wirings (bit lines BL, first layer wirings 38, 39) connected to the n + semiconductor region 23 and the P + semiconductor region 22. Also, by setting the bit line BL to be composed of W film / T i N film / T i film, the sheet resistance can be reduced to less than 2 Ω / □, so the data reading speed and writing can be improved. At the same time, the bit line BL and the first layer wirings 38 and 39 of the peripheral circuit can be formed in the same process. In addition,% * _ This paper size is in accordance with China's standard for household furniture (CNS) A4 specification (2 丨 0x297) -28- #fM Ministry of Standards and Technology Bureau ^ ^ ^ cooperative cooperative seal &quot; 412862 A? _B7 five 2. Description of the invention &lt; 26) When the first layer of wiring (3, 38, 9) of the peripheral circuit is composed of the wiring of the same layer as the bit line BL, it is the same as the A1 formed on the layer above the memory cell. Compared with the case where the wires constitute the first-layer wiring, the contact holes of the MISFET (η-channel type MI SFETQn, ρ-channel type MI SFETQp) for connecting to the peripheral circuit and the first-layer wiring (3 4 to 37) can be reduced. The aspect ratio improves the reliability of the connection of the first layer wiring. The bit line BL, in order to reduce the parasitic capacitance formed between the adjacent bit line BL as much as possible, and improve the reading of data. The fetching speed and the writing speed are set to have a longer interval than the width * The interval of the bit line BL is, for example, 0.24 // m, and the width is, for example, 0.22 // m 〇 Then, remove After the photoresist film 41, as shown in FIG. 27, a sidewall spacer is formed on the sidewall of the bit line BL and the sidewall of the first layer wiring 38, 39. 43. The sidewall spacer layer 43 is formed by stacking a silicon nitride film on the bit lines BL and the first layer wirings 38 and 39 by a CVD method, and then anisotropically etching the silicon nitride film. Next, as shown in the 28th plaque, an SOG film 44 having a film thickness of about 300 nm is applied to the upper portions of the bit lines BL and the first layer wirings 38 and 39 by rotating coating. Next, the semiconductor substrate 1 is heat-treated at 8 p ° C for about 1 minute, and the SOG film 44 is sintered, thereby reducing the etching rate of the SOG film 44 with respect to the fluoric acid-based etching solution. The reflow characteristic of S 0_ G film is higher than that of BPSG, and it is subtle (please read the precautions on the back before filling this page). Order-! This paper size adopts China National Standard (CNS) A4 specification (210X297 mm) ) -29-

好浼部中央榡準局P工消於合作社印W 412862 A7 B7 五、發明説明（27 ) 的配線之間具有優秀的間隙塡充特性，因此•可以良好地 埋入到被微細化到光右印之解析極限左右爲止之位元線 BL彼k的間隙內。又，SOG膜44，由於即使不進行 對B P S G膜爲必要之高溫，長時間的熱處理，也可以得 到高的軟化流動（reflow )特性，因此可以抑制在形成於 位元線BL之下層之記億格選擇用MISFETQs之源 極，汲極或是周邊電路之MISFET(η通道型 MI SFETQn，ρ 通道型MI SFETQp)之源極 *汲極中所包含之雜質的熱擴散，而可以達到淺接合的效 果•更者，由於可以抑制構成閘極1 4A (字元線WL) 以及閘極14B，14C之金屬（W膜）的氧化，因此可 以提高構成D R A Μ之記憶格以及周邊電路之 MI SFET的性能。又，可以抑制構成位元線BL以及 第1層配線38，39之Ti膜，TiN膜的氧化，而能 夠減少配線電阻》 接著，如第2 9圖所示，當在SOG膜4 4的上部堆 積膜厚爲6 0 0 nm左右的氧化矽膜4 5後，.藉由CMP 法對該氧化矽膜4 5實施硏磨，而使其表面變爲平坦。氧 化矽膜4 5，則是藉由以例如臭氧（〇3)與TEOS作爲 來源氣體的電漿CVD法來堆稹。 t 如此般，本實施形態，在位元線B L以及第1層配線 3 8 * 3 9的上部，即使在剛形成膜後，也可以旋轉塗佈 平坦性良好的SOG膜44，更者，則藉由CMP法，使 •堆積在其_上部的氧化矽膜4 5變爲平坦藉此，除了可以 本紙張尺度適用中囷园家標率（CNS &gt; A4規格（2丨0X297公釐） -----------:·------ir------% - (锖先聞讀背面之注意事項再填寫本頁) -30 - 4128.62 A7 __B7 五、發明説明（28 ) (妍先閱讀背面之注意事項再填寫本頁) 提高在位元線B L彼此之間隙的間隙塡充特性外，也可以 使位在位元線BL以友第1層配線38，3 9之上部的絕 緣膜變k平坦》又由於不實施高溫，長時間的熱處理，因 此可以防止構成記億格以及周邊電路的Μ I S F E T的特 性惡化，而得以提高性能，此外，也可以降低位元線B L 以及第1層配線38，39的電阻。 接著，如第3 0圖所示，在氧化矽膜4 5的上部堆積 膜厚爲lOOnm左右的氧化矽膜46。該氧化矽膜46 則是爲了要修補在被CMP法硏磨時在上述氧化矽膜4 5 的表面所發生之微細的傷痕而堆積。氧化矽膜4 6則是利 用例如以臭氧（〇3)與TEOS作爲來源氣體的電漿 C V D法而堆積* 接著，如第3 1圖所示*藉由以光阻膜4 7作爲掩罩 的乾蝕刻，而除去位在接觸孔2 9之上部的氧化矽膜4 6 ，45以及SOG膜44以及氧化矽膜3 1，遂形成到達 插塞3 0之表面的通孔4 8。該蝕刻則是在使氮化矽膜相 對於氧化矽膜46，5 1，3 1以及SOG膜44的蝕刻 速度變小的條件下而進行，即使通孔4 8與位元線B L的 對合發生偏差，也可以使位在位元線B L之上部的氮化矽 膜4 0以及側壁間隔層4 3不會被切削$深《藉此，通孔 4 8可以相對於位元線B L呈自我整合地形成》 接著在除去光阻膜4 7後，使用氟酸+氟化銨混合液 等的蝕刻液，來除去露出在通孔4 8之底部之插塞3 0之 表面的乾蝕刻殘渣以及自然氧化膜等。此時，雖然露出在 *- * , 本紙乐尺度適用中圉园家揉率（CNS ) Λ4規格（2丨0X297公釐） -31 - 时湞部中央枒卑局β工消於合作社印裝 412862 at B7 五、發明説明（29 ) 1 ' 通孔4 8之側壁的SOG膜4 4也暴露於蝕刻液中，但是 如上所述，由於SOG膜44，藉由在800 °C左右的高 溫下實施燒結，可以減低相對於氟酸系之蝕刻液的蝕刻速 率，因此，通孔4 8的側壁不會因爲該濕蝕刻處理而被大 幅地切削（undercut )。藉此，可以確實地防止在接下來 的過程中被埋入到通孔4 8之內部的插塞彼此發生短路。 又，由於使插塞與位元線B L充分地離開，因此可以抑制 位元線B L之寄生電容的增加情形。 接著，·如第3 2圖所示，在通孔4 8的內部形成插塞 4 9 »插塞4 9是藉由在氧化矽膜4 6的上部，藉由 CVD法堆積經摻雜了η型雜質（例如P (磷）的多晶矽 膜後，對該多晶矽膜實施平坦蝕刻（ethch back )法而殘留 在通孔4 8的內部而形成》 接著，如第3 3圖所示，當在氧化矽膜4 6的上部， 藉由CVD法堆積膜厚約爲1 0 0 nm左右的氮化矽膜 5 1後，藉由以光阻膜5 2作爲掩罩的乾蝕刻，來除去周 邊電路領域的氮化矽膜5 1。殘留在記憶體陣列的氮化矽 膜5 1，則在形成後述之資料儲存用電容元件之下部電極 的過程中，當對位在下部電極之間的氧化矽膜進行蝕刻時 當作阻止蝕刻膜來使用。 、 接著，在除去光阻膜5 2後，如第3 4圖所示，在氮 化矽膜5 1的上部堆積膜厚爲1 · 4 //m左右的氧化矽膜 5 3，藉由以光阻膜5 4作爲掩罩的乾蝕刻，來除去氧化 矽膜5 3以及氮化矽膜5 1，藉此在通孔4 8的上部形成 ^ 1 * 本紙張尺度適/0中國g家標準（CNS ) A4规# ( 2丨0X297公釐) ^ -32 - · — ) 11 —---訂丨----ίΑ丨 (请先閱讀背面之注^►項再填寫本頁) 妗浸部中次枒準局β-τ-消於合竹社印紫 412862 五、發明説明（) 30 溝5 5 *在此同時，則在記憶體陣列的周圍形成包圍記億 體陣列之框狀的溝5 5 a ·氧化矽膜5 3，則藉由例如以 臭氧（〇3)與TEOS作爲來源氣體的電漿CVD法而堆 稹。 接著，在除去光阻膜5 4後，如第3 5圖所示，藉由 CVD法，在氧化矽膜5 3的上部堆積經摻雜了 η型雜質 (例如Ρ (磷））之膜厚爲6 0 nm左右的多晶矽膜5 6 。該多晶矽膜5 6則當作資什儲存用電容元件之下部電極 材料來使甩。 接著，如第3 6圖所示，藉由旋轉塗覆法，在多晶矽 膜56的上部塗佈膜厚足以埋入溝55，55a (例如 300〜400nm左右）的SOG膜57，接著爲了使 溶媒揮發·在藉由4 0 0 °C左右的熱處理對S OG膜5 7 實施烘焙後，如第3 7圔所示，對SOG膜5 7實施平坦 蝕刻（etch back )，更者藉著對位在氧化矽膜53之上部 的多晶矽膜5 6實施平坦蝕刻，可以使多晶矽膜5 6殘留 在溝55，55a的內部· 接著，如第3 8圖所示，以光阻膜5 8來覆蓋周邊電 路領域的氧化矽膜5 3，藉由濕蝕刻除去位在溝5 5之內 部的SOG膜5 7與溝5 5之間隙的氧化矽膜5 3，而形 成資料儲存電容元件的下部電極6 0。此時’由於在溝 5 5的間隙殘留下氮化矽膜5 1，因ifc，該間隙的氧化政 膜4 6不會被蝕刻》又，覆蓋周邊電路領域之氧化矽膜 5 3的光阻膜5 8的一端，則被配置在莽形成於記億體陣 本紙張尺度通用中國园家標率（CNS)A4現格（2I0X297公釐） ------；----------^------峡-. (請先W讀背面之注f項再填巧本頁) -33- 蚜承部中央榡卑局兵Η消於合作ίι印裝 412862 at _B7 五、發明説明) οι 列之最外側的下部電極6 0與周邊電路領域的邊界部，亦 即，溝5 5 a的上部於是，即使光阻膜5 8發生對位偏 差，由於其端部不會位在形成於記憶體陣列之最外側的下 部電極6 0上，因此，SOG膜5 3不會殘留在該下部電 極6 0之溝5 5的內部，或是氧化矽膜5 3不會殘留在該 下部電極6 0與溝5 5 a的間隙。又，由於周邊電路領域 之氧化矽膜5 3的一部分也不會暴露於蝕刻液，因此，周 邊電路領域之氧化矽膜5 3的一部分不會被切削成爲深溝 〇 * 接著，除去光阻膜5 8 |又爲了要防止構成下部電極 6 0的多晶矽膜（5 6 )發生氧化，乃使半導體基板1置 於氨環境中，以8 0 0 °C左右進行熱處理，在使多晶矽膜 5 6的表面氮化後，如第3 9圖所示，藉由CVD法，在 下部電極6 0的上部堆積膜厚爲2 0 nm左右的T a 2〇5 (氧化鉅）膜6 1，接著，使半導體基板1在80 0 eC左 右下進行熱處理*而修復Ta2〇5膜6 1的缺陷。該 T a 2〇5膜6 1乃當作資料儲存用電容元件的電容絕緣膜 材料來使用= 接著，如第4 0圖所示，在藉由CVD法與噴濺法， 在Ta2〇s膜6 1的上部堆積膜厚爲1 5〇nm左右的 T i N膜6 2後，藉由以光阻膜6 3作爲掩罩的乾蝕刻· 對丁 i N膜6 2以及Ta2〇5膜6 1實施圖案，而形成以 由T i N膜6 2所形成的上部電極，由732〇5膜6 1所 形成的電容絕緣膜，以及由多晶矽膜5.6所形成的下部電 本纸張尺度通用中國g家標準（CNS ) Λ4現格（2丨0X297公釐） ----：丨_„-----------1T--------成- (請先閲婧背面之注意Ϋ项再填寫本頁) -34- 412862 a? B7 五、發明说明（32 ) 極6 0所構成的資料儲存用電容元件C。藉此，而完成由 記億格選擇用Μ I S f E TQ s與串聯於此之資料儲存用 電容元#C所構成的DRAM的記憶格》 接著，在除去光阻膜6 3後，如第4 1圖所示，在資 料儲存用電容元件C的上部堆積膜厚爲1 0 0 nm左右的 氧化矽膜6 4。氧化矽膜6 5，則是藉由以例如臭氧（〇3 )與TEOS作爲來源氣體的電漿CVD法而堆稹•接著 •藉由以光阻膜6 5作爲掩罩的乾蝕刻，藉著除去位在周 邊電路之第1層配線38之上部的氣化矽膜64，53， 46，45，SOG膜44以及氮化矽膜40而形成通孔 6 6 β 接著，在除去光阻膜6 5後，如第4 2圖所示，在通 孔6 6的內部形成插塞6 7，接著則在氧化矽膜6 4的上 部形成第2層配線68，69。插塞67，則是藉由噴濺 法，在氧化p膜6 4的上部堆積膜厚爲1 0 0 n m左右的 T i N膜，更者，當在其上部，藉由CVD法堆積膜厚爲 5 0 0 nm左右的W膜後，對該些膜實施平坦蝕刻*而藉 由殘留在通孔66的內部來形成。第2層配線68，69 ，則是當藉由噴濺法，在氧化矽膜6 4的上部形成膜厚爲 5 0 nm左右的T i N膜，膜厚爲6 0、nm左右的A 1膜 ，膜厚爲5 0 nm的T i膜後，藉由以光阻膜作爲掩罩的 乾蝕刻，對該些膜實施圖案而形成。 接著•如第43圖所示*在第2層配線68 * 69的 上部堆積層間絕緣膜。層間絕緣膜由例如.膜厚爲3 0 0 本紙張尺度適州中Βϋ家標率（CNS } A4il格（210X297公釐） (諳先聞讀背面之注意事項再填湾本頁 訂 好漭部中决榡淖局另η消费合作社印製 -35- 412862 A7 _B7 五、發明説明（33 )。 {讀先聞讀背面之注意事項再填巧本頁) nm左右的氣化矽膜7 1，膜厚爲4 0 0 nm左右的 SOG膜72，以及膜厚爲300nm左右的氧化矽膜 7 3所^成。氧化矽膜7 1，7 3則藉由例如以臭氧（0 3 )與TEOS作爲來源氣體的電漿CVD法而堆積。又， 對SOG膜7 2所實施的烘焙，爲了要防止以A 1膜爲主 體之第2層配線68，69發生惡化，乃在400 °C左右 的溫度下進行。又烘焙的目的在於使溶媒揮發。因此*烘 焙的溫度會較對於S OG膜2 4以及4 4的烘焙溫度爲高 氟 〇 接著，如果4 4圖所示，在位於資料儲存用電容元件 C之上部的層間絕緣膜形成通孔7 4，當在位於周邊電路 之第2層配線6 9之上部形成通孔7 5後，在通孔74 * 7 5的內部形成插塞7 6 -接著則在層間絕緣膜的上部形 成第3層配線77，78，79。通孔74，75則是藉 由以光阻膜作爲掩罩的乾蝕刻，來除去氧化矽膜7 3， SOG膜72，以及氧化矽膜64而形成。在此，由於未 利用氟酸+氟化銨混合液來淸洗，因此不需要對SOG膜 實施高溫熱處理。 之後，雖然在第3層配線7 7〜7 9的上部堆積由氧 化矽膜與氮化矽膜所構成的鈍化膜，但是省略其圖示。藉 \ 由以上的過程大致完成本實施形態的D R AM。 (賁施形態3 ) 請參照第4 5圖〜第4 8圖來說明本實施形態之 本紙張尺度適用中國g家榇準（（，NS &gt;厶4洗格（2丨0X297公釐） -36- 412862 a? _____B7 五、發明説明k ) D R A Μ的製造方法。 {讀先閱讀背面之注意事項再填寫本頁) '首先，如第4 5圖所示，在形成有記憶格選擇用 MI skETQs以及周邊電路之η通道型 MI SFETQn，ρ通道型MI SFETQp的半導體 基板1上，藉由旋轉塗覆塗佈膜厚爲3 0 0 nm左右的 SOG膜24，接著，則使半導體基板1 *在800乞下 進行1分鐘的熱處理，在對s 0G膜2 4實施燒結後，在 S 0G膜2 4的上部堆積膜厚爲6 0 0 nm左右的氧化矽 膜2 5。到此爲止的過程，則與上述實施形態1的過程（ 第3圖〜第18圖相同）* 在上述實施形態1中，雖然接下來以CMP法對氧化 矽膜2 5實施硏磨，但是在本實施形態中，如第4 6圖所 示，在對氧化矽膜2 5實施硏磨後，更者連對其下層的 S 0G膜2 4也實施硏磨《該硏磨|則是利用覆蓋記億格 選擇用MI SFETQs的氧化矽膜20當作阻止膜來使 用，當其表面露出時停止硏磨。 接著，如第4 7圖所示*當在氧化矽膜2 5的上部堆 積膜厚爲1 0 0 nm左右的氧化矽膜2 6後|如第48圖 所示，藉由以光阻膜2 7作爲掩罩的乾蝕刻，來除去位在 記憶格選擇用MISFETQs之η型尹導體領域19( 源極，汲極）之上部的氧化矽膜2 6以及SOG膜24， 接著則除去氮化矽膜1 5與閘氧化膜13，藉此，在η型 半導體領域1 9 (源極，汲極）之其中一個的上部形成接 觸孔2 8 ,而在另一個性上部形成接觸孔2 9 ·以後的過 s f 本紙張尺度適用中國K家標準（CNS)A4規格（210X297公釐） -37· 时滅部中决枒準局兵J消於合竹社印絮 412862 A7 __B7 _ 五、發明说明（35 ) 程則與上述實施形態1相同。 '根據本實施形態，由於可以使覆蓋記憶格選擇用 MI SFETQs以及周邊電路η通道型MI SFET， Ρ通道型MI SFE 丁的絕緣膜（SOG膜24，氧化矽 膜2 6 )膜厚變薄*因此可以減少在記憶格選擇用 MI SFETQs之η型半導體領域19 (源極，汲極） 之上部所形成之接觸孔28，29的縱橫比。又，利用將 位於記憶格選擇用MISFETQs之上部的氮化矽膜 2 0當作阻止膜來進行硏磨，藉此，可以減低在硏磨後之 絕緣膜（SOG膜24，氧化矽膜26)之膜厚的變動· 藉此，可以提高接觸孔2 8，2 9的加工良率。又可 以提髙被堆積在接觸孔2 8，2 9之內部的插塞材料的埋 入特性，能夠減低接點電阻。更者*在以後的過程中，由 於可以減小在周邊電路之η通道型MI SFETQn，p 通道型Μ I S F E TQ p之各源極，汲極上所形成的接觸 孔（34〜37)的縱橫比，因此可以提高接觸孔（34 〜3 7 )的加工良率。又由於可以提髙被堆積在接觸孔（ 3 4〜3 7 )之內部的配線材料的埋入特性，因此可以減 低接點電阻。 (實施形態3 ) 請參照第4 9圖〜第5 3圖來說明本發明之DRAM 的製造方法。 首茫，如第4 9圖所示，在記憶格连擇用 s. * 尺度適用中國S家榇準（CNS ) Λ4%格（2]〇乂297公藿) ---------ί 〆------IT------4ft- (谛先閏讀背面之注項再填寫本頁) -38· 412862 A7 ___B7_ 五、發明説明（36 )&quot; MI SFETQs的上部形成的位元線BL，在周邊電路 之η通道型MI SFgTQn，p通道型 MI SFETQp的上部形成第1層配線38，39。到 此爲止的過程則與上述實施形態1的過程（第3圇〜第 2 6圖）相同。 接著，在除去光阻膜4 1後，如第5 0圓所示，在位 元線BL以及第1層配線38|39的上部堆積膜厚爲 lOOnm左右的氧化矽膜80·氧化矽膜80則是藉由The Ministry of Industry and Commerce, the Central Bureau of Standards and Consumer Affairs, was eliminated by the cooperative seal W 412862 A7 B7 V. The invention (27) has excellent gap charging characteristics between the wirings, so it can be buried well to be refined to the right The bit lines BL and k to the left and right of the analysis limit of the seal are within the gap. In addition, the SOG film 44 can obtain high softening flow (reflow) characteristics even if the BPSG film is not required to be subjected to the high temperature and long-term heat treatment, so that it is possible to suppress the formation of billions in layers formed below the bit line BL. The grid selects the source of the MISFETQs, the drain, or the source of the MISFET (n-channel MI SFETQn, ρ-channel MI SFETQp) of the peripheral circuit * The thermal diffusion of impurities contained in the drain can achieve shallow junctions. Effects • Furthermore, since the oxidation of the metal (W film) constituting the gates 14A (word line WL) and the gates 14B and 14C can be suppressed, the memory cells constituting the DRA M and the MI SFETs of the peripheral circuits can be improved. performance. In addition, it is possible to suppress the oxidation of the Ti film and the TiN film constituting the bit line BL and the first layer wirings 38 and 39, thereby reducing the wiring resistance. Next, as shown in FIG. After the silicon oxide film 45 having a film thickness of about 600 nm is deposited, the silicon oxide film 45 is honed by a CMP method to make its surface flat. The silicon oxide film 45 is stacked by a plasma CVD method using, for example, ozone (〇3) and TEOS as source gases. In this way, in this embodiment, the SOG film 44 with good flatness can be spin-coated on the bit lines BL and the first layer wirings 3 8 * 3 9 even after the film is formed, or, By the CMP method, the silicon oxide film 45 deposited on the upper part of the substrate is made flat, so that in addition to the standard of the Zhongyuan Garden (CNS &gt; A4 specification (2 丨 0X297 mm) for this paper scale)- ----------: · ------ ir ------%-(锖 First read the notes on the back and then fill out this page) -30-4128.62 A7 __B7 V. Invention Explanation (28) (Yan first read the precautions on the back and then fill out this page) In addition to improving the gap charging characteristics of the gaps between the bit lines BL, the bit lines BL can also be connected to the first layer of the wiring 38, The insulating film on the upper part of the 9 becomes flat. Furthermore, because high temperature and long-term heat treatment is not performed, the characteristics of the M ISFET that constitutes the terabyte and peripheral circuits can be prevented from deteriorating, and the performance can be improved. In addition, the bit can be reduced. The resistance of the element line BL and the first-layer wirings 38 and 39. Next, as shown in FIG. 30, a film thickness of 1 is deposited on the silicon oxide film 45. The silicon oxide film 46 is about OO nm. The silicon oxide film 46 is deposited to repair the minute flaws that occur on the surface of the silicon oxide film 4 5 when honed by the CMP method. The silicon oxide film 46 is It is deposited by, for example, a plasma CVD method using ozone (〇3) and TEOS as source gases. * Next, as shown in FIG. 31 * By dry etching using a photoresist film 4 7 as a mask, the position is removed. The silicon oxide films 4 6 and 45 above the contact holes 29 and the SOG film 44 and the silicon oxide film 31 are formed through holes 48 that reach the surface of the plug 30. This etching is performed on the silicon nitride film. It is performed under conditions that the etching rate of the silicon oxide film 46, 5 1, 31, and the SOG film 44 is small, and even if the alignment of the through-hole 48 and the bit line BL is deviated, the bit can be positioned. The silicon nitride film 40 above the line BL and the sidewall spacer layer 43 will not be cut deep. "Through this, the through hole 48 can be formed in a self-integrated manner with respect to the bit line BL." Next, the photoresist film is removed. After 47, an etching solution such as a hydrofluoric acid + ammonium fluoride mixture is used to remove the surface of the plug 30 exposed at the bottom of the through hole 48. Etching residue, natural oxide film, etc. At this time, although it is exposed on *-*, the paper scale is applicable to the Zhongyuan Garden Kneading Ratio (CNS) Λ4 specification (2 丨 0X297 mm) -31-Central Ministry of Hibernation β 工 消 消 合 社 印 装 412862 at B7 V. Description of the Invention (29) 1 'The through-hole SOG film 44 on the side wall of the 8 is also exposed to the etchant, but as mentioned above, due to the SOG film 44, the Sintering at a high temperature of about 800 ° C can reduce the etching rate with respect to the fluoric acid-based etching solution. Therefore, the side wall of the through hole 48 will not be undercut significantly due to the wet etching process. Thereby, it is possible to surely prevent the plugs buried in the through holes 48 from being short-circuited with each other in the following process. In addition, since the plug is sufficiently separated from the bit line BL, the increase in the parasitic capacitance of the bit line BL can be suppressed. Next, as shown in FIG. 32, a plug 4 9 is formed inside the through hole 48. The plug 49 is deposited on the silicon oxide film 46 by doped η by CVD. Polycrystalline silicon film of type impurity (such as P (phosphorus), and then the polycrystalline silicon film is subjected to an ethch back method to remain inside the through-holes 48 and 8 ". Then, as shown in FIG. On the top of the silicon film 46, a silicon nitride film 51 having a thickness of about 100 nm is deposited by a CVD method, and then the peripheral circuit area is removed by dry etching using the photoresist film 52 as a mask. Silicon nitride film 51. The silicon nitride film 51 remaining in the memory array, when forming the lower electrode of the data storage capacitor element described later, when the silicon oxide film is positioned between the lower electrodes It is used as an etching stopper during etching. Next, after removing the photoresist film 5 2, as shown in FIG. 34, a film thickness is deposited on the silicon nitride film 51 at a thickness of 1 · 4 // m. The left and right silicon oxide films 5 3 are removed by dry etching using the photoresist film 54 as a mask to remove the silicon oxide film 5 3 and the silicon nitride film 51. The upper part of the hole 4 8 is formed ^ 1 * The paper size is suitable for China Standard (CNS) A4 gauge # (2 丨 0X297 mm) ^ -32-· —) 11 ----- order 丨 ---- ίΑ 丨 (Please read the note on the back ^ ►item before filling this page) 妗 中 中 中 准 局 β-τ- 消 于 合 竹 社 印 紫 412862 5. Description of the invention () 30 ditch 5 5 * here At the same time, a frame-shaped trench 5 5 a · silicon oxide film 5 3 is formed around the memory array, and the plasma CVD method using ozone (〇3) and TEOS as source gases is formed. And the pile of crickets. Next, after removing the photoresist film 54, as shown in FIG. 35, a film thickness doped with n-type impurities (for example, P (phosphorus)) is deposited on the silicon oxide film 53 by an CVD method. It is a polycrystalline silicon film 5 6 around 60 nm. The polycrystalline silicon film 56 is used as a material for the lower electrode of a capacitor element for storage. Next, as shown in FIG. 36, by a spin coating method, an SOG film 57 having a film thickness sufficient to embed the trenches 55, 55a (for example, about 300 to 400 nm) is applied on the upper portion of the polycrystalline silicon film 56. Volatilization: After baking the SOG film 57 by heat treatment at about 400 ° C, the SOG film 57 is subjected to flat etching (etch back) as shown in Fig. 37 (a), or by alignment. The polycrystalline silicon film 56 on the silicon oxide film 53 is flat-etched, so that the polycrystalline silicon film 56 can remain inside the grooves 55 and 55a. Next, as shown in FIG. 38, the periphery is covered with a photoresist film 58. The silicon oxide film 5 3 in the circuit field removes the silicon oxide film 5 3 between the SOG film 5 7 and the trench 55 5 inside the trench 5 5 by wet etching to form a lower electrode 6 0 of the data storage capacitor element. . At this time, “Since the silicon nitride film 51 remains in the gap between the trenches 5 and 5, ifc, the oxide film 46 of this gap will not be etched.” Also, the photoresist of the silicon oxide film 5 3 covering the peripheral circuit area is covered. One end of the film 5 8 is configured at the standard Chinese Garden Standard (CNS) A4 (2I0X297 mm) which is formed on the paper scale of the Chi-Yi array. ---- ^ ------ Xia-. (Please read the note f on the back side before filling out this page) -33- The central aphid department of the aphid bearing department disappeared in cooperation. Print 412862 at _B7 V. Description of the invention) οι The outermost boundary between the lower electrode 60 and the peripheral circuit area, that is, the upper part of the groove 5 5 a. Therefore, even if the alignment deviation of the photoresist film 58 occurs due to its end It will not be located on the lower electrode 60 formed on the outermost side of the memory array. Therefore, the SOG film 53 will not remain inside the groove 55 of the lower electrode 60, or the silicon oxide film 53 will not The gap between the lower electrode 60 and the groove 5 5 a remains. In addition, since a part of the silicon oxide film 53 in the peripheral circuit area is not exposed to the etching solution, a part of the silicon oxide film 53 in the peripheral circuit area is not cut into deep grooves. Next, the photoresist film 5 is removed. 8 | In order to prevent the polycrystalline silicon film (5 6) constituting the lower electrode 60 from oxidizing, the semiconductor substrate 1 is placed in an ammonia environment, and heat treatment is performed at about 8 0 ° C, so that the surface of the polycrystalline silicon film 5 6 After nitriding, as shown in FIG. 39, a T a 20 (oxidized giant) film 61 having a film thickness of about 20 nm is deposited on the upper portion of the lower electrode 60 by a CVD method, and then a semiconductor is formed. The substrate 1 is heat-treated at about 80 0 eC * to repair the defects of the Ta205 film 61. The Ta 2 05 film 61 is used as a capacitor insulating film material for a data storage capacitor element. Next, as shown in FIG. 40, a Ta 2 0s film is formed by a CVD method and a sputtering method. After the T i N film 6 2 having a film thickness of about 150 nm is deposited on the upper part of 61, dry etching using the photoresist film 63 as a mask is performed. The N i film 6 2 and the Ta 2 0 film 6 1Implement a pattern to form an upper electrode formed by a T i N film 62, a capacitor insulating film formed by a 73205 film 61, and a lower electrical paper formed by a polycrystalline silicon film 5.6 g-house standard (CNS) Λ4 is present (2 丨 0X297 mm) ----: 丨 _ „--------- 1T -------- Cheng-(Please read first Note the item on the back of Jing. Please fill in this page again.) -34- 412862 a? B7 V. Description of the invention (32) Capacitor element C for data storage composed of pole 60. This completes the selection of M IS by the memorizer. f E TQ s and the memory cell of the DRAM constituted by the data storage capacitor element #C connected in series here. Next, after removing the photoresist film 63, as shown in FIG. 41, the data storage capacitor element C The thickness of the upper layer of oxygen is about 100 nm. The silicon film 6 4. The silicon oxide film 65 is stacked by a plasma CVD method using, for example, ozone (0 3) and TEOS as source gases. • Then • by using a photoresist film 65 as a mask. By dry etching, a via hole 6 6 β is formed by removing the vaporized silicon film 64, 53, 46, 45, the SOG film 44, and the silicon nitride film 40 located above the first layer wiring 38 of the peripheral circuit. After the photoresist film 65 is removed, as shown in FIG. 42, a plug 6 7 is formed inside the through hole 66, and then a second layer of wiring 68, 69 is formed on the silicon oxide film 64. 67, a T i N film with a film thickness of about 100 nm is deposited on the oxide p film 64 by a sputtering method, and a film thickness of 5 is deposited on the upper part by a CVD method. After W films of about 0 0 nm, these films are flat-etched * and formed by remaining inside the through-holes 66. The second-layer wirings 68 and 69 are formed on the silicon oxide by a sputtering method. A T i N film with a film thickness of about 50 nm, an A 1 film with a film thickness of about 60 nm, and a T i film with a film thickness of 50 nm were formed on the upper part of the film 64, and then a photoresist film was used. Dry etching as a mask The pattern is formed. Then, as shown in Fig. 43 *, an interlayer insulating film is deposited on the second layer of wiring 68 * 69. The interlayer insulating film is made of, for example, a film thickness of 3 0 0, which is a paper standard in Shizhou. (CNS) A4il (210X297 mm) (Please read the notes on the back and fill in this page to order this page and order it from the Ministry of Economic Affairs and other consumer cooperatives -35- 412862 A7 _B7 V. Description of the invention ( 33). {Read the notes on the back and fill in this page before filling in this page) A vaporized silicon film with a thickness of about 7 nm, a SOG film 72 with a thickness of about 400 nm, and a silicon oxide film with a thickness of about 300 nm 7 3 ^ 成。 By ^ cheng. The silicon oxide films 7 1 and 7 3 are deposited by, for example, a plasma CVD method using ozone (0 3) and TEOS as source gases. The baking of the SOG film 72 is performed at a temperature of about 400 ° C in order to prevent deterioration of the second-layer wirings 68 and 69 mainly composed of the A 1 film. The purpose of rebaking is to evaporate the solvent. Therefore, the baking temperature will be higher than the baking temperature for the SOG films 24 and 44. Then, as shown in Fig. 4, a through-hole 7 is formed in the interlayer insulating film located above the capacitor C for data storage. 4. After forming a through hole 7 5 above the second layer wiring 6 9 of the peripheral circuit, a plug 7 6 is formed inside the through hole 74 * 7 5-and then a third layer is formed on the upper part of the interlayer insulating film Wiring 77, 78, 79. The through holes 74 and 75 are formed by removing the silicon oxide film 73, the SOG film 72, and the silicon oxide film 64 by dry etching using a photoresist film as a mask. Here, since the mixed solution of hydrofluoric acid + ammonium fluoride is not used for washing, it is not necessary to perform high-temperature heat treatment on the SOG film. After that, although a passivation film composed of a silicon oxide film and a silicon nitride film is deposited on the third layer wirings 7 7 to 7 9, the illustration is omitted. Through the above process, the D R AM of this embodiment is roughly completed. (Applied Form 3) Please refer to Figure 45 to Figure 4-8 to explain the paper size of this embodiment that is applicable to Chinese standards ((, NS &gt; 厶 4 wash grid (2 丨 0X297 mm)- 36- 412862 a? _____B7 V. Description of the invention k) DRA Μ manufacturing method. {Read the precautions on the back before filling in this page) 'First, as shown in Figure 4-5, when the memory cell is formed, MI is selected. SKETQs and peripheral circuits of the η-channel MI SFETQn and ρ-channel MI SFETQp semiconductor substrate 1 are spin-coated with an SOG film 24 having a thickness of about 300 nm, and then, the semiconductor substrate 1 * A heat treatment was performed at 800 ° C for 1 minute. After the s 0G film 24 was sintered, a silicon oxide film 25 having a thickness of about 600 nm was deposited on the top of the S 0G film 24. The process up to this point is the same as the process of the first embodiment (FIG. 3 to FIG. 18) * In the first embodiment, although the silicon oxide film 25 is subsequently honed by the CMP method, In this embodiment, as shown in Figs. 46 and 6, after honing the silicon oxide film 25, honing is performed even on the underlying S0G film 24. "This honing | Billion Cell chose to use the silicon oxide film 20 of MI SFETQs as the stopper film, and stopped honing when its surface was exposed. Next, as shown in FIGS. 4 to 7 * After the silicon oxide film 2 6 having a thickness of about 100 nm is deposited on the silicon oxide film 25, the photoresist film 2 is used as shown in FIG. 48. 7 as a mask for dry etching to remove the silicon oxide film 26 and the SOG film 24 located above the n-type Yin conductor region 19 (source, drain) of the memory cell selection MISFETQs, and then remove the silicon nitride. The film 15 and the gate oxide film 13 form a contact hole 2 8 on one of the n-type semiconductor regions 19 (source, drain), and a contact hole 2 9 on the other part. The paper size of this paper is applicable to Chinese K-standard (CNS) A4 specifications (210X297 mm) -37 · Jie Yuzhong Juquan Bing J Xiao Yu Hezhu Club Printing 412862 A7 __B7 _ V. Description of the invention ( 35) The procedure is the same as the first embodiment. 'According to this embodiment, it is possible to reduce the thickness of the insulating film (SOG film 24, silicon oxide film 2 6) of the memory channel selection MI SFETQs and the peripheral circuit η-channel MI SFET and P-channel MI SFE. * Therefore, the aspect ratios of the contact holes 28 and 29 formed on the n-type semiconductor region 19 (source, drain) of the memory cell selection MI SFETQs can be reduced. In addition, the silicon nitride film 20 located on the upper part of the memory cell selection MISFETQs is used as a blocking film to perform honing, thereby reducing the insulating films (SOG film 24, silicon oxide film 26) after honing. Variation of film thickness · This can improve the processing yield of the contact holes 28, 29. It is also possible to improve the embedding characteristics of the plug material accumulated inside the contact holes 28, 29, and to reduce the contact resistance. Furthermore, in the later process, the aspect ratio of the contact hole (34 ~ 37) formed on the drain of each source of the n-channel MI SFETQn and p-channel MI ISFE TQ p in the peripheral circuit can be reduced. Therefore, it is possible to improve the processing yield of the contact hole (34 to 37). In addition, the embedded characteristics of the wiring materials accumulated inside the contact holes (34 to 37) can be improved, so that the contact resistance can be reduced. (Embodiment 3) A method of manufacturing a DRAM according to the present invention will be described with reference to FIGS. 49 to 53. First, as shown in Figure 4-9, use s in the memory grid. * The scale is applicable to the Chinese family standard (CNS) Λ 4% grid (2) 〇 乂 297 乂) -------- -ί 〆 ------ IT ------ 4ft- (谛 Please read the notes on the back before filling out this page) -38 · 412862 A7 ___B7_ V. Description of the Invention (36) &quot; MI SFETQs The bit lines BL formed on the upper part form first layer wirings 38 and 39 on the n-channel type MI SFgTQn and p-channel type MI SFETQp of the peripheral circuit. The process up to this point is the same as the process of the first embodiment (Figs. 3 to 26). Next, after removing the photoresist film 41, as shown by the 50th circle, a silicon oxide film 80 and a silicon oxide film 80 having a film thickness of about 100 nm are deposited on the bit lines BL and the first layer wirings 38 | 39. Is by

例如以臭氧（03)與TEOS作爲來源氣體的電漿CVD 法而堆積。亦即，本實施形態，並不在位元線B L之側壁 與第1層配線3 8，39的側壁形成氮化矽的側壁間隔層 〇 接著，如第5 1圖所示，在氧化矽膜8 0的上部旋轉 塗佈膜厚爲3 0 0 nm左右的SOG膜2 1 4，接著在對 半導體基板1，在8 0 0 °C下進行1分鐘的熱處理，而使 5 0 G膜4 4燒結後，在S 0 G膜4 4的上部堆積膜厚爲 6 0 0 nm左右的氧化矽膜4 5。氧化矽膜4 5則是藉由 以例如臭氧（〇3)與TEOS作爲來源氣體的電漿CVD 法而堆積。 接著•如第5 2圖所示，藉由CVp法，對氧化矽膜 45，SOG膜44，以及氧化矽膜80進行蝕刻*該硏 磨則利用將覆蓋位元線BL以及第1層配線3 8，39的 氮化矽膜4 0作爲阻止膜而進行，當其表面露出時，則停 止硏磨 、· ♦ 本紙張尺度適用+囤园家標準（（:阳）六4規格（2丨(^297公羞&gt; (諳先閲讀背面之注項再填将本頁) -訂 &quot;I . -39- 412862 a7 _____B7 五、發明说明（37 ) ' 接著，如第5 3圖所示，當在位元線B L以及第1層 配線3 8，3 9的上部堆積膜厚爲1 0 〇 nm所氧化矽膜 4 6後，藉由以光阻膜4 7作爲掩罩的乾蝕刻，來除去位 在接觸孔2 9之上部的絕緣膜，藉此而形成通孔4 8。以 後的過程則與上述實施形態1相同* 如本實施形態，當未在位元線B L的側壁形成氮化矽 膜的側壁間隔層時，則無法使通孔4 8相對於位元線B L 呈自我整合地形成》因此，爲了要確實地防止在接下來的 過程中被埋入到通孔4 8之內部的插塞與位元線B L發生 短路，因此必須要減小通孔4 8的直徑，或是縮小位元線 B L寬度》 根據本實施形態，由於可以使覆蓋位元線B L以及第 1層配線3 8，3 9之絕緣膜的膜厚變薄，因此可以減小 在接觸孔2 9之上部所形成之通孔4 8的縱横比。又，由 於利用將覆蓋位元BL以及第1絕緣膜38，3 9的氮化 矽膜4 0作爲阻止膜來進行硏磨，因此，可以減低在硏磨 後之絕緣膜的膜厚的變動。 經潢部中决糅聿局貝J消资合作社印繁 (讀先聞讀背面之注意事項再填寫本頁) 藉此，可以提高通孔4 0的加工良率。又*由於提高 被堆積在通孔4 8之內部的插塞材料的埋入特性|因此可 以減低接點電阻· ， (實施形態4 ) 請參照第5 4圖〜第5 7圖來說明本實施形態的 D R A Μ的製造過程· . 本紙浪尺度適用中囷囤家標丰（A4规格（210X297公嫠&gt; -40 - 抒澇部中决樣埠^消费合作il印裝 _B7__ 五、發明説明（38 )' 首先，如第5 4圖所示’在形成有記憶格選擇用 M I S F E TQ s以茇周邊電路之η通道型 MI SFETQn，ρ通道型MI SFETQp的半導體 基板1上則旋轉塗佈SOG膜24。該SOG膜24的膜 厚則設成較上述實施形態1的膜厚（3 0 0 nm左右）爲 厚的厚度，例如7 0 0 n m左右》 接著，當使半導體基板1，在800 °C下進行1分鐘 左右的熱處理，而將上述S OG膜2 4燒結後，如第5 5 圖所示，藉由CMP法對SOG膜2 4實施硏磨。如本實 施形態所示，當以厚的膜厚來堆積S OG膜2 4時，由於 SOG膜2 4的硏磨磨量變多，因此，即使是在其上部不 堆積氧化矽膜（2 5)，也可以提高其表面的平坦性。當 藉由CVD法來硏磨SOG膜2 4時，如第5 6圖所示， 與上述實施形態2同樣地，利用將覆蓋記憶格選擇用 M rs F E TQ s的氮化矽膜2 0作爲阻止膜來使用，當 其表面露出時，則停止硏磨。 接著，如第57圖所示，當藉由CVD法，在SOG 膜2 4的上部堆積膜厚爲1 0 0 nm左右的氧化矽膜2 6 後，藉由以光阻膜2 7作爲掩罩的乾蝕刻，來除去位在記 億格選擇用MI SFETQs之η型半-體領域19 (源 極，汲極）的上部的絕緣膜，藉此，在η型半導體領域 1 9 (源極，汲極）的其中一個的上部形成接觸孔2 8， 而在另一個的上部形成接觸孔2 9，以後的過程則與上述 實施形態U相同。 本紙乐尺度讁周中國S家標準（CNS &gt; A4規格（210X297公釐） {請先閲讀背面之注f項再填寫本Κ) 訂 44I . -41 - 412862 五、發明说明（39 ) 根據本實施形態•由於利用2層的絕緣膜（s 0G膜 24以及氧化矽膜26)，可以使位在記億格選擇用 MI skETQs以及周邊電路之η通道型 MI SFETQn，ρ通道型MI SFETQP之上部的 絕緣膜變爲平坦，因此可以減少製造過程。 雖然未圖示，但是在位元線B L以及第1層配線3 8 ，3 9的上部旋轉塗佈膜厚厚到7 0 0 nm左右的SOG 膜44，接著，在使半導體基扳1，在80CTC下進行1 分鐘左右的熱處理，而對S 0G膜4 4實施燒結後，藉由 CMP法來硏磨SOG膜44，由於使用2層的絕緣膜（ SOG膜44以及氧化矽膜46)，可以使位在位元線 BL以及第1層配線3 8，39之上部的絕緣膜變爲平坦 ，因此更可以減少製造過程。 (實施形態5 ) 請參照第5 8圖〜第6 1圖來說明本實施形態之 D R A Μ的製造過程。 烀&quot;部中决枒卑局βΗ消合作社印52 (讀先聞讀背面之注意事項再填转本頁) 如上述實施形態4，當將SOG膜塗厚，而進行高溫 燒結時，則容易在膜中發生裂痕，爲了要防止此一情形， 首先，如第5 8圖所示•在形成有記億塔選擇用 MISFETQs以及周邊電路之η通道型 MI SFETQn，ρ通道型MI SFETQp的半導體 基板1上旋轉塗佈膜厚爲350nm的SOG膜24a， 接著，則使半導體基板1，在8 0 Ot ；f進行1分鐘左右 本紙張尺度读用中國围家揉準（（，呢）六4規&lt;格（2丨0&gt;&lt;297公釐） • 42- _^12862___£___ 五、發明説明（^ ):: 40 的熱處理，而對SOG膜2 4 a實施燒結* 接著，如第5 9®所示，在SOG膜2 4的上部旋轉 塗佈膜厚爲350nm左右的SOG膜24b ’接著，則 使半導體基板1在8 0 0 °C下進行1分鐘左右的熱處理， 而對SOG膜246實施燒結。藉此，2層的SOG膜 24a，24b合計的膜厚成爲700nm左右。 接著，如第6 0圖所示•藉由CMP法來硏磨SOG 膜24b (或是位在其下層的SOG膜24a)，而使其 表面變爲平坦。此時，與上述實施形態2同樣地，利用將 覆蓋記憶格選擇用MISFETQs的氧化矽膜20作爲 阻止膜來使用，在其表面露出時，則停止硏磨》 接著，如第6 1圖所示，當藉由CVD法在SO G膜 246 (或S0G膜24a)的上部堆積膜厚爲1〇〇 nm左右的氧化矽膜2 6後，藉由以光阻膜2 7作爲掩罩 的乾蝕刻，來除去位在記憶格選擇用Μ I S F E TQn之 η型半導體領域1 9 (源極，汲極）之上部的絕緣膜，在 η型半導體領域1 9 (源極，汲極）之其中一個的上部形 成接觸孔2 8，而在另一個的上部形成接觸孔2 9。以後 的過程則與上述實施形態1相同。 根據本實施形態，將S0G膜（2,4 a ，24b)的 塗佈以及燒結分成2次·藉由使被實施1次燒結之SOG 膜的膜厚變薄，可以抑制在膜中發生裂痕。 SOG膜的塗佈以及燒結，也可以分成3次或是更多 次。又*雖然未圖示，但是即使是在位元線B L以及第1 、* j 本紙張尺度ΐί用中SS家梯準（rNS M4規格（210X297公釐） ------:----.------1T------^ I (讀先閱讀背面之注意事項再填寫本頁) -43- 412862 A7 B7 五、發明説明匕）a 41 層配線38，39的上部旋轉塗佈厚的SOG膜44，藉 由將其塗佈以及燒結分成多次，也可以抑制裂痕的發生。 (誚先W讀背面之注$項再填寫本頁) (實施形態6 ) 請參照第6 2圖〜第6 6圖來說明本實施形態之 DRAM的製造方法。 首先，如第6 2圖所示，在記憶格選擇用 MI SFETQs的上部形成位元線BL，而在周邊電路 之η通道型MISFETQn，p通道型 MI SFETQp的上部形成第1層配線38，39 * 在形成位元線BL以及第1層配線38，39時，首 先藉由噴濺法，在氧化矽膜3 1的上部堆積膜厚爲5 0 nm左右的Ti膜，使半導體基板1 *在800 °C左右下 進行熱處理•接著，則藉由噴濺法，在T i膜的上部，堆For example, a plasma CVD method using ozone (03) and TEOS as source gases is deposited. That is, in this embodiment, a sidewall spacer of silicon nitride is not formed on the sidewall of the bit line BL and the sidewalls of the first layer wirings 38 and 39. Next, as shown in FIG. 51, the silicon oxide film 8 The SOG film 2 1 4 with a film thickness of about 300 nm is spin-coated on the upper part of 0, and then the semiconductor substrate 1 is heat-treated at 800 ° C for 1 minute to sinter the 50 G film 4 4 Then, a silicon oxide film 4 5 having a film thickness of about 600 nm is deposited on the S 0 G film 4 4. The silicon oxide film 45 is deposited by a plasma CVD method using, for example, ozone (〇3) and TEOS as source gases. Then, as shown in FIG. 52, the silicon oxide film 45, the SOG film 44, and the silicon oxide film 80 are etched by the CVp method. The honing is performed by covering the bit lines BL and the first layer wiring 3 The silicon nitride film of 8, 39 is used as a blocking film. When the surface is exposed, the honing is stopped. ♦ This paper is applicable to the standard of the paper + storehouse standard ((: yang) 6 4 specifications (2 丨 ( ^ 297 public shame> (谙 first read the notes on the back and then fill in this page) -Order &quot; I. -39- 412862 a7 _____B7 5. Invention Description (37) 'Then, as shown in Figure 5 3, After the silicon oxide film 46 having a film thickness of 100 nm is deposited on the bit lines BL and the first layer wirings 38 and 39, a dry etching process using the photoresist film 47 as a mask is performed. The through hole 4 8 is formed by removing the insulating film located above the contact hole 29. The subsequent process is the same as that in the first embodiment described above. * In this embodiment, when no nitride is formed on the sidewall of the bit line BL When the sidewall spacer of the silicon film is used, the through-holes 48 and 8 cannot be formed in a self-integrated manner with respect to the bit line BL. Therefore, in order to reliably prevent the following process, The plug buried in the through hole 48 is short-circuited with the bit line BL. Therefore, it is necessary to reduce the diameter of the through hole 48 or reduce the width of the bit line BL. According to this embodiment, since the The film thickness of the insulating film covering the bit lines BL and the first-layer wirings 38, 39 is reduced, so that the aspect ratio of the through-holes 4 and 8 formed on the contact hole 29 can be reduced. Honing is performed by using the silicon nitride film 40 covering the bit BL and the first insulating film 38, 39 as a barrier film, so that the variation in film thickness of the insulating film after honing can be reduced. Decisiveness Bureau J Consumer Cooperative Co., Ltd. Yinfan (read the notes on the back and then fill out this page) This can improve the processing yield of the through hole 40. Also * due to the increase in the accumulation of through holes 4 8 Embedded characteristics of the internal plug material | Therefore, contact resistance can be reduced. (Embodiment 4) Please refer to FIGS. 54 to 57 to describe the manufacturing process of the DRA M of this embodiment.. Standards apply to Zhongli storehouse standard Fengfeng (A4 size (210X297 males &gt; -40)-the sample port in the Ministry of Waterlogging ^ consumption Printed as il__B7__ 5. Description of the invention (38) First, as shown in Fig. 5 ', MISFE TQ s for memory cell selection is used to form the n-channel MI SFETQn and p-channel MI SFETQp of peripheral circuits. The semiconductor substrate 1 is spin-coated with an SOG film 24. The thickness of the SOG film 24 is set to be thicker than the film thickness (about 300 nm) of the first embodiment, for example, about 700 nm. Next, the semiconductor substrate 1 is subjected to a heat treatment at 800 ° C for about 1 minute, and the SOG film 24 is sintered. As shown in Fig. 5 and 5, the SOG film 24 is subjected to the CMP method. mill. As shown in this embodiment, when the SOG film 24 is deposited with a thick film thickness, since the honing amount of the SOG film 24 is increased, the silicon oxide film is not deposited even on the upper portion (25) , Can also improve the flatness of its surface. When the SOG film 24 is honed by the CVD method, as shown in FIG. 56, as in the second embodiment, a silicon nitride film 20 covering the memory cell selection M rs FE TQ s is used as Prevent the film from being used, and stop honing when its surface is exposed. Next, as shown in FIG. 57, when a silicon oxide film 2 6 having a thickness of about 100 nm is deposited on the SOG film 24 by a CVD method, a photoresist film 27 is used as a mask. Dry etching to remove the insulating film located on the upper part of the n-type half-body region 19 (source, drain) of the MI SFETQs selected by the grid, thereby, in the n-type semiconductor field 19 (source, A drain hole 28 is formed in the upper part of one of the drain electrodes, and a contact hole 29 is formed in the upper part of the other. The subsequent process is the same as the above-mentioned embodiment U. Chinese paper standard of this paper (Chinese standard of CNS &gt; A4 (210X297mm) {Please read the note f on the back before filling this K) Order 44I. -41-412862 V. Description of the invention (39) Implementation mode • The use of two layers of insulating films (s 0G film 24 and silicon oxide film 26) enables the upper part of η-channel MI SFETQn and ρ-channel MI SFETQP for MI skETQs for selection and peripheral circuits. The insulating film becomes flat, so the manufacturing process can be reduced. Although not shown, an SOG film 44 having a film thickness of about 700 nm is spin-coated on the bit lines BL and the first layer wirings 3 8 and 39, and then the semiconductor substrate 1 is placed on Heat treatment is performed at 80CTC for about 1 minute, and the SOG film 44 is sintered, and then the SOG film 44 is honed by the CMP method. Since a two-layer insulating film (SOG film 44 and silicon oxide film 46) is used, Since the insulating film located above the bit line BL and the first layer wirings 38 and 39 is flattened, the manufacturing process can be further reduced. (Embodiment 5) The manufacturing process of D R A M according to this embodiment will be described with reference to Figs. 58 to 61.烀 &quot; Ministry of the Middle and the Hungry Bureau βΗelimination of cooperative cooperative seal 52 (read the notes on the back and then fill in this page) As in the fourth embodiment, when the SOG film is thickened and high temperature sintering is performed, it is easy In order to prevent cracks in the film, first, as shown in Fig. 58. • Semiconductor substrates with η-channel type MI SFETQn and ρ-channel type MI SFETQp for MISFETQs for selection and peripheral circuits are formed. The SOG film 24a with a film thickness of 350 nm is spin-coated on 1 and then the semiconductor substrate 1 is subjected to 80 Ot; f for about 1 minute. &lt; Grid (2 丨 0 &gt; &lt; 297 mm) • 42- _ ^ 12862 ___ £ ___ V. Description of the Invention (^) :: 40 heat treatment, and sintering the SOG film 2 4 a * Then, as described in Section 5 As shown in 9®, the SOG film 24b 'with a film thickness of about 350 nm is spin-coated on the upper part of the SOG film 24. Next, the semiconductor substrate 1 is heat-treated at 800 ° C for about 1 minute, and the SOG film is then applied. Sintering is performed in 246. As a result, the total thickness of the two layers of SOG films 24a and 24b becomes approximately 700 nm. Shown • The SOG film 24b (or the underlying SOG film 24a) is polished by the CMP method to flatten the surface. At this time, as in the second embodiment, the memory cell is covered by using The silicon oxide film 20 of MISFETQs is selected to be used as the stopper film. When the surface is exposed, the honing is stopped. Then, as shown in FIG. 61, when the SO G film 246 (or SOG film 24a) is formed by the CVD method, After the silicon oxide film 26 having a film thickness of about 100 nm is deposited on the upper part of the substrate, the n-type semiconductor located in the memory cell selection M ISFE TQn is removed by dry etching using the photoresist film 27 as a mask. In the insulating film above the area 19 (source, drain), a contact hole 28 is formed in the upper part of one of the n-type semiconductor areas 1 9 (source, drain), and the contact hole is formed in the upper part of the other. 2 9. The subsequent process is the same as that in the above-mentioned Embodiment 1. According to this embodiment, the coating and sintering of the S0G film (2, 4 a, 24b) are divided into two times. The SOG film is sintered once. The thickness of the film can be reduced to prevent cracks in the film. The coating and sintering of the SOG film can also be divided into 3 or more times. * Although not shown, but even in bit line BL and the first, * j paper standard, SS standard (rNS M4 specification (210X297 mm)- ----: ----.------ 1T ------ ^ I (Read the precautions on the back before filling out this page) -43- 412862 A7 B7 V. Inventive Instructions Dagger) A 41-layer wiring 38, 39 is spin-coated with a thick SOG film 44 at the top, and cracking can be suppressed by coating and sintering it several times. (Please read the note on the back side before filling in this page.) (Embodiment 6) Please refer to FIGS. 62 to 66 to describe the method of manufacturing the DRAM according to this embodiment. First, as shown in FIG. 62, a bit line BL is formed on the memory cell selection MI SFETQs, and a first layer wiring 38, 39 is formed on the n-channel MISFETQn and p-channel MI SFETQp of the peripheral circuit. * When forming the bit line BL and the first layer wirings 38 and 39, firstly, a Ti film having a thickness of about 50 nm is deposited on the silicon oxide film 31 by a sputtering method, so that the semiconductor substrate 1 * Heat treatment is performed at about 800 ° C. Then, by spraying,

I 烀漭部中次枒-&quot;局Mh&quot;·汾合作社印&quot; 積膜厚爲5 0 n m左右的T i N膜，更者•當藉由C VD 法·在其上部堆積膜厚爲1 5 Onm左右的W膜後，以光 阻膜4 1作爲掩罩，對該些膜厚爲1 5 0 nm左右的W膜 後，以光阻膜4 1作爲掩罩，對該些膜實施圖案。亦即， 本實施形態•在位元線B L以及第1層配線3 8 * 3 9的 上部未堆積氮化矽膜40。 （ 接著，在除去光阻膜4 1後，如果6 3圖所示，在位 元線BL以及第1層配線38 | 39的上部堆積膜厚爲 1 0 0 nm左右的氧化矽膜8 1。氧化矽膜8 1則是藉由 以例如臭澴（0 3 )與T E 0 S作爲來源氣體的電漿 '本紙張尺度適用中HS家梯率&lt; ('NS) Λ4規格（2丨0父297公藿) ' -44- «济部中次橾卑局貝J-消於合作社印¾ 412862 at ____B7 五、發明説明（42 ) CVD法而堆積。亦即，本實施形態，在位元線b L的側 壁與第1餍配線3 8，3 9的側壁未形成氮化矽的側壁間 隔層· 接著’如第6 4圖所示，在氧化矽膜8 1的上部旋轉 塗佈膜厚爲3 0 0 nm左右的S 0G膜4 4，接著則使半 導體基板1，在8 0 0 °C下進行1分鐘左右的熱處理，且 對SOG膜44實施燒結。 接著，如第6 5圖所示，當在SOG膜4 4的上部堆 積膜厚爲6 0 0 nm左右的氧化矽膜4 5後，藉由CMP 法，對氧化矽膜4 5實施硏磨，而使其表面變爲平坦。氧 化矽膜4 5，則是藉由例如以臭氧（0 3 )與T E 0 S作爲 來源氣體的電漿CVD法而堆積》 接著，如第6 5圖所示，當在氧化矽膜4 5的上部堆 積膜厚爲1 0 0 nm左右的氧化矽膜4 6後，藉由以光阻 膜4 7作爲掩罩的乾蝕刻，來除去位在接觸孔2 9之上部 的絕緣膜，而形成通孔4 8。以後的過程則與上述實施形 態1相同。 如本實施形態般，當在位元線B L的上部不形成氮化 矽膜4 0，且在側壁不形成氮化矽的側壁間隔層時，則無 法相對於位元線B L呈自我整合地形成p孔4 8。因此， 爲了要確實地防止在接下來的過程中，被埋入到通孔4 8 之內部的插塞與位元線B L發生短路，必須要減小通孔 4 8的直徑，或是減小位元線B L的寬度。 根據本實施形態，與上述實施形態.1同樣地|在不使 * * 本紙張尺度適用中國囤家榡哗（CNS ) Λ4規格（210X297公釐） {婧先閲讀背面之注意事項再填寫本頁) 訂 -45- 412SQ2 五、發明说明（43 ) 構成記憶格以及周邊電路之Μ I S F E T的特性惡化的情 況下，除了可以提高位元線B L彼此之微細間隙的間隙塡 充性外，也可以使位在位元線BL以及第1層配線3 8， 3 9之上部的絕緣膜變爲平坦。又可以確實地防止被埋入 到通孔4 8之內部的插塞4 9與位元線B L發生短路。 以上雖然是根據發明的實施形態來具體地說明本發明 人所提出的發明•但是本發明並不限於上述實施形態，在 不脫離其要旨的範圍內，當然可以進行各種的變更。 在上述實施形態1〜6中，雖然是針對應用在 DRAM之製造過程的情形來加以說明，但是本發明，記 憶體LSI或是邏輯LSI自不待言，也可以廣泛地應用 在具有一般依據微細之間隔而形成之電極配線的高積體 L S I的製造過程上。 又，本發明也可以應用在混合載有邏輯電路與 DRAM的LSI等上。 (發明之效果） 衧涝部中戎樣ί?·局δ Η消費合作社印髮 在本案的掲露的發明中，若是簡單地說明由代表例所 得到的效果時，則如下所述· 根據本發明，可以在不使Μ I S F E T之特性變惡化 \ 的情況下，使位在依微細間隔被形成之電極配線的上部的 絕緣膜變爲平坦· 根據本發明，由於可以減低開孔於絕緣膜之連接孔的 縱橫比，因此，可以提高配線的連接信.賴性以及減低接觸 •η ( , 本紙張尺度適用中國囷家橾率（（、NS ) Λ4Μ ( 210X297公釐） -46- A7412862 _〜W62 _B7____ 五、發明説明（Μ )&quot; 孔電阻》 (錆先Μ讀背面之注意&quot;項苒填寫本頁&gt; 根據本發明，由於可以防止當在包含S 0 G膜的絕緣 膜形成i接孔後，因爲濕蝕刻導致連接孔徑擴大，因此可 以防止配線的短路以及減低寄生電容。 圖式說明 第1圖係已形成本發明之實施形態1之DRAM的半 導體基板的整體的平面圖。 第2圖係本發明之實施形態1之D R A Μ的等效電路 圖。 第3圖係表本發明之實施形態1之DRAM之製造方 法的半導體基板的主要部分的斷面圖。 第4圖係表本發明之實施形態1之DRAM之製造方 法的半導體基板的主要部分的斷面圖。 ^ 第5圖係表本發明之實施形態1之DRA Μ之製造方 法的半導體基板的主要部分的斷面圖。 第6圖係表本發明之實施形態1之D R A Μ之製造方 法的半導體基板的主要部分的斷面圖* 第7圖係表本發明之實施形態1之DRAM之製造方 法的半導體基板的主要部分的斷面圖。、 第8圖係表本發明之實施形態1之D R A Μ之製造方 法的半導體基板的主要部分的斷面圖。 第9圓係表本發明之實施形態1之DRAM之製造方 法的半導體基板的主要部分的斷面圖。/ 本纸張尺度適用中國因家標準{ CNS ) Λ4規洛（2丨0X297公釐） -47- 41286^ 五、發明説明（45 ) 第1 0圖係表本發明之實施形態1之DRAM之製造 方法的半導體基板的主要部分的斷面圖》 第i 1圖係表本發明之實施形態1之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第12圖係表本發明之實施彤態1之DRAM之製造 方法的半導體基板的主要部分的斷面圚* 第1 3圖係表本發明之實施形態1之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第1 4圖係表本發明之實施形態1之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第1 5圖係表本發明之實施形態1之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第1 6圇係表本發明之實施形態1之DRAM之製造 方法的半導髖基板的主要部分的斷面圖》 第1 7圖係表SOG膜的濕蝕刻量與熱處理溫度之相 關性的說明圖。 烀漭部中次枒&quot;局兵工消於合作杜印製 (诗先聞讀背面之注意事项再填寫本頁) 第1 8圖係表本發明之實施形態1之DRAM之製造 方法的半導體基板的主要部分的斷面圖· 第1 9圖係表本發明之實施形態1之DRAM之製造 方法的半導體基板的主要部分的斷面圖* 第2 0圖係表本發明之實施形態1之DRAM之製造 方法的半導體基板的主要部分的斷面圖·I 烀 漭 部 中 次 桠-&quot; Bureau Mh &quot; · Fen Cooperative Press &quot; T i N film with a film thickness of about 50 nm, or, when the C VD method is used, the film thickness is After a W film of about 15 Onm, a photoresist film 41 is used as a mask, and after these W films having a film thickness of about 150 nm, a photoresist film 41 is used as a mask. pattern. That is, in the present embodiment, the silicon nitride film 40 is not deposited on the bit lines BL and the first layer wirings 3 8 * 3 9. (Next, after removing the photoresist film 41, as shown in FIG. 63, a silicon oxide film 81 having a film thickness of about 100 nm is deposited on the bit line BL and the first layer wiring 38 | 39. The silicon oxide film 81 is based on a plasma using, for example, odor (0 3) and TE 0 S as source gases. The HS standard in this paper is applicable to the grade of the HS &lt; ('NS) Λ4 specification (2 丨 0 parent 297 Gong) '-44- «The Ministry of Economic Affairs of the Ministry of Economy and Social Affairs J-Eliminated in the cooperative seal ¾ 412862 at ____B7 V. Description of the invention (42) CVD method and accumulation. That is, this embodiment, the bit line The sidewall of b L and the sidewall of the first 餍 wiring 3 8, 39 are not formed with silicon nitride sidewall spacers. Then, as shown in FIG. 64, the thickness of the spin-coated film on the silicon oxide film 81 is The S 0G film 4 4 is about 300 nm, and then the semiconductor substrate 1 is heat-treated at 800 ° C. for about 1 minute, and the SOG film 44 is sintered. Next, as shown in FIG. 6 and FIG. After the silicon oxide film 45 having a film thickness of about 600 nm is deposited on the SOG film 44, the silicon oxide film 45 is honed by the CMP method to make its surface flat. Oxidation Silicon film 4 5 It is deposited by, for example, a plasma CVD method using ozone (0 3) and TE 0 S as source gases. Next, as shown in FIG. 65, when the thickness of the silicon oxide film 45 is 10, the thickness is 10 After the silicon oxide film 46 at about 0 nm, the insulating film located above the contact hole 29 is removed by dry etching with the photoresist film 47 as a mask to form a through hole 48. The subsequent process It is the same as the above Embodiment 1. As in this embodiment, when a silicon nitride film 40 is not formed on the bit line BL and a sidewall spacer of silicon nitride is not formed on the sidewall, it cannot be aligned with the bit. The element line BL forms a self-integrated p-hole 48. Therefore, in order to reliably prevent a short-circuit between the plug buried in the through hole 48 and the bit line BL in the following process, it is necessary to Reduce the diameter of the through hole 48 or the width of the bit line BL. According to this embodiment, it is the same as the above embodiment 1. | Without making * * This paper size is applicable to Chinese storehouses (CNS) ) Λ4 specifications (210X297 mm) {Jing first read the precautions on the back before filling in this page) Order -45- 412SQ2 5 Description of the Invention (43) In the case where the characteristics of the M ISFETs constituting the memory cell and the peripheral circuit are deteriorated, in addition to improving the gap filling property of the minute gaps between the bit lines BL, the bit lines BL and the The insulating film on the upper layers of the single-layer wirings 3 8 and 3 9 is flat. Furthermore, it is possible to reliably prevent the plug 49 embedded in the through hole 48 from being short-circuited with the bit line BL. As mentioned above, although the invention proposed by the present inventors was specifically explained based on the embodiment of the invention, the invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Although Embodiments 1 to 6 are described in the case of applying to the manufacturing process of DRAM, the present invention is not limited to a memory LSI or a logic LSI, and it can be widely applied to a microchip having a general basis. The manufacturing process of the high-integration LSI with electrode wiring formed at intervals. The present invention can also be applied to an LSI or the like in which a logic circuit and a DRAM are mixed. (Effects of the invention) In the case of the Ministry of Waterlogging, the ί? Bureau Η Η Consumer Cooperative Co., Ltd. published the invention disclosed in this case. If the effect obtained by the representative example is simply explained, it is as follows. The invention makes it possible to flatten the insulating film on the upper part of the electrode wiring formed at fine intervals without deteriorating the characteristics of the M ISFET. According to the present invention, the number of openings in the insulating film can be reduced. The aspect ratio of the connection hole, therefore, can improve the connection reliability of the wiring. Reliability and reduce contact • η (, This paper size is applicable to China's family rate ((, NS) Λ4M (210X297 mm) -46- A7412862 _ ~ W62 _B7____ V. Description of the invention (M) &quot; Hole resistance "(锖 M read the note on the back first &quot; item 苒 Fill this page &gt; According to the present invention, it is possible to prevent the formation of i After the connection, the connection aperture is enlarged due to the wet etching, so that short circuit of the wiring can be prevented and parasitic capacitance can be reduced. Figure 1 illustrates the entire semiconductor substrate on which the DRAM according to the first embodiment of the present invention has been formed. Plan view. Fig. 2 is an equivalent circuit diagram of DRA M in Embodiment 1 of the present invention. Fig. 3 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a DRAM according to Embodiment 1 of the present invention. Fig. 4 Fig. 5 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a DRAM according to the first embodiment of the present invention. ^ Fig. 5 is a cross-sectional view of a main part of a semiconductor substrate showing a method for producing DRA M according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view of a main part of a semiconductor substrate showing a manufacturing method of the DRA M according to the first embodiment of the present invention * FIG. 7 is a semiconductor substrate showing a manufacturing method of the DRAM according to the first embodiment of the present invention Sectional view of the main part. FIG. 8 is a cross-sectional view of a main part of a semiconductor substrate for manufacturing the DRA M of the first embodiment of the present invention. A ninth circle is a DRAM of the first embodiment of the present invention. A cross-sectional view of the main part of a semiconductor substrate manufactured by the manufacturing method./ This paper size is in accordance with Chinese standards {CNS) Λ4 gauge Luo (2 丨 0X297 mm) -47- 41286 ^ V. Description of the invention (45) 1 0 chart series Cross-sectional view of a main part of a semiconductor substrate of a method for manufacturing a DRAM according to the first embodiment of the invention "Fig. I 1 is a cross-sectional view of a main part of a semiconductor substrate of the method for manufacturing a DRAM according to the first embodiment of the present invention. 12 is a cross-section of a main part of a semiconductor substrate showing a method for manufacturing a DRAM according to Embodiment 1 of the present invention. * FIG. 13 is a main part of a semiconductor substrate showing a method for manufacturing a DRAM according to Embodiment 1 of the present invention. Fig. 14 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a DRAM according to the first embodiment of the present invention. Fig. 15 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a DRAM according to the first embodiment of the present invention. No. 16 is a cross-sectional view of a main part of a semiconductor hip substrate of the DRAM manufacturing method according to the first embodiment of the present invention. FIG. 17 is a diagram showing the correlation between the wet etching amount of SOG film and the heat treatment temperature. Illustration.烀 漭 部 中 次 桠 &quot; The Bureau ’s military industry eliminated in cooperation Du printed (Notes on the back of the poem before reading this page and then fill out this page) Figure 18 shows the semiconductor of the DRAM manufacturing method according to the first embodiment of the present invention Cross-sectional view of the main part of the substrate. Fig. 19 is a cross-sectional view of the main part of the semiconductor substrate for the method of manufacturing the DRAM according to the first embodiment of the present invention. Fig. 20 is a cross-sectional view of the first embodiment of the present invention. Cross-sectional view of a main part of a semiconductor substrate for a DRAM manufacturing method ·

第2 1圖係表本發明之實施形態1之DRAM之製造 方法的半導體基板的主要部分的斷面圖V v 4 . 本紙張尺度適用中國S家揉準（rNS&gt;A4规格（2丨0x297公釐） • 48 - U2862 A7 B7 妗系部中决枒準局兵工消介合作社印54 五、發明説明（46 ) 、· 1 1 第2 2圖係表本發明之實施形態1 之 D R A M 之製 造 1 1 I 方法的半導體基板的主要部分的斷面圖 〇 1 I 第》3圖係表本發明之實施形態1 之 D R A M 之製 造 请 先 1 方法的半導體基板的主要部分的斷面圖 0 Μ 背 1 第2 4圖係表本發明之實施形態1 之 D R A M 之製 造 面 之 si 1 方法的半導體基板的主要部分的斷面圖 〇 ίΛ. 意 事 1 1 I 第2 5圖係表本發明之實施形態1 之 D R A M 之製 造 項 再 % 1 1 方法的半導體基板的主要部分的斷面圖 〇 % 本 頁 1 第2 6圖係表本發明之實施形態1 之 D R A M 之製 造 1 I 方法的半導體基板的主要部分的斷面圖 0 1 1 I 第2 7圖係表本發明之實施形態1 之 D R A M 之製 造 1 1 訂 1 方法的半導體基板的主要部分的斷面圖 0 第2 8圖係表本發明之實施形態1 之 D R A M 之製 造 I | 方法的半導體基板的主要部分的斷面圖 〇 1 I 第2 9圖係表本發明之實施形態1 之 D R A M 之製 造 1 1 tM 方法的半導體基板的主要部分的斷面圖 0 1 第3 0圖係表本發明之實施形態1 之 D R A M 之製 造 i 1 方法的半導體基板的主要部分的斷面圖 〇 1 I 第3 1圖係表本發明之實施形態1 之 D R A M 之製 造 I I 方法的半導體基板的主要部分的斷面圚 e 1 第3 2圖係表本發明之實施形態1 之 D R A M 之製 造 1 1 方法的半導體基板的主要部分的斷面圖 9 1. 第3 3圖係表本發明之實施形態1 之 D R A M 之製 造 1 1 方法的半導體基板的主要部分的斷面圈 〇 ' 1 1 本紙張尺度適州中國g家標率（CNS )Λ4規格（210X297公釐） -49- 412862 A7 B7 对/•却f'^fi·局兵Η消於合作社印繁 五、發明说明（47 )&quot; 1 J 第3 4圖係表本發明之實施形態1 之 D R A M 之製 造 1 1 方法的半導體基板的主要部分的斷面圖 〇 1 1 第b 5圖係表本發明之實施形態1 之 D R A M 之製 造 -¾ £ 1 I 方法的半導體基板的主要部分的斷面圖 0 聞 δ A 1 第3 6圖係表本發明之實施形態1 之 D R A M 之製 造 Ήι 面 之 1 1 方法的半導體基板的主要部分的斷面圖 〇 注 意 事 1 1 第3 7圖係表本發明之實施形態1 之 D R A M 之製 造 項 填 1 1 方法的半導體基板的主要部分的斷面圖 0 % 本 頁 •. · I 第3 8圖係表本發明之實施形態1 之 D R A M 之製 造 1 | 方法的半導體基板的主要部分的斷面圖 e 1 1 I 第3 9圖係表本發明之實施形態1 之 D R A M 之製 造 1 1 訂 1 方法的半導體基板的主要部分的斷面圖 0 第4 0圖係表本發明之實施形態1 之 D R A M 之製 造 1 1 方法的半導體基板的主要部分的斷面圖 〇 1 I 第4 1圖係表本發明之實施形態1 之 D R A M 之製 造 1 1 方法的半導體基扳的主要部分的斷面圖 〇 1 第4 2圖係表本發明之實施形態1 之 D R A M 之製 造 1 1 方法的半導體基板的主要部分的斷面圖 0 1 I 第4 3圖係表本發明之實施形態1 之 D R A M 之製 造 1 I 方法的半導體基板的主要部分的斷面圖 0 1 | 第4 4圖係表本發明之實施形態1 之 D R A M 之製 造 1 t 方法的半導體基板的主要部分的斷面圖 〇 1 第4 5圖係表本發明之實施形態2 之 D R A M 之製造 1 1 方法的举導體基板的主要部分的斷面圖 〇 • 1 1 本紙張尺度讁用中國S家揉準（CNS ) Λ4规格（210X297公漦&gt; -50- 紂沪部中决榡準局消於合竹社印裝 412862 a? _ B7___ 五、發明説明（48 )&quot; 第4 6圖係表本發明之實施形態2之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第4 7圔係表本發明之實施形態2之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第4 8圖係表本發明之實施形態2之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第4 9圚係表本發明之實施形態3之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第5 0圔係表本發明之實施形態3之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第51圖係表本發明之實施形態3之DRAM之製造 方法的半導體基板的主要部分的斷面圖》 第5 2圇係表本發明之實施形態3之DRAM之製造 方法的半導體基板的主要部分的斷面圖· 第5 3圖係表本發明之實施形態3之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第5 4圖係表本發明之實施形態4之DRAM之製造 方法的半導體基板的主要部分的斷面圖· 第5 5圖係表本發明之實施形態4之DRAM之製造 方法的半導體基板的主要部分的斷面圖》 第5 6圖係表本發明之實施形態4之DRAM之製造 方法的半導體基板的主要部分的斷面圖。FIG. 21 is a cross-sectional view of a main part of a semiconductor substrate V v 4 showing a method for manufacturing a DRAM according to the first embodiment of the present invention. This paper size is applicable to China ’s standard (rNS &gt; A4 specification (2 丨 0x297) (Central) • 48-U2862 A7 B7 Department of the Ministry of Justice, quasi-station ordnance industry consumer cooperatives 54. Description of the invention (46), · 1 1 Figure 2 2 shows the manufacture of DRAM according to the first embodiment of the present invention 1 1 Cross-sectional view of the main part of the semiconductor substrate of the I method. The first and third drawings show the cross-sectional view of the main part of the semiconductor substrate of the first method. 1 FIG. 2 4 is a cross-sectional view of a main part of a semiconductor substrate according to the si 1 method of the manufacturing surface of the DRAM according to the first embodiment of the present invention. Section 1 of the manufacturing method of the DRAM of the aspect 1 is a cross-sectional view of the main part of the semiconductor substrate of the method 1% 0% of this page 1 is a diagram showing the manufacturing method of the DRAM 1 of the embodiment 1 of the present invention Sectional view of the main part of the board 0 1 1 I FIG. 2 7 is a cross-sectional view of a main part of a semiconductor substrate according to Embodiment 1 of the present invention 1 1 order 1 method. Cross-sectional view of the main part of a semiconductor substrate for manufacturing I | method of the first embodiment of the present invention. 01 I Figures 2 to 9 show the semiconductor substrate of the 1st tM method for manufacturing the DRAM according to the first embodiment of the present invention. Cross-sectional view of the main part 0 1 to 30 are cross-sectional views of the main part of the semiconductor substrate for manufacturing the i 1 method of the DRAM according to the first embodiment of the present invention. 0 1 I FIG. 31 shows the implementation of the present invention. Section 1 of the main part of the semiconductor substrate of the DRAM manufacturing method II in the form 1 圚 e 1 Figure 3 2 shows a section of the main part of the semiconductor substrate of the manufacturing method 1 of the DRAM 1 of the present invention 1 1 method 1. Fig. 3 and Fig. 3 are cross-sections of a main part of a semiconductor substrate of the method 1 for manufacturing a DRAM according to the first embodiment of the present invention. 1 1 This paper is scaled to China ’s national standard rate (CNS) Λ4 specifications (210X297 mm) -49- 412862 A7 B7 Yes / • but f '^ fi · Bao Bing disappeared in the cooperatives. 47) &1; 1 J FIG. 3 4 is a cross-sectional view of a main part of a semiconductor substrate in a method 1 for manufacturing a DRAM according to Embodiment 1 of the present invention. 0 1 1 FIG. 5 is a diagram showing Embodiment 1 of the present invention. Cross-sectional view of the main part of a semiconductor substrate manufactured by the ¾ £ 1 I method 0 δ A 1 Figures 3 and 6 show the semiconductor substrate of the 1-1 manufacturing method of the DRAM according to the first embodiment of the present invention Sectional view of the main part of 〇 Note 1 1 3 7 is a cross-sectional view of the main part of a semiconductor substrate filled with a 1 1 method of manufacturing a DRAM according to Embodiment 1 of the present invention 0% This page •. · · I FIG. 8 is a cross-sectional view of a main part of a semiconductor substrate for manufacturing method 1 of the first embodiment of the present invention e 1 1 I FIG. 3 9 is a chart for manufacturing a DRAM according to the first embodiment of the present invention 1 1 Cross-sectional view of the main part of a semiconductor substrate according to the method 1 0 0 4 0 is a cross-sectional view of the main part of the semiconductor substrate 1 according to the first embodiment of the present invention. 1 1 Section 4 1 The figure is a cross-sectional view of a main part of a semiconductor substrate according to the method 1 for manufacturing the DRAM of the first embodiment of the present invention. Figure 4 2 is a diagram showing the semiconductor for the 1 method of manufacturing the DRAM according to the first embodiment of the present invention. Sectional view of the main part of the substrate 0 1 I FIG. 4 3 is a cross-sectional view of the main part of the semiconductor substrate 1 1 method of manufacturing the DRAM according to the first embodiment of the present invention 0 1 | FIG. 4 4 is a table Cross-sectional view of a main part of a semiconductor substrate of a 1 t method for manufacturing a DRAM according to Embodiment 1 of the present invention. Figures 4 to 5 show the main part of a conductive substrate for a 1 1 method of manufacturing a DRAM according to Embodiment 2 of the present invention. Cross section 〇 • 1 1 The size of this paper is based on the Chinese standard (CNS) Λ4 size (210X297) 漦 -50- The Ministry of Economy and Technology Printed by Yuzhusha Co., Ltd. 412862 a? _ B7___ 5. Description of the Invention (48) &quot; Figures 4 and 6 are cross-sectional views of the main parts of a semiconductor substrate showing a method of manufacturing a DRAM according to a second embodiment of the present invention. Section 47 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a DRAM according to the second embodiment of the present invention. Figures 4 to 8 are cross-sectional views of main parts of a semiconductor substrate showing a method of manufacturing a DRAM according to a second embodiment of the present invention. Section 49 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a DRAM according to the third embodiment of the present invention. 50th is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a DRAM according to the third embodiment of the present invention. Fig. 51 is a sectional view of a main part of a semiconductor substrate showing a method for manufacturing a DRAM according to a third embodiment of the present invention "Fig. 51 is a main part of a semiconductor substrate showing a method for manufacturing a DRAM according to a third embodiment of the present invention; Fig. 53 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a DRAM according to a third embodiment of the present invention. Fig. 54 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a DRAM according to a fourth embodiment of the present invention. Fig. 55 is a diagram showing a main part of a semiconductor substrate of the method for manufacturing a DRAM according to the fourth embodiment of the present invention. Partial Cross-Section Views "Figures 5 to 6 are cross-sectional views of main parts of a semiconductor substrate showing a method of manufacturing a DRAM according to a fourth embodiment of the present invention.

第5 7圖係表本發明之實施形態4之DRAM之製造 方法的半導體基板的主要部分的斷面圖V 本紙張尺度適州中國囷家標华{ (，NS ) Λ4^ (2iOX297公釐） t銪先聞讀背面之注意事項再填寫本頁) 訂 - •51 - 412862 A7 ___B7_ 五、發明説明（49 ) 第5 8圖係表本發明之實施形態5之DRAM之製造 方法的半導體基板的主要部分的斷面圖》 第5 9圖係表本發明之實施形態5之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第6 0圖係表本發明之實施形態5之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第6 1圖係表本發明之實施形態5之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第6 2圖係表本發明之實施形態6之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第6 3圖係表本發明之實施形態6之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第6 4圖係表本發明之實施形態6之DRAM之製造 方法的半導體基板的主要部分的斷面圖。 第6 5圖係表本發明之實施形態6之DRAM之製造 方法的半導體基板的主要部分的斷面圖》 衧济部中次標卑扃貝工消於合竹社印奴 (請先Μ讀背面之注意事項再填寫本頁) 第6 6圖係表本發明之實施形態6之DRAM之製造 方法的半導體基板的主要部分的斷面圖· 符號說明 ， 1 半導體基板 1 A 半導體晶片 2 氧化矽膜 3 氮化矽膜 , 本紙張尺度適州中國囷家標準（CNS Μ4規格（210X297公藶） -52- U2S62 ^ 五、發明説明（5Q ) 4 光阻膜 5 元 件分離溝 5 a 溝 6 氧 化矽膜 7 氧 化矽膜 8 氮 化矽膜 9 光 阻膜 1 0 η 型半導體領域 1 1 Ρ 型阱 1 2 η 型阱 1 3 閘 氧化膜 1 4 Α〜 1 4 c 閛極 1 5 氮化矽膜 1 6 光阻膜 1 7 P _型半導體領域 1 8 η _型半導體領域 1 9 η型半導體領域 2 0 氮化矽膜 2 0 a 側壁間隔層 2 1 光阻膜 2 2 Ρ +型半導體領域 2 3 η +型半導體領域 2 4 S 0 G膜 2 4 a ，- 2 4b S 0 G 膜 {婧先閱讀背面之注意事項再填寫本頁) 訂 -合 丨* 本紙張尺度ϋ用中国囤家揉啤（（:NS &gt; Α4Ϊ11格（210X297公着） -53- 时滴部中央桴ίί-局oiJr.消赘合竹=f.t印欠 A7 _412R(\9,_b7_ 五、發明説明（）v 51 2 5 氧化矽膜 2 6 氧化矽膜 2 7 光阻膜 2 8 接觸孔 2 9 接觸孔 3 0 插塞 31 氧化矽膜 3 2 光阻膜 3 3 光阻膜 34〜37 接觸孔 38，39 第1層配線 40 氮化矽膜 4 1 光阻膜 4 2 T i S i 2 層 4 3 側壁間隔層 4 4 S ◦ G 膜 45 氧化矽膜 4 6 氧化砂膜 4 7 光阻膜 4 8 通孔 ， 4 9 插塞 51 氮化矽膜 5 2 光阻膜 5 3 氧化矽膜 本紙张尺度进用中國囷家標嘩（CNS ) ΑΊ规格（210X297公羞） (銪先聞讀背面之注意事項再填寫本S ) 訂 -54- ίίΜ部中决榡準局CICJ.消合作社印努 412862 ^五、發明説明（52 )：' 5 4 光阻膜 5 5 溝 5 5 a 溝 56 多晶矽膜 5 7 S 0 G 膜 5 8 光阻膜 60 下部電極 61 TazOs 膜 6 2 TiN膜（上部電極） 6 3 光阻膜 64 氧化矽膜 6 5 光阻膜 6 6 通孔 6 7 插塞 68，69 第2層配線 71 氧化矽膜 7 2 S 0 G 膜 73 氧化矽膜 74*75 通孔 7 6 插塞 77〜79 第3層配線 80 氧化矽膜 81 氧化矽膜 B L —位元線 (餚先閲讀背面之注意事項再填寫本頁) 訂 -ί6! 本纸张尺度埯用中囷囤家標卒（「阳）六4現格（2丨0&gt;&lt;297公漦） -55- 好浇部中^標-l-^pJ.消合竹il印^ A7 _4128R2 B7 五、發明説明（„ ) 9 0〇 C 資 料儲 存 用 電 容 元 件 Μ A R Y 記憶體 陣 列 Q η η 通道 型 Μ. I S F Ε 丁 Q Ρ Ρ 通道 型 Μ I S F Ε Τ Q S 記憶格 選 擇 Μ I S F Ε Τ S A 感 測放 大 器 W D 元驅 動 器 (銪先聞讀背面之注意事項再填寫本頁)Figures 5 and 7 are cross-sectional views of a main part of a semiconductor substrate showing a manufacturing method of a DRAM according to the fourth embodiment of the present invention. V Paper size Shizhou China Jiajia Biaohua {(, NS) Λ4 ^ (2iOX297 mm) t 铕 read the precautions on the back before filling this page) Order-• 51-412862 A7 ___B7_ V. Description of the Invention (49) Figures 5 and 8 show the semiconductor substrate of the DRAM manufacturing method according to the fifth embodiment of the present invention. Sectional View of Main Part "Figs. 5 to 9 are cross-sectional views of main parts of a semiconductor substrate showing a method for manufacturing a DRAM according to a fifth embodiment of the present invention. Fig. 60 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a DRAM according to a fifth embodiment of the present invention. Fig. 61 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a DRAM according to a fifth embodiment of the present invention. Fig. 62 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a DRAM according to a sixth embodiment of the present invention. Fig. 63 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a DRAM according to a sixth embodiment of the present invention. Fig. 64 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a DRAM according to a sixth embodiment of the present invention. Fig. 65 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a DRAM according to a sixth embodiment of the present invention. " (Notes on the back of the page, please fill in this page) Figures 6 and 6 are cross-sectional views of the main parts of the semiconductor substrate of the DRAM manufacturing method according to the sixth embodiment of the present invention. Symbol description, 1 semiconductor substrate 1 A semiconductor wafer 2 silicon oxide Film 3 Silicon Nitride film, this paper is in accordance with China's standard of CNS M4 (210X297 cm) -52- U2S62 ^ V. Description of the invention (5Q) 4 Photoresist film 5 Element separation groove 5 a groove 6 oxidation Silicon film 7 Silicon oxide film 8 Silicon nitride film 9 Photoresist film 1 0 η-type semiconductor field 1 1 P-type well 1 2 η-type well 1 3 Gate oxide film 1 4 Α ~ 1 4 c 閛 pole 1 5 Silicon nitride Film 1 6 Photoresistive film 1 7 P _type semiconductor field 1 8 η _type semiconductor field 1 9 η type semiconductor field 2 0 Silicon nitride film 2 0 a sidewall spacer 2 1 photoresist film 2 2 P + type semiconductor field 2 3 η + type semiconductor field 2 4 S 0 G film 2 4 a,- 2 4b S 0 G film {Jing first read the precautions on the back and then fill out this page) Order-Combination 丨 * This paper size uses Chinese kneading beer ((: NS &gt; Α4Ϊ11 grid (210X297)) -53- The central part of the time-division department 桴 ί- bureau oiJr. Elimination of superfluous bamboo = ft 印 ow A7 _412R (\ 9, _b7_ V. Description of the invention () v 51 2 5 Silicon oxide film 2 6 Silicon oxide film 2 7 Photoresist film 2 8 Contact hole 2 9 Contact hole 3 0 Plug 31 Silicon oxide film 3 2 Photoresist film 3 3 Photoresist film 34 ~ 37 Contact holes 38, 39 First layer wiring 40 Silicon nitride film 4 1 Photoresist film 4 2 T i S i 2 layer 4 3 sidewall spacer 4 4 S ◦ G film 45 silicon oxide film 4 6 sand oxide film 4 7 photoresist film 4 8 through hole, 4 9 plug 51 silicon nitride film 5 2 photoresist film 5 3 The silicon oxide film used in this paper is in the Chinese standard (CNS) ΑΊ size (210X297). (Please read the precautions on the back before filling in this S) Order-54- ί Department of the Ministry of Justice, CICJ. Consumer Cooperatives Innu 412862 ^ V. Description of the invention (52): '5 4 photoresist film 5 5 groove 5 5 a groove 56 polycrystalline silicon film 5 7 S 0 G film 5 8 photoresist film 60 lower electrode 61 TazOs film 6 2 TiN Membrane (upper electrode) 6 3 Photoresist film 64 Silicon oxide film 6 5 Photoresist film 6 6 Through hole 6 7 Plug 68, 69 Layer 2 wiring 71 Silicon oxide film 7 2 S 0 G film 73 Silicon oxide film 74 * 75 Through hole 7 6 Plug 77 ~ 79 Layer 3 Wiring 80 Silicon Oxide Film 81 Silicon Oxide Film BL—Bit Line (Read the precautions on the back first and then fill out this page) Order-6! This paper is a standard paper that is used in China. ("Yang" 6) 4 grids (2 丨 0 &gt; &lt; 297gong) -55- In the good pouring department ^ standard -l- ^ pJ. Fusion bamboo il seal ^ A7 _4128R2 B7 V. Description of the invention („) 9 00C Capacitive element for data storage MY ARY Memory array Q η η Channel type M. ISF Ε 丁 Q Ρ Ρ Channel type Μ ISF Ε Τ QS Memory cell selection Μ ISF Ε SA Sensor amplifier WD element driver (铕(Read the notes on the back before filling out this page)

T 本紙張尺度诮州中國國家栋辛&lt; CNS &gt;A4規格（210X297公簷） -56-T paper size Luzhou China National Dongxin &lt; CNS &gt; A4 specification (210X297 male eaves) -56-

Claims (1)

412862412862 煩請委員明示，本衆妗正饺是否^更原實質内&quot;經濟部中央標準局员工消費合作社印製 六、申請專利範圍 第87109184號專利申請案 中文申請專利範圍修正本 民國88年2月修正 1 ·—種半導體積體電路^置之製造方法，包含具有 配置在沿著半導體基板之主面的第1方向而延伸存在的多 個字元線與沿著第2方向而延伸存在的多個位元線的交點 ，包含一具有由備有與上述字元線一體被形成的閘極的記 憶格選擇用Μ I S F E T、與串聯於此之資料儲存用電容 元件所構成之記憶格的D RAM，其特徵在於具備： (a) 當在半導體基板的主面上堆積第1導電膜後 ，對上述第1導電膜實施圖案，而形成成爲記億格選擇用 Μ I S F E T之閘極的字元線的過程及； (b ) 在以SOG膜來被覆上述字元線之間後，對 上述S ◦ G膜實施熱處理的過程。 2 .如申請專利範圍第1項之半導體積體電路裝置之 製造方法，上述S ◦ G膜的被覆與熱處理乃分別分成多次 的過程來進行。 3.如申請專利範圍第1項半導體積體電路裝置之製 造方法，在上述過程（b )之後，在上述SOG膜的上述 堆積第1氧化矽膜，藉著至少以CMP法對上述第1氧化 矽膜實施硏磨|而使其表面變爲平坦。 4 .如申請專利範圍第3項半導體積體電路裝置之製 造方法，在上述字元配線.的上部形成氮化矽膜，在以 CMP法對上述第1氧化矽膜.以及S 0 G膜實施硏磨之際 本紙張尺度逋用中國國家揉準（CNS ) A4规格（210X297公釐） (請先Μ讀背面之注^h項再填寫本頁) 經濟部中央標準局員工消費合作社印装 412862 § _ D8 六、申請專利範圍 ’將上述氮化矽膜當作阻蝕膜來使用。 5 .如申請專利範圍第3項之半導體積體電路裝置之 製造方法，在以上述CMP法而硏磨的上述第1氧化矽膜 的上部堆積第2氧化矽膜。 6 ·如申請專利範圍第1項之半導體積體電路裝置之 製造方法，藉著以CMP法來硏磨S 0G膜，而使其表面 變得平坦。 7 ·如申請專利範圍第6項之半導體積體電路裝置之 製造方法，·在上述電極配線的上部形成氮化矽膜，在以 CMP法來硏磨上述s 0G膜之際，將上述氮化矽膜當作 阻蝕膜來使用。 8 .如申請專利範圍第6項之半導體積體電路裝置之製 造方法，在以上述CMP法所硏磨過的上述S 0 G膜的上 部堆積第1氧化矽膜。 9 .如申請專利範圍第1項之半導體積體電路裝置之 製造方法，上述第1導電膜至少包含金屬膜。 1 0 .如申請專利範圍第9項之半導體積體電路裝置 之製造方法，上述第1導電膜係由多晶矽膜，由堆積在其 上部的WN膜或T i N膜所形成的障壁層，以及堆積在其 上部的W膜所形成。 1 1 .如申請專利範圍第1項之半導體積體電路裝置 之製造方法，上述SOG膜的熱處理條件爲800 °C，1 分鐘左右。 . 12.如申請專利範圍第1項之半導體積體電路裝置 1· ^^^1 Jy nn m· .•urns' (請先M讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家橾準（CNS ) A4規格（210X297公釐） -2- D8 412862 六、申請專利範圍 之製造方法，上述互相鄰接之上述字元線彼此的間隔爲由 光石印之解析極限所決定的最小尺寸左右 1 3 如申請專利範圍第3項之半導體積體電路裝置 之製造方法，以來源氣體利用臭氧與T E 0 S的電漿 C VD法來堆積上述第1氧化矽膜。 14.如申請專利範圍第1項至第13項之任一項之 半導體積體電路裝置之製造方法，在包含上述字元線之上 部的上述S 0 G膜的絕緣膜上，實施乾蝕刻而形成連 後’利用包含氟酸的洗淨液來淸洗上述連接孔的內部。 /1 5 _ —種半導體積體電路裝置之製造方法，主要係 包含一被配置在沿著半導體基板之主面的第1方向而延伸 存在的多個字元線與沿著第2方向而延伸存在的多個位元 線的交點上，而與上述字元線形成一體的閘極的記憶格選 擇用Μ I S F E T、以及串聯於此之資料儲存用電容元件 所構成之具有記憶格的D R AM的半導體積體電路裝置之 製造方法，其特徵在於包含： 經濟部中央標準局負工消費舍作社印繁 (a ) 在半導體基板的主面形成記憶格選擇用 MISFET的過程； (b ) 當在上述記憶格選擇用MI S.FET的上部 堆積第1絕緣膜後，對上述第1絕緣膜實施開孔，在上述 記憶格選擇用Μ I S F E T之源極，汲極之其中一個的上 部形成第1接觸孔，而在另一個的上部形成第2接觸孔的 過程； . (c ) 當在上述第1絕緣膜的上部堆積第1導電膜 -3 - 本紙張尺度適用中國國家榡準（CNS ) Α4规格（210X297公釐） 經濟部中夫椹牵局貝工消费合作杜印*. 412862 S .&gt;__DS__六、申請專利範圍 後·藉著對上述第1導電膜資施圓案•形成經由上^第1 接觸孔在電氣上與上述記憶格選擇用Μ I S F E T之源極 *汲極的其中一個連接的位元線的過程及； (d) 在以SO G膜來被覆上述位元線之間後，對 上述SOG膜實施熱處理· 1 6 .如申請專利範面第15項之半導體積體電路裝置 之製造方法，上述第一導電膜由Ti (鈦）膜，於其上部堆 積而成的氮化鈦膜、及於其上部堆稹而成的鎢膜所形成· 17 ·如申請專利範圔第1 5項之半導體稹體電路裝 置之製造方法，藉著對上述第1導電膜實施圖案，可以同 時形成上述位元線與周邊電路的第1層配線· 1 8 . —種半導髖稹體電路裝匿之製造方法，其主要 係一具有多個由第1MISFET與串聯連接於此之資# 儲存用霣容元件所構成的記億格的記億餿陣列以及由多偭第 2M I S F E T所構成之周邊電路的半導體積體電路裝置 ::之製造方法，其特徴在於包含： (a) 在半導體基板上形成第1MISFET的閘 極與第2M I S F ET的Μ極的過程： (b ) 在位於上述第1MISFET之閘極之兩端 的上述半導體基板表面形成用於構成上述第1 MI SFET之源極，汲棰的第1半導髖領域*而在位於 上述第2MI SFET之閘極之兩端的上述半導饈基板表 面形成用於構成上述第2. MI SFET之源極，汲極的第 2半導k領域的過程： :-1,1-------------ΪΓ------,ίι (谛先《讀背面之注*事項Κ寫本貫) 本紙張尺度遑角中繭家«準t CNS &gt; ( 21?Χ297公簸） 412862 A8 BS C8 DS 六、申請專利範圍 . 1' (c) 如覆蓋上述第1 ，第2MI SFET般地形 成第1絕緣膜的過程； (婧先閲讀背面之注^K項再填寫本頁) (d) 在上述第1絕緣膜形成可讓上述第1 MI SFET之上述第1半導體領域露出的第1開孔的過 程； (e) 在上述第1開孔選擇性地形成多晶矽膜的過 程； (ί ) 在上述多晶矽膜上形成第2絕緣膜的過程； (g) 在上述第2絕緣膜形成第2開孔，而讓上述 多晶矽膜露出的過程； (h) 在上述第1、2絕緣膜形成第3開孔，而讓 上述第2M I S F E T之上述第2半導體領域露出的過程 及； (i ) 在上述第2 ，第3開孔內堆積導體層的過程 而使上述第2開孔與上述第3開孔以不同的過程形成 〇 經濟部中央標準局負工消費合作社印製 1 9 . 一種半導體積體電路裝置之製造方法，其主要 係一具有被形成在半導體基板上的第1 Μ I S F Ε Τ的半 導體積體電路裝置之製造方法，其特徵在於： (a) 經由第1絕緣膜在半導體基板上形成成爲第 1ΜΪ SFET之閘極的第1導體層的過程； (b ) 在位於上述.第1導電膜之兩端的上述半導體 基板表面形成可當作上述第1MISFET之源極，汲極 -5- 本紙張尺度逋用中國困家梯率（CNS ) A4规格（210X297公釐） 412862 8 888 ABCD 申請專利範圍 來使用之第1以及第2半導體領域的過程； (c ) 如覆蓋上述第1MI SFET般地塗佈第2 絕緣膜，而對上述第2絕緣膜實施熱處理的過程； (d) 在上述第1絕緣膜形成可讓上述第1 MI SFET的第1半導體領域露出的第1開口以及可讓 上述第2半導體領域露出的第2開口的過程及： (e ) 在上述第1以及第2開口形成第2導體層的 過程。 2 0 .如申請專利範圍第1 9項之半導體積體電路裝 置之製造方法，在上述過程（d )與（e )之間更具有（ 歲離3 口的過程。 (請先W讀背面之注項再填寫本頁) 經濟部中央榇隼局員工消費合作社印製 f)以氟酸來淸洗上述第1以及 2 1 ·如申請專利範圍第] 之製造方法，在上述過程（c)與\_ )之間更具有（g )以機械地以及化學地來硏磨上述第2絕緣膜的過程。 2 2 .如申請專利範圍第1 9項之半導體積體電路裝 置之製造方法，在上述過程（c )與（d )之間更具有（ h )在上述第2絕緣膜上堆積第3絕緣膜，而以機械地以 及化學地來硏磨上述第3絕緣膜的過程= 2 3 . —種半導體積體電路裝置之製造方法，其主要 係一具有被形成在半導體基板上的第1MI SFET的半 導體積體電路裝置之製造方法，其特徵在於： (a) 經由第1絕緣膜在半導體基板上形成成爲第 1MI SFET之閘極的第1導體層的過程： (b) 在位於上述第1導電膜之兩端的上述半導體 導體積體電路裝置 本紙張尺度遄用中國國家#準（CNS &gt; A4规格（210X297公釐） -6 - 412862 B8 C8 D8 六、申請專利範圍 基板表面形成可當作上述第1 Μ I S F E T之源極，汲極 來使用之第1以及第2半導體領域的過程； (c ) 如覆蓋上述第1ΜΙ SFET般地塗佈第2 絕緣膜，而對上述第2絕緣膜實施熱處理的過程； (d ) 在上述第1絕緣膜形成可讓上述第1 MI SFET的第1半導體領域露出的第1開口的過程； (e ) 在上述第1開口形成第2導體層的過程； (f ) 在上述第2導體層上形成第3絕緣膜的過程 (S ) 在上述第3絕緣膜上形成第3導體層的過程 1 (h ) 在上述第3導體層上塗佈第4絕緣膜，而對 上述第4絕緣膜實施第2熱處理的過程： (i ) 在上述第4絕緣膜形成第2開口，可讓上述 第3導體層的一部分露出的過程；及 (J ) 在上述第2開口內形成第4導體層的過程； 而上述第1熱處理溫度較上述第2熱處理溫度爲高= 2 4 如申請專利範圍第2 3項之半導體積體電路裝 置之製造方法，上述第3以及第4導體層則堆積鋁層。 2 5 .如申請專利範圍第2 3項之半導體積體電路裝 置之製造方法，在上述過程（d )與（e )之間更具有（ k )以氟酸來淸洗上述第1開口之半導體基板表面的過程 〇 ^ 2 6 .如申請專利範圍第.2 3項之半導體積體電路裝 本紙張尺度適用中國國家揉準（CNS ) A4洗格（210X297公釐) ：~~Z --.1.-------:梦------訂 (請先閲讀背面之注f項再填寫本頁) 經濟部中央標率局貝工消費合作社印装 BS 412862 ξ\_ 六、申請專利範圍 置之製造方法，在上述過程（C )與（d )之間更具有（ 1 )以機械地以及化學地來硏磨上述第2絕緣膜的過程。 27 .如申請專利範圍第23項之半導體積體電路裝 置之製造方法，在上述過程（c )與（d )之間更具有（ m)在上述第2絕緣膜上堆積第5絕緣膜，而以機械地以 及化學地來硏磨上述第5絕緣膜的過程。 2 8 .如申請專利範圍第2 3項之半導體積體電路裝 置之製造方法*更具有在上述第3導體層與上述第4絕緣 層之間形成第6絕緣膜，而在上述第4絕緣膜與上述第4 導體膜之間形成第7絕緣膜的過程。 2 9 . —種半導體積體電路裝置之製造方法，主要係 具有於半導體基板上所形成之第1及第2的]VII SFET ，其特徵在於具備： (a ) 於半導體基板上選擇性地形成溝槽之過程； (b) 堆積能夠將上述溝槽覆蓋的膜厚的氧化膜， 於上述溝槽內選擇性地留下上述氧化膜的過程： 經濟部中央梂準局負工消費合作社印裝 (請先閲讀背面之注意事項再填寫本頁) (c) 於上述溝槽所圍繞之半導體基板上，使做爲 第丨及2的MI SFET的閘極之第1導體層互相鄰接形成 的過程； (d ) 於上述第1導電膜上及第1導電膜間形成氮化 矽膜的過程； (e ) 於上述做爲第1及2的MI SFET的閘極之 第1導體層間及第1導體層上，塗敷第1絕緣層，於上述第 1絕緣層上施以熱處理之過程； 本紙張尺度適用中國國家#準（CNS ) A4規格（210X297公釐） -8 - 經濟部中央梯準局員工消费合作社印装 Λ8 B8 C8-：_412 齡 D8---々、申請專利範圍 (f) 於上述做爲第1及2的MISFET的閘極之 第1導體層間，在上述第1絕緣膜及上述氮化矽膜上形成開 口，使上述半導體基板之主面露出之過程； (g) 將半導體基板之主面以含有氟酸之液體淸洗 之過程；以及 C h ) 於上述開口內形成第2導體層之過程， 而上述開口之形成過程包含：在上述第1絕緣膜之蝕刻率 較上述氮化矽膜更大之條件下，進行上述第1絕緣膜之鈾 刻之過程、與在上述氮化矽膜之蝕刻率較上述絕緣膜更大 之條件下，進行上述氮化矽膜之蝕刻之過程。 3 0 . —種半導體積體電路裝置之製造方法，其特徵 在於具備： (a ) 於半導體基板上選擇性地形成溝槽之過程； (b ) 堆積能夠將上述溝槽覆蓋的膜厚的氧化膜， 於上述溝槽內選擇性地留下上述氧化膜的過程； (c) 於上述半導體基板上，使第1及2的導體層互 相鄰接形成的過程； (d ) 於上述第1與第2的導電膜上及第1與第2導 電膜間形成氮化矽膜的過程； (e ) 於上述氮化矽膜上，塗敷第1絕緣層，使第1 與第2導電膜間能被掩蓋，於上述第1絕緣層上施以熱處 理之過程： (f ) 於上述第1與第2導體層間，在上述第1絕緣 層與第1氮化矽膜上，形成開口互相鄰接的第1與第2開 n - ^^1 I 1 - - I * I— I I. 111 ID ^^1 ^^1 n ^^1 (請先wtl背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家梂準（CNS ) A4规格（2丨0&gt;&lt;297公釐） -9 - AS B8 CS D8 經濟部中央揉唪局員工消費合作社印«- 六、申請專利範園 口，而使上述半導體基板之主面露出之過程： (g) 將半導體基板之主面以含有氟酸之液體淸洗 之過程；以及 (h) 於上述第1及第2開口內形成第2導體層之 過程， 而上述第1與第2開口之形成過程包含：在上述第1絕緣 膜之蝕刻率較上述氮化矽膜更大之條件下，進行上述第1 絕緣膜之蝕刻之過程、與在上述氮化矽膜之蝕刻率較上述 氧化膜更大之條件下，進行上述氮化矽膜之蝕刻之過程。 3 1 ·如申請專利範圍第3 0項半導體積體電路裝置 之製造方法，其中上述第1絕緣膜爲SOG膜。 3 2 .如申請專利範圍第3 0項半導體積體電路裝置 之製造方法，其中在上述（e )過程與（f )過程之間， 又有 (i )於上述第1絕緣膜上堆積第2絕緣膜之過程；及 :(j )對上述第2絕緣膜施加硏磨之過程。 3 3 .如申請專利範圍第3 0項半導體積體電路裝置 之製造方法，其中上述氮化矽膜之蝕刻過程爲：如同在上 述第1與第2導體層之側面壁上形成側壁絕緣膜一般的異 方性蝕刻過程。 (请先閲讀背面之注$項再填寫本頁)Members are kindly requested to make clear whether the original dumplings are within the original substance &quot; Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 6. Patent Application No. 87109184. 1 · A method for manufacturing a semiconductor integrated circuit, comprising a plurality of word lines arranged to extend along a first direction along a main surface of a semiconductor substrate and a plurality of word lines arranged to extend along a second direction The intersection of the bit lines includes a D RAM having a memory cell composed of a memory cell selection M ISFET provided with a gate formed integrally with the word line, and a data storage capacitor element connected in series. It is characterized in that: (a) after the first conductive film is deposited on the main surface of the semiconductor substrate, the first conductive film is patterned to form a word line that becomes the gate of the M ISFET for selection of hundreds of grids; Process and; (b) a process of heat-treating the S ◦ G film after covering the word lines with the SOG film. 2. According to the method for manufacturing a semiconductor integrated circuit device according to item 1 of the scope of patent application, the coating and heat treatment of the above-mentioned S ◦ G film are separately divided into multiple processes. 3. According to the method for manufacturing a semiconductor integrated circuit device according to item 1 of the patent application scope, after the above process (b), the first silicon oxide film is deposited on the above-mentioned SOG film, and the above-mentioned first oxidation is performed by at least the CMP method. Honing the silicon film | makes its surface flat. 4. According to the method for manufacturing a semiconductor integrated circuit device according to item 3 of the patent application, a silicon nitride film is formed on the word wiring, and the first silicon oxide film and the S 0 G film are implemented by a CMP method. At the time of honing, the paper size is in Chinese National Standard (CNS) A4 (210X297 mm) (Please read the note on the back ^ h before filling out this page) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 412862 § _ D8 6. Scope of Patent Application 'The above silicon nitride film is used as a resist film. 5. According to the method for manufacturing a semiconductor integrated circuit device according to item 3 of the scope of patent application, a second silicon oxide film is deposited on the first silicon oxide film which has been honed by the CMP method. 6 · As in the method for manufacturing a semiconductor integrated circuit device according to item 1 of the scope of patent application, the surface of the SOG film is flattened by CMP method. 7 · According to the method for manufacturing a semiconductor integrated circuit device according to item 6 of the scope of patent application, · A silicon nitride film is formed on the above electrode wiring, and when the s 0G film is honed by the CMP method, the above-mentioned nitride is formed. The silicon film is used as an etching resist film. 8. According to the method for manufacturing a semiconductor integrated circuit device according to item 6 of the scope of patent application, a first silicon oxide film is deposited on the upper portion of the above-mentioned S 0 G film which has been honed by the CMP method. 9. The method for manufacturing a semiconductor integrated circuit device according to item 1 of the scope of patent application, wherein the first conductive film includes at least a metal film. 10. If the method for manufacturing a semiconductor integrated circuit device according to item 9 of the scope of the patent application, the first conductive film is a barrier layer formed of a polycrystalline silicon film, a WN film or a T i N film deposited on the upper part, and A W film deposited on top of it. 1 1. If the method for manufacturing a semiconductor integrated circuit device according to item 1 of the scope of patent application, the heat treatment conditions of the above-mentioned SOG film are 800 ° C, about 1 minute. 12. If the semiconductor integrated circuit device 1 of the scope of patent application 1 · ^^^ 1 Jy nn m ·. • urns' (please read the precautions on the back before filling this page) This paper uses China National Standard (CNS) A4 (210X297 mm) -2- D8 412862 6. In the manufacturing method in the scope of patent application, the distance between the above-mentioned word lines adjacent to each other is the minimum size determined by the analytical limit of light lithography Left and right 1 3 According to the method of manufacturing a semiconductor integrated circuit device in the third item of the patent application scope, the above-mentioned first silicon oxide film is deposited using a plasma C VD method using ozone and TE 0 S as a source gas. 14. According to the method for manufacturing a semiconductor integrated circuit device according to any one of the scope of claims 1 to 13, the dry etching is performed on the insulating film including the S 0 G film above the word line. After the formation of the connection, the inside of the connection hole was rinsed with a cleaning solution containing hydrofluoric acid. / 1 5 _ —A method for manufacturing a semiconductor integrated circuit device, mainly including a plurality of word lines arranged to extend along a first direction of a main surface of a semiconductor substrate and extending along a second direction At the intersection of a plurality of bit lines, a memory cell selection M ISFET for gates forming an integrated body with the word line and a DR AM with a memory cell formed by a data storage capacitor element connected in series therewith A method for manufacturing a semiconductor integrated circuit device, comprising: (a) a process of forming a memory cell selection MISFET on a main surface of a semiconductor substrate; (b) when After the first insulating film is deposited on the memory cell selection MI S.FET, a hole is formed in the first insulating film, and the first one of the source and drain of the memory cell selection MI ISFET is formed as a first. The process of forming a second contact hole on the top of another contact hole; (c) When the first conductive film is deposited on top of the first insulating film -3-This paper applies to China National Standards (CNS) Α4 Specifications (210X297 mm) Du Fu, China ’s Ministry of Economic Affairs and the Bureau ’s consumer cooperation Du Yin *. 412862 S. &Gt; __ DS__ VI. After applying for a patent scope · By implementing the above-mentioned first conductive film materials • Formation via The first contact hole is electrically connected with the above memory cell to select a bit line connected to one of the source and the drain of the M ISFET, and (d) the SO G film is used to cover the bit line. After a while, the above-mentioned SOG film is subjected to heat treatment. 16. According to the method for manufacturing a semiconductor integrated circuit device according to item 15 of the patent application, the first conductive film is made of a Ti (titanium) film deposited on the upper part. Formed by a titanium nitride film and a tungsten film stacked on top of it · 17 · For example, the method for manufacturing a semiconductor body circuit device according to item 15 of the patent application, by patterning the first conductive film It is possible to form the first layer wiring of the above-mentioned bit line and peripheral circuits at the same time. A method for manufacturing a semiconducting hip carcass circuit, which mainly includes a plurality of first MISFETs connected in series with the first MISFET.资 # Storage of billions of grids composed of capacitive components And a semiconductor integrated circuit device of a peripheral circuit composed of a plurality of 2M ISFETs :: A manufacturing method, which specifically includes: (a) forming a gate of a first MISFET and an M pole of a 2M ISF ET on a semiconductor substrate; Process: (b) forming the first semiconducting hip region for forming the source of the first MI SFET on the surface of the semiconductor substrate at both ends of the gate of the first MISFET, and in the second MI The process of forming the surface of the semiconducting substrate at both ends of the gate of the SFET to form the second semiconducting k region of the source and drain of the second MI SFET:: -1,1 ------ ------- ΪΓ ------, ίι (谛 first "read the note on the back side * item K writes this book) The paper size of the paper cocoon« quasi t CNS &gt; (21? × 297 ) 412862 A8 BS C8 DS 6. Scope of patent application. 1 '(c) The process of forming the first insulation film like covering the first and second MI SFETs above; (Jing first read the note ^ K on the back before filling this page ) (d) forming a first opening in the first insulating film to expose the first semiconductor region of the first MI SFET; (e) in (1) a process of forming a second insulating film on the polycrystalline silicon film; (g) forming a second opening of the second insulating film to allow the polycrystalline silicon film to be formed; Exposure process; (h) forming a third opening in the above-mentioned first and second insulating films, and exposing the second semiconductor area of the above-mentioned 2M ISFET; and (i) in the above-mentioned second and third openings The process of internally stacking the conductor layer makes the second opening and the third opening formed in a different process. Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 19. A method for manufacturing a semiconductor integrated circuit device, It is mainly a method for manufacturing a semiconductor integrated circuit device having a 1 M ISF ET formed on a semiconductor substrate, which is characterized by: (a) forming a gate of a 1 MΪ SFET on a semiconductor substrate via a first insulating film; Process of the first conductor layer of the electrode; (b) forming on the surface of the semiconductor substrate located at both ends of the first conductive film as the source of the first MISFET; Gradient (CNS) A4 specification (210X297 mm) 412862 8 888 ABCD Processes in the first and second semiconductor fields for which patent applications are used; (c) coating the second insulating film as if covering the first MI SFET, And performing a heat treatment process on the second insulating film; (d) forming a first opening in the first insulating film that allows the first semiconductor region of the first MI SFET to be exposed and a first opening that allows the second semiconductor region to be exposed The process of 2 openings and (e) the process of forming a second conductor layer in the first and second openings. 20. If the method for manufacturing a semiconductor integrated circuit device according to item 19 of the scope of patent application, there is a process of (3 years apart) between the above processes (d) and (e). (Please read the back of the first Please fill in this page for the note) Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs f) Washing the above 1 and 2 1 with fluoric acid · The manufacturing method as in the scope of patent application], in the above process (c) and \ _) Further has (g) a process of honing the second insulating film mechanically and chemically. 2 2. If the method for manufacturing a semiconductor integrated circuit device according to item 19 of the scope of patent application, there is (h) a third insulating film deposited on the second insulating film between the processes (c) and (d). The process of honing the third insulating film mechanically and chemically = 2 3. A method for manufacturing a semiconductor integrated circuit device, which is mainly a semiconductor having a first MI SFET formed on a semiconductor substrate A method for manufacturing an integrated circuit device is characterized by: (a) forming a first conductor layer to be a gate of a first MI SFET on a semiconductor substrate via a first insulating film: (b) in the first conductive film The above-mentioned semiconductor conducting body circuit device at both ends of this paper is in Chinese national standard (CNS &gt; A4 size (210X297mm)) -6-412862 B8 C8 D8 6. The scope of patent application The substrate surface can be regarded as the first 1M ISFET source and drain to use in the first and second semiconductor fields; (c) coating the second insulating film as if covering the first 1M SFET, and heat-treating the second insulating film Over (D) a process of forming a first opening in the first insulating film to expose the first semiconductor region of the first MI SFET; (e) a process of forming a second conductor layer in the first opening; (f) Process (S) for forming a third insulating film on the second conductor layer Process (1) for forming a third conductor layer on the third insulating film (h) Applying a fourth insulating film on the third conductor layer, and A process of performing a second heat treatment on the fourth insulating film: (i) a process of forming a second opening in the fourth insulating film to expose a part of the third conductor layer; and (J) in the second opening. The process of forming a fourth conductor layer; and the first heat treatment temperature is higher than the second heat treatment temperature = 2 4 If the method of manufacturing a semiconductor integrated circuit device according to item 23 of the patent application, the above 3 and 4 conductors The layer is stacked with an aluminum layer. 25. As in the method for manufacturing a semiconductor integrated circuit device according to item 23 of the patent application scope, between the above processes (d) and (e), (k) is further washed with hydrofluoric acid. The process of the surface of the semiconductor substrate of the first opening above. ^ 2 6. As applied The paper size of the semiconductor integrated circuit assembly of the item No. 2 and 3 is applicable to the Chinese National Standards (CNS) A4 (210X297 mm): ~~ Z-. 1 .-------: Dream ------ Order (please read the note f on the back before filling this page) Printed by BS 412862, Shellfish Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs Ⅵ. The processes (C) and (d) further include (1) a process of honing the second insulating film mechanically and chemically. 27. If the method of manufacturing a semiconductor integrated circuit device according to item 23 of the scope of patent application, between the processes (c) and (d), there is (m) a fifth insulating film deposited on the second insulating film, and The process of honing the fifth insulating film mechanically and chemically. 2 8. The method for manufacturing a semiconductor integrated circuit device according to item 23 of the scope of patent application * further includes forming a sixth insulating film between the third conductive layer and the fourth insulating layer, and forming the fourth insulating film A process of forming a seventh insulating film with the fourth conductive film. 2 9. —A method for manufacturing a semiconductor integrated circuit device, which mainly includes first and second] VII SFETs formed on a semiconductor substrate, and is characterized by having: (a) selective formation on a semiconductor substrate The process of the trench; (b) The process of depositing an oxide film with a film thickness that can cover the trench, and selectively leaving the oxide film in the trench: Printed by the Central Consumers ’Association of the Ministry of Economic Affairs (Please read the precautions on the back before filling this page) (c) On the semiconductor substrate surrounded by the above trenches, the process of forming the first conductor layers of the gates of the MI SFETs No. 2 and No. 2 adjacent to each other (D) a process of forming a silicon nitride film on the first conductive film and between the first conductive films; (e) between the first conductive layer and the first conductive layer of the gates of the MI SFETs described above as the first and second The process of coating the first insulating layer on the conductor layer and applying heat treatment on the above first insulating layer; This paper size applies to China National Standard #CNS (CNS) A4 (210X297 mm) -8-Central Standard of Ministry of Economic Affairs Bureau employee consumer cooperatives printed Λ8 B8 C8-: _412 age D8 --- 々 Application scope (f) Between the first conductor layer of the gates of the first and second MISFETs, an opening is formed in the first insulating film and the silicon nitride film to make the semiconductor substrate The process of exposing the main surface; (g) the process of washing the main surface of the semiconductor substrate with a liquid containing hydrofluoric acid; and C h) the process of forming a second conductor layer in the opening, and the process of forming the opening includes : Under the condition that the etching rate of the first insulating film is larger than that of the silicon nitride film, the process of performing the uranium etching of the first insulating film and the etching rate of the silicon nitride film is larger than that of the insulating film. Under the conditions, the above-mentioned etching process of the silicon nitride film is performed. 30. A method for manufacturing a semiconductor integrated circuit device, comprising: (a) a process of selectively forming a trench on a semiconductor substrate; (b) depositing an oxide film having a thickness capable of covering the trench A process of selectively leaving the oxide film in the trench; (c) a process in which the first and second conductor layers are formed next to each other on the semiconductor substrate; (d) in the first and the first A process of forming a silicon nitride film on the conductive film of 2 and between the first and second conductive films; (e) coating a first insulating layer on the silicon nitride film to make the energy between the first and second conductive films The process of applying a heat treatment to the first insulating layer while being covered: (f) forming a first opening between the first insulating layer and the first silicon nitride film adjacent to each other between the first and second conductor layers. 1 and 2nd open n-^^ 1 I 1--I * I— I I. 111 ID ^^ 1 ^^ 1 n ^^ 1 (Please note on the back of wtl before filling this page) This paper size 逋With China National Standards (CNS) A4 (2 丨 0 &gt; &lt; 297 mm) -9-AS B8 CS D8 Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs «- 6. The process of applying for the patent Fanyuankou and exposing the main surface of the semiconductor substrate: (g) the process of washing the main surface of the semiconductor substrate with a liquid containing hydrofluoric acid; and (h) The process of forming the second conductor layer in the two openings, and the process of forming the first and second openings includes: performing the first insulation under the condition that the etching rate of the first insulating film is greater than that of the silicon nitride film. The process of etching the film and the process of etching the silicon nitride film under the condition that the etching rate of the silicon nitride film is greater than that of the oxide film. 3 1 · The method for manufacturing a semiconductor integrated circuit device according to claim 30 of the patent application range, wherein the first insulating film is a SOG film. 3 2. According to the manufacturing method of the semiconductor integrated circuit device No. 30 in the scope of patent application, between (e) process and (f) process, there is (i) a second The process of insulating film; and (j) the process of applying honing to the above-mentioned second insulating film. 3 3. According to the manufacturing method of the semiconductor integrated circuit device No. 30 in the scope of the patent application, the silicon nitride film is etched as follows: a sidewall insulating film is formed on the side walls of the first and second conductor layers Anisotropic etching process. (Please read the note on the back before filling this page) 本紙張尺度適用中國國家標準（CNS ) A4洗格（210X297公釐） -10-This paper size applies to China National Standard (CNS) A4 Washing (210X297 mm) -10-
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