CN101263600B - 半导体元件的制造方法、以及由此方法形成的半导体元件 - Google Patents

半导体元件的制造方法、以及由此方法形成的半导体元件 Download PDF

Info

Publication number
CN101263600B
CN101263600B CN2004800392661A CN200480039266A CN101263600B CN 101263600 B CN101263600 B CN 101263600B CN 2004800392661 A CN2004800392661 A CN 2004800392661A CN 200480039266 A CN200480039266 A CN 200480039266A CN 101263600 B CN101263600 B CN 101263600B
Authority
CN
China
Prior art keywords
forming
region
semiconductor
buried layer
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2004800392661A
Other languages
English (en)
Chinese (zh)
Other versions
CN101263600A (zh
Inventor
詹姆斯·A·基希格斯纳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN101263600A publication Critical patent/CN101263600A/zh
Application granted granted Critical
Publication of CN101263600B publication Critical patent/CN101263600B/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/40Vertical BJTs
    • H10D10/421Vertical BJTs having both emitter-base and base-collector junctions ending at the same surface of the body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/01Manufacture or treatment
    • H10D10/021Manufacture or treatment of heterojunction BJTs [HBT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/01Manufacture or treatment
    • H10D10/051Manufacture or treatment of vertical BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/80Heterojunction BJTs
    • H10D10/821Vertical heterojunction BJTs
    • H10D10/891Vertical heterojunction BJTs comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137Collector regions of BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0107Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401Combinations of FETs or IGBTs with BJTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)
CN2004800392661A 2003-12-31 2004-11-18 半导体元件的制造方法、以及由此方法形成的半导体元件 Expired - Fee Related CN101263600B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/750,125 2003-12-31
US10/750,125 US7084485B2 (en) 2003-12-31 2003-12-31 Method of manufacturing a semiconductor component, and semiconductor component formed thereby
PCT/US2004/038757 WO2005065089A2 (en) 2003-12-31 2004-11-18 Method of manufacturing a semiconductor component, and semiconductor component formed thereby

Publications (2)

Publication Number Publication Date
CN101263600A CN101263600A (zh) 2008-09-10
CN101263600B true CN101263600B (zh) 2010-10-27

Family

ID=34711212

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2004800392661A Expired - Fee Related CN101263600B (zh) 2003-12-31 2004-11-18 半导体元件的制造方法、以及由此方法形成的半导体元件

Country Status (7)

Country Link
US (1) US7084485B2 (enExample)
EP (1) EP1702349A4 (enExample)
JP (1) JP2007525831A (enExample)
KR (1) KR20060111650A (enExample)
CN (1) CN101263600B (enExample)
TW (1) TWI370520B (enExample)
WO (1) WO2005065089A2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7358545B2 (en) * 2005-08-10 2008-04-15 United Microelectronics Corp. Bipolar junction transistor
US7772060B2 (en) * 2006-06-21 2010-08-10 Texas Instruments Deutschland Gmbh Integrated SiGe NMOS and PMOS transistors
US8405127B2 (en) * 2008-02-20 2013-03-26 International Business Machines Corporation Method and apparatus for fabricating a heterojunction bipolar transistor
JP2011528187A (ja) * 2008-07-14 2011-11-10 エヌエックスピー ビー ヴィ トランジスタデバイス及びその製造方法
US8053866B2 (en) * 2009-08-06 2011-11-08 Freescale Semiconductor, Inc. Varactor structures
CN102403343B (zh) * 2010-09-08 2013-07-24 上海华虹Nec电子有限公司 BiCMOS工艺中的垂直寄生型PNP器件及制造方法
CN102544081B (zh) * 2010-12-16 2014-10-08 上海华虹宏力半导体制造有限公司 锗硅异质结npn三极管及制造方法
CN102412274B (zh) * 2011-01-13 2014-02-26 上海华虹宏力半导体制造有限公司 锗硅hbt工艺中垂直寄生型pnp器件及制造方法
CN102655170B (zh) * 2011-03-04 2014-08-13 上海华虹宏力半导体制造有限公司 锗硅异质结双极晶体管工艺中可变电容及制造方法
CN102956480A (zh) * 2011-08-31 2013-03-06 上海华虹Nec电子有限公司 有赝埋层的锗硅hbt降低集电极电阻的制造方法及器件
CN102412275B (zh) * 2011-09-22 2013-06-12 上海华虹Nec电子有限公司 锗硅BiCMOS工艺中纵向PNP器件及制作方法
CN102412287B (zh) * 2011-11-08 2013-07-24 上海华虹Nec电子有限公司 锗硅hbt器件及其制造方法
CN103050518B (zh) * 2012-01-06 2015-04-08 上海华虹宏力半导体制造有限公司 锗硅异质结双极型晶体管及其制造方法
US10431654B2 (en) * 2015-06-25 2019-10-01 International Business Machines Corporation Extrinsic base doping for bipolar junction transistors

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1231506A (zh) * 1998-04-07 1999-10-13 日本电气株式会社 高速和低寄生电容的半导体器件及其制造方法
US6472753B2 (en) * 2000-11-07 2002-10-29 Hitachi, Ltd. BICMOS semiconductor integrated circuit device and fabrication process thereof
CN1447442A (zh) * 2002-03-27 2003-10-08 罗姆股份有限公司 一种双极型晶体管及应用它的半导体装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55132052A (en) * 1979-03-31 1980-10-14 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device
US4674173A (en) * 1985-06-28 1987-06-23 Texas Instruments Incorporated Method for fabricating bipolar transistor
JPH02283028A (ja) * 1988-12-23 1990-11-20 Fujitsu Ltd 半導体装置及びその製造方法
GB2243717B (en) * 1990-05-01 1994-06-15 Stc Plc Bipolar transistor device
US5061646A (en) 1990-06-29 1991-10-29 Motorola, Inc. Method for forming a self-aligned bipolar transistor
JP2746499B2 (ja) * 1992-05-15 1998-05-06 三菱電機株式会社 半導体装置及びその製造方法
WO1995005679A1 (en) * 1993-08-17 1995-02-23 Peter Fred Blomley Bipolar transistors and method of making the same
US5465006A (en) * 1994-07-15 1995-11-07 Hewlett-Packard Company Bipolar stripe transistor structure
US5569613A (en) * 1995-02-01 1996-10-29 United Microelectronics Corp. Method of making bipolar junction transistor
JPH11312687A (ja) * 1998-04-30 1999-11-09 Toshiba Corp 半導体装置およびその製造方法
US6239477B1 (en) * 1998-10-07 2001-05-29 Texas Instruments Incorporated Self-aligned transistor contact for epitaxial layers
JP2000252294A (ja) * 1999-03-01 2000-09-14 Nec Corp 半導体装置及びその製造方法
JP3322239B2 (ja) * 1999-04-30 2002-09-09 日本電気株式会社 半導体装置の製造方法
WO2001004960A1 (en) * 1999-07-07 2001-01-18 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for the same manufacturing
JP3748744B2 (ja) * 1999-10-18 2006-02-22 Necエレクトロニクス株式会社 半導体装置
JP3621359B2 (ja) * 2001-05-25 2005-02-16 Necエレクトロニクス株式会社 半導体装置及びその製造方法
JP2003007713A (ja) * 2001-06-22 2003-01-10 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
FR2829288A1 (fr) * 2001-09-06 2003-03-07 St Microelectronics Sa Structure de contact sur une region profonde formee dans un substrat semiconducteur

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1231506A (zh) * 1998-04-07 1999-10-13 日本电气株式会社 高速和低寄生电容的半导体器件及其制造方法
US6472753B2 (en) * 2000-11-07 2002-10-29 Hitachi, Ltd. BICMOS semiconductor integrated circuit device and fabrication process thereof
CN1447442A (zh) * 2002-03-27 2003-10-08 罗姆股份有限公司 一种双极型晶体管及应用它的半导体装置

Also Published As

Publication number Publication date
JP2007525831A (ja) 2007-09-06
TWI370520B (en) 2012-08-11
WO2005065089A3 (en) 2007-12-06
US7084485B2 (en) 2006-08-01
TW200525701A (en) 2005-08-01
KR20060111650A (ko) 2006-10-27
EP1702349A2 (en) 2006-09-20
CN101263600A (zh) 2008-09-10
EP1702349A4 (en) 2010-09-15
US20050145951A1 (en) 2005-07-07
WO2005065089A2 (en) 2005-07-21

Similar Documents

Publication Publication Date Title
US7491617B2 (en) Transistor structure with minimized parasitics and method of fabricating the same
US6940149B1 (en) Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base
CN102104062B (zh) 双极晶体管
KR100486304B1 (ko) 자기정렬을 이용한 바이씨모스 제조방법
US9059138B2 (en) Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure
US8476675B2 (en) Semiconductor device and method of manufacture thereof
CN101529568B (zh) 制造双极晶体管的方法
CN110310988B (zh) 半导体装置和制造半导体装置的方法
CN101263600B (zh) 半导体元件的制造方法、以及由此方法形成的半导体元件
US6156594A (en) Fabrication of bipolar/CMOS integrated circuits and of a capacitor
CN113270490A (zh) 一种pnp型双极晶体管制造方法
US8872237B2 (en) Heterojunction bipolar transistor manufacturing method and integrated circuit comprising a heterojunction bipolar transistor
US6180442B1 (en) Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method
CN100463217C (zh) 制备窄掺杂剖面高性能半导体器件的结构和方法
KR100455829B1 (ko) 초자기정렬 이종접합 바이폴라 소자 및 그 제조방법
JP2005510867A (ja) 半導体デバイスおよび該半導体デバイスの製造方法
US11721726B2 (en) Horizontal current bipolar transistor with silicon-germanium base
JP2001319936A (ja) バイポーラトランジスタ及びその製造方法
US20130099288A1 (en) SiGe HBT and Manufacturing Method Thereof
US7572708B1 (en) Utilization of doped glass on the sidewall of the emitter window in a bipolar transistor structure
US20090212394A1 (en) Bipolar transistor and method of fabricating the same
CN100533680C (zh) 双极晶体管及其制造方法
CN101194348A (zh) 制造异质结双极晶体管的方法
HK1028487A (en) Trench-isolated bipolar devices

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20101027

Termination date: 20181118

CF01 Termination of patent right due to non-payment of annual fee