CN101238585A - Ldmos晶体管 - Google Patents

Ldmos晶体管 Download PDF

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CN101238585A
CN101238585A CN200680028703.9A CN200680028703A CN101238585A CN 101238585 A CN101238585 A CN 101238585A CN 200680028703 A CN200680028703 A CN 200680028703A CN 101238585 A CN101238585 A CN 101238585A
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ldmos transistor
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斯蒂芬·J·C·H·特厄乌文
弗雷尔克·范瑞哲
彼得拉·C·A·哈梅斯
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Koninklijke Philips NV
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Abstract

本发明的LDMOS晶体管(1)包括衬底(2)、栅极电极(10)、衬底触点区域(11)、源极区域(3)、沟道区域(4)和漏极区域(5)，漏极区域(5)包括漏极触点区域(6)和漏极延伸区域(7)。漏极触点区域(6)与在漏极延伸区域(7)上方延伸的顶部金属层(23)电连接，其中顶部金属层(23)与漏极延伸区域(7)之间的距离(723)大于2μm。这样可以减小漏极触点区域(6)的面积并且增加LDMOS晶体管(1)的RF功率输出效率。在另一种实施方式中，源极区域(3)经由硅化物层(32)而不是第一金属层(21)与衬底触点区域(11)电连接，从而减小了源极区域(3)与漏极区域(5)之间的容性耦合并且由此进一步增大了LDMOS晶体管(1)的RF功率输出效率。

Description

LDMOS晶体管
技术领域
本发明涉及LDMOS晶体管。
背景技术
在用于个人通信系统(GSM、EDGE、WCDMA)的基站中，RF功率放大器是关键部件。对于这些功率放大器，RF横向扩散金属氧化物半导体(一般缩写为LDMOS)晶体管是现在的技术首选，因为它们拥有优异的高功率、增益和线性。为了能够满足新的通信标准所施加的要求，LDMOS晶体管的性能在尺寸持续不断缩小的同时正经历着连续不断的提高。
在WO2005/022645中，公开了一种LDMOS晶体管，这种晶体管包括半导体衬底中的源极和漏极区域，在半导体衬底中，源极和漏极区域是通过沟道区域相互连接起来的。源极区域和衬底通过第一金属层电连接。该LDMOS晶体管此外还包括半导体衬底上的栅极电极，用于影响沟道区域中的电子分布。漏极区域包括漏极触点区域和从漏极触点区域朝向沟道区域延伸的漏极延伸区域。漏极触点区域经由漏极触点与顶部金属层电连接，该顶部金属层仅仅在漏极触点区域上方延伸并且不在漏极延伸区域上方延伸。这样防止了顶部金属层对漏极延伸区域的耗尽造成不良影响，因为如果顶部金属层在漏极延伸区域上方延伸，则漏极延伸区域的串联电阻将会变得更加取决于电压，从而会降低LDMOS晶体管的性能。此外，顶部金属层需要具有很高的电流承受力，这导致顶部金属层要很宽很厚才能够在不遭受电迁移的前提下承受很高的电流电平。因为仅允许顶部金属层在漏极触点区域上方延伸并且因为顶部金属层宽到足以能够承受很高的电流电平，所以漏极触点区域会占据相对较大的面积，这会不利地增大由LDMOS晶体管占据的总面积。另一个缺点是，漏极触点区域的面积相对较大会导致LDMOS晶体管的输出电容相对较大。LDMOS晶体管的输出电容是由源极区域和漏极区域之间的容性耦合(除此之外还有其它因素)决定的，并且该输出电容包括漏极延伸区域到源极区域的电容和漏极触点区域到源极区域的电容。在28V的典型漏极偏置的条件下，漏极延伸区域几乎完全耗尽，并且因此LDMOS晶体管的输出电容在这一典型偏置条件下主要由漏极触点区域到源极区域的电容决定。输出电容相对较大会不利地降低LDMOS晶体管的RF功率输出效率，RF功率输出效率被定义为RF输出功率除以LDMOS晶体管的DC输入功率。
发明内容
本发明的目的是提供一种RF功率输出效率得到改善的LDMOS晶体管。按照本发明，这一目的是通过提供权利要求1中所述的LDMOS晶体管来实现的。
按照本发明的LDMOS晶体管包括处于第一半导体类型的半导体衬底中的均为第二半导体类型的源极区域和漏极区域，源极区域和漏极区域通过第一半导体类型的沟道区域相互连接。栅极电极在沟道区域上方延伸并且能够影响沟道区域中的电子分布。漏极区域包括漏极触点区域和漏极伸展区域，漏极延伸区域接近沟道区域。按照本发明的LDMOS晶体管此外还包括顶部金属层，该顶部金属层通过漏极触点与漏极触点区域电连接，并且该顶部金属层在漏极延伸区域上方延伸，其中顶部金属层与漏极延伸区域之间的距离基本上大于2μm。本发明基于这样的见解：如果顶部金属层与漏极延伸区域之间的距离使得顶部金属层几乎不会影响漏极延伸区域的耗尽，则使得顶部金属层能够在漏极延伸区域上方延伸又不影响LDMOS晶体管的性能成为了可能。从而给予顶部层获得期望电流承受力所需的任何尺寸而漏极触点区域不需要具有相同大小的尺寸成为了可能。此外，与现有技术相比，漏极触点区域的面积并且由此LDMOS晶体管的输出电容得到了减小，因为漏极触点区域的面积不需要与顶部金属层的尺寸一样大。输出电容的减小有利地增加了LDMOS晶体管的RF功率输出效率。
另一个优点是，漏极触点区域面积的减小能够实现由LDMOS晶体管占据的总面积的减小。
此外，顶部金属层和漏极触点区域之间的距离使得顶部金属层不会对反馈电容造成影响。反馈电容是漏极区域和栅极电极之间的电容。顶部金属层和漏极触点区域之间的距离较短会增大反馈电容，从而降低LDMOS晶体管的RF性能。
此外，顶部金属层和漏极延伸区域之间的距离使得LDMOS晶体管在零栅极电压(BVdss)下的漏极到源极击穿电压不受顶部金属层的影响。顶部金属层和漏极触点区域之间的距离较短会不利地减小LDMOS晶体管的漏极到源极击穿电压。
在按照本发明的LDMOS晶体管的第一实施方式中，顶部金属层和漏极延伸区域之间距离是5μm。在这个距离下，顶部金属层对LDMOS晶体管性能的影响表现得足够小。
在按照本发明LDMOS晶体管的第二实施方式中，经由漏极触点到漏极触点区域的电连接此外还包括至少一个中间金属层和处于中间金属层与顶部金属层之间的至少一个金属间触点。至少一个中间层的引入有益地增加了顶部金属层和漏极延伸区域之间的距离并且有利地引入了LDMOS晶体管与IC(集成电路)上其它装置的相互连接方案的自由度。
在按照本发明的LDMOS晶体管的第三实施方式中，顶部金属层包括Al和Cu的混合物。顶部金属层的尺寸不受漏极触点区域面积约束这一实际情况为使用比Au更为普通和更加便宜的金属材料提供了可能。因为A1和Cu材料的混合物不能承受和Au一样高的电流电平，所以顶部金属层具有比现有技术的顶部金属层更大的宽度，以使得顶部金属层能够承受住与现有技术相同的高电流电平，而又不会遭受电迁移。
在按照本发明的LDMOS晶体管的第四实施方式中，第一LDMOS晶体管的漏极触点区域与第二LDMOS晶体管的漏极触点区域是公共的，第二LDMOS晶体管与第一LDMOS晶体管镜面对称。在这种实施方式中，漏极触点区域面积减小的益处由两个LDMOS晶体管共享，这将会进一步减小LDMOS晶体管在IC上占据的总面积。
在第五实施方式中，LDMOS晶体管包括第一半导体类型的衬底触点区域，该衬底触点区域与源极区域邻接，其中衬底触点区域和源极区域经由硅化物层电连接。硅化物层要比现有技术中用来将衬底触点区域与源极区域电连接起来的第一金属层薄，从而进一步减小了反馈电容并且由此进一步增大了LDMOS晶体管的RF功率输出效率，因为硅化物层的尺寸比标准金属层的尺寸小。
在第六实施方式中，LDMOS晶体管包括处于栅极电极和漏极触点区域之间的屏蔽层，其中该屏蔽层在漏极延伸区域的一部分上方延伸。屏蔽层的引入减小了栅极电极和漏极区域之间的反馈电容，这对LDMOS晶体管的RF性能有好处。
附图说明
将参照附图进一步阐述和介绍本发明的这些和其它方面，其中：
图1表示按照现有技术的LDMOS晶体管的简略横截面图；
图2表示按照本发明的一个实施方式的LDMOS晶体管的简略横截面图；
图3表示按照本发明的第二实施方式的LDMOS晶体管的简略横截面图；和
图4表示按照本发明的第三实施方式的LDMOS晶体管的简略横截面图。
附图不是按比例画出的。总地来说，在附图中，相同的组成部分由相同的附图标记指代。
具体实施方式
图1画出了按照现有技术的常规LDMOS晶体管99的横截面图，包括半导体材料的衬底2，在此情况下是p型硅，在衬底2上形成有p型外延层12。LDMOS晶体管99此外还包括n型源极区域3、n型漏极区域5和多晶硅栅极电极10，可以根据情况为多晶硅栅极电极10配备硅化物层并且多晶硅栅极电极10在沟道区域4上方延伸，多晶硅栅极电极10在这个例子中是横向扩散p型区域。源极区域3和漏极区域5通过沟道区域4相互连接。p型衬底触点区域11与衬底2电连接并且在与邻接沟道区域4的一侧相反的一侧上与源极区域3邻接。沟道区域4、衬底触点区域11、源极区域3和漏极区域5都设置在外延层12内。栅极电极10与衬底2由栅极氧化物层18分隔开，栅极氧化物层18例如包括热生长的二氧化硅。源极区域3通过源极触点41、第一金属层21和衬底触点40与衬底触点区域11电连接。因此源极区域3经由衬底触点区域11与衬底2的底表面电连接。
漏极区域5包括n型漏极延伸区域7和n型漏极触点区域6，漏极延伸区域7照顾到LDMOS晶体管99的高压操作。漏极延伸区域7的掺杂等级比漏极触点区域6低并且漏极延伸区域7对LDMOS晶体管99的最大输出功率是最优的。应当注意，漏极延伸区域7还可以包括多种不同类型的掺杂等级，这提高了装置的寿命。
LDMOS晶体管99此外还包括屏蔽层31，屏蔽层31起到虚假栅极电极的作用并且改善反馈电容。屏蔽层31在这种情况下在栅极电极10和漏极延伸区域7的一部分上方延伸并且被绝缘层14与栅极电极10分隔开，绝缘层14例如包括等离子体氧化物。屏蔽层31与外延层12被栅极氧化物层18和绝缘层14分隔开，并且因此与漏极延伸区域7分隔开。由于屏蔽层31与栅极电极10和漏极延伸区域7靠得很近，因此漏极延伸区域7中的电场分布得到了改善，从而减小了反馈电容，这对RF性能有好处。
漏极触点区域6用于将漏极区域5分别经由漏极触点20和第一金属间触点22电连接到第一金属层21和顶部金属层23。顶部金属层21与漏极延伸区域7之间的距离在这个例子中是2μm。看起来LDMOS晶体管99的性能，比如源极到漏极的击穿电压和输出电容，在顶部金属层21在漏极延伸区域7上方延伸的时候受到了不良影响。因此，第一金属层21和顶部金属层23都不在漏极延伸区域7上方延伸，以便避免金属层对LDMOS晶体管99的性能造成任何不良影响。顶部金属层23具有大到足以使得顶部金属层23能够承受住高电流电平而不遭受电迁移的尺寸(例如宽度和厚度)。此外，顶部金属层23的材料包括Au，这种材料比起其它较为传统的材料(比如Al和Cu)，能够承受住更高电流电平而不会遭受电迁移。漏极触点区域6的面积相对较大，因为顶部金属层23具有较大的宽度并且不得在漏极延伸区域7上方延伸。漏极触点区域6的面积较大为应用多个漏极和第一金属间触点20、22提供了可能。
图2画出了按照本发明的LDMOS晶体管1的第一实施方式的横截面图。LDMOS晶体管1，类似于现有的LDMOS晶体管99，包括衬底2、衬底触点区域11、外延层12、栅极电极10、屏蔽层31、绝缘区域14、栅极氧化物层18、沟道区域4、源极区域3和漏极区域5，漏极区域5包括漏极触点区域6和漏极延伸区域7。
与现有技术的LDMOS晶体管99的主要差别在于，按照本发明的LDMOS晶体管1的顶部金属层23在漏极延伸区域7上方延伸，在这个例子中，漏极触点区域7与顶部金属层23之间的距离723为5μm。另一个差别在于，顶部金属层包括Al和Cu的混合物，这是IC技术中更为普通的材料。因为这种材料不能承受和现有技术的LDMOS晶体管99中应用的材料Au一样高的电流电平，所以顶部金属层23具有比现有技术的LDMOS晶体管99的顶部金属层更大的宽度，以使得顶部金属层23能够承受住与现有技术相同的高电流电平，而不会遭受电迁移。与现有技术的LDMOS晶体管99的再一个差别在于，在这种情况下，漏极触点区域6通过漏极触点20、第一金属层21、第一金属间触点22、第二金属层24、第二金属间触点25、第三金属层26和第三金属间触点27与顶部金属层电连接。这一金属层与金属间触点的层叠在顶部金属层23和漏极延伸区域7之间创造了大到足以使顶部金属层23能够在漏极延伸区域7上方延伸而又不影响LDMOS晶体管性能的距离723。此外，额外的金属层给出了设计LDMOS晶体管与IC上其它装置的耗费较小面积的相互连接方案的额外自由度。
漏极触点区域6利用一个漏极触点20与第一金属层21电连接，这使得漏极触点区域6的面积大幅减小。于是这个面积由漏极触点20的尺寸和所应用技术的平板印刷能力决定。因为输出电容减小了，所以漏极触点区域6的面积减小提高了LDMOS晶体管1的RF功率输出效率。
图3画出了按照本发明的LDMOS晶体管1的第二实施方式的横截面图。在该实施方式中，源极区域3和衬底触点区域11通过硅化物层32电连接，硅化物层32要比第一金属层21薄并且减小了源极区域3与漏极区域5之间的容性耦合。由此，减小了输出电容，LDMOS晶体管1的RF功率输出效率随之相应地进一步增大。
图4画出了按照本发明的LDMOS晶体管1的第三实施方式的横截面图，其中LDMOS晶体管1的漏极触点区域6与第二LDMOS晶体管91的漏极触点区域6是公共的，第二LDMOS晶体管91与LDMOS晶体管1沿着轴线A-A’镜面对称。此外，两个LDMOS晶体管1和91现在分享了漏极触点区域6面积减小的益处。这样由LDMOS晶体管1和第二LDMOS晶体管91占据的面积比LDMOS晶体管1和LDMOS晶体管91各自具有它们自己的单独的漏极触点区域6时的情况还要小。
对LDMOS晶体管1进行的测量的结果表明，与现有技术的LDMOS晶体管99相比，取决于测量条件，RF功率输出效率增加了4个百分点左右。此外，表明了与现有技术的LDMOS晶体管99相比，取决于测量条件，输出电容减小了15％左右。
总而言之，本发明的LDMOS晶体管包括衬底、栅极电极、衬底触点区域、源极区域、沟道区域和漏极区域，漏极区域包括漏极触点区域和漏极延伸区域。漏极触点区域与顶部金属层电连接，该顶部金属层在漏极延伸区域上方延伸，其中顶部金属层与漏极延伸区域之间的距离大于2μm。这样可以减小漏极触点区域的面积并且增加LDMOS晶体管的RF功率输出效率。在另一种实施方式中，源极区域经由硅化物层而不是第一金属层与衬底触点区域电连接，从而减小了源极区域与漏极区域之间的容性耦合，并且由此进一步增大了LDMOS晶体管的RF功率输出效率。
应当注意，前面提到的实施方式是图解说明而不是对本发明加以限制，并且本领域技术人员将能够设计出很多可供选用的实施方式，而不会超出由所附权利要求定义的本发明的范围。在权利要求里，置于括号之间的任何附图标记都不应看作是对权利要求的限定。单词“包括”并不排除除了权利要求中列出的那些元件或步骤之外还存在其它的元件或步骤的可能。此外，置于要素前面的单词“一”或“一个”并不排除存在多个这种要素的可能。

Claims (8)

1.一种LDMOS晶体管(1)，其被设置在第一半导体类型的半导体衬底(2)中，该LDMOS晶体管(1)包括：
均为第二半导体类型并且通过沟道区域(4)相互连接的源极区域(3)和漏极区域(5)，其中栅极电极(10)在所述沟道区域(4)上方延伸，所述漏极区域(5)包括漏极触点区域(6)和从沟道区域(4)朝向漏极触点区域(6)延伸的漏极延伸区域(7)，其中漏极触点区域(6)经由漏极触点(20)与顶部金属层(2 3)电连接，
所述LDMOS晶体管(1)的特征在于，顶部金属层(23)在漏极延伸区域(7)的至少一部分上方延伸，其中顶部金属层(23)与漏极延伸区域(7)之间的距离(723)大于2μm。
2.按照权利要求1中所述的LDMOS晶体管(1)，其中，顶部金属层(23)与漏极延伸区域(7)之间的距离(723)为5μm。
3.按照权利要求1中所述的LDMOS晶体管(1)，其中，漏极触点(20)和顶部金属层(23)通过至少一个中间金属层(21，24，26)和至少一个金属间触点(22，25，27)电连接。
4.按照权利要求1中所述的LDMOS晶体管(1)，其中，顶部金属层(23)包括Al和Cu的混合物。
5.按照权利要求1中所述的LDMOS晶体管(1)，其中，漏极触点区域(6)利用一个漏极触点(20)与顶部金属层(23)电连接。
6.按照权利要求1中所述的LDMOS晶体管(1)，其中，LDMOS晶体管(1)的漏极触点区域(6)与第二LDMOS晶体管(91)的漏极触点区域(6)是公共的，第二LDMOS晶体管(91)与LDMOS晶体管(1)镜面对称。
7.按照权利要求1中所述的LDMOS晶体管(1)，其中，LDMOS晶体管(1)此外还包括第一半导体类型的衬底触点区域(11)，该衬底触点区域(11)在与邻接沟道区域(4)的一侧相反的一侧处与源极区域(3)邻接，并且其中衬底触点区域(11)和源极区域(3)经由硅化物层(32)电连接。
8.按照前述任何一项权利要求中所述的LDMOS晶体管(1)，此外还包括处于栅极电极(10)和漏极触点区域(6)之间的屏蔽层(11)，所述屏蔽层(11)覆盖着漏极延伸区域(7)的一部分。
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