CN101211972B - 半导体结构及其形成方法 - Google Patents
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Abstract
本发明提供一种半导体结构及其形成方法。其中该半导体结构包括:基板;第一阱区,位于上述基板上,上述第一阱区具有第一导电类型;第二阱区和第三阱区,上述第二阱区相邻于上述第一阱区,上述第二和第三阱区具有相反于上述第一导电类型的第二导电类型;第一深阱区,位于至少一部分的上述第一阱区和上述第二阱区下方,上述第一深阱区具有上述第二导电类型;第二深阱区,位于上述第三阱区下方,上述第二深阱区具有上述第二导电类型;绝缘区,位于一部分上述第一阱区中;栅极介电质,从上述绝缘区的上方延伸至上述第二阱区的上方;栅极,位于上述栅极介电质上。本发明能够提高击穿电压。
Description
技术领域
本发明有关于一种半导体元件,特别有关于一种金属氧化物半导体(metal-oxide-semiconductor,MOS)元件,又特别有关于一种高压MOS元件的结构及其制造方法。
背景技术
高压金属氧化物半导体(high-voltage metal-oxide-semiconductor,HVMOS)元件广泛地应用于例如中央处理器电源供应器(CPU power supply)、电源管理系统(power management)、交流/直流转换器(AC/DC converter)等许多电子元件中。HVMOS元件具有多种类型。横向扩散MOS元件(lateral diffused MOS,LDMOS)为最常用的HVMOS元件。LDMOS元件典型地包括漏极区和包围漏极区的横向扩散漏极区。横向扩散漏极区典型地具有比漏极区低的掺杂浓度,因此具有高崩溃电场。
图1显示公知的横向扩散p型MOS元件(lateral diffused PMOS,LDPMOS)2,其包括栅极氧化层10、位于栅极氧化层10上的栅极12、位于低压p型阱(low-voltage p-well,LVPW)区4中的漏极区6以及位于低压n型阱(low-voltage n-well,LVNW)区7中的源极区8。浅沟槽隔离(shallow trenchisolation,STI)区14隔开漏极区6和栅极12,所以可外加高的漏极对栅极的电压(drain-to-gate voltage)。LDPMOS元件2可被绝缘环状物(isolation ring)包围,其包括LVNW区7和16,以及对应的拾取区(pickup region)18。为了绝缘的目的,n型深阱(deep n-well,DNW)区20典型地在LVPW区4以及LVNW区7和16的下方形成。
典型地,绝缘环状物施加0V的电压。因此,当漏极区6施加高电压时,漏极区6和LVNW区16之间施加相同的高电压。在介于LVPW区4、LVNW区16和DNW区20之间的界面的区域22中会产生高电场。高电场的产生会导致LDPMOS元件2的击穿电压(breakdown voltage)下降。如图1所示,LDPMOS元件典型地可在高约12V的高电压下操作而不会击穿。然而,LDPMOS元件经常被要求在16V或更高的电压下操作。因此,需要改善LDPMOS元件的结构。
发明内容
鉴于上述现有技术的不足,提出本发明。
本发明提供一种半导体结构,包括基板;第一阱区,位于上述基板上,上述第一阱区具有第一导电类型;第二阱区,位于上述基板上,且横向相邻于上述第一阱区,上述第二阱区具有相反于上述第一导电类型的第二导电类型;第三阱区,上述第三阱区具有上述第二导电类型,其中上述第二阱区和上述第三阱区彼此隔开;第一深阱区,位于至少一部分的上述第一阱区和上述第二阱区的下方,上述第一深阱区具有上述第二导电类型;第二深阱区,位于上述第三阱区的下方,上述第二深阱区具有上述第二导电类型,其中上述第二深阱区包围至少一部分的上述第三阱区的侧壁和底部,且其中上述第一深阱区和上述第二深阱区被间隙隔开;绝缘区,位于一部分上述第一阱区中,从上述第一阱区的顶面延伸至上述第一阱区中;栅极介电质,从上述第一阱区的上方延伸至上述第二阱区的上方,其中一部分上述栅极介电质位于上述绝缘区的上方;栅极,位于上述栅极介电质上。
如上所述的半导体结构,其中该第一导电类型为p型,且该第二导电类型为n型。
如上所述的半导体结构,其中该第一导电类型为n型,且该第二导电类型为p型。
如上所述的半导体结构,其中位于该间隙中的第二导电类型杂质的第一杂质浓度低于位于该第一深阱区和该第二深阱区中的该第二导电类型杂质的第二杂质浓度。
如上所述的半导体结构,其中该第一杂质浓度小于该第二杂质浓度超过一个数量级。
如上所述的半导体结构,其中该第一阱区、该第二阱区和该第三阱区之中每一个都为连续阱区,其具有实质上均匀的杂质浓度。
如上所述的半导体结构,还包括第四阱区,位于该第一阱区和该第三阱区之间,该第四阱区具有该第一导电类型,其中该第四阱区与该第一阱区和该第三阱区隔开。
如上所述的半导体结构,其中该第四阱区与该第二深阱区相邻。
如上所述的半导体结构,其中该第四阱区与该第二深阱区隔开。
如上所述的半导体结构,其中该第一阱区和该第二阱区为高压阱区。
如上所述的半导体结构,还包括第四阱区,位于该第二阱区相对于该第一阱区的相反侧,该第四阱区具有该第一导电类型,其中该第四阱区相邻于该第二阱区,且该栅极介电质延伸至该第四阱区上方。
如上所述的半导体结构,还包括:第一源/漏极区,位于该第一阱区中,且相邻于该绝缘区;以及第二源/漏极区,位于该第二阱区中,且相邻于该栅极介电质。
本发明提供另一种半导体结构,包括基板;第一阱区,位于上述基板上,上述第一阱区具有第一导电类型;第二阱区,位于上述基板上,且横向相邻于上述第一阱区,上述第二阱区具有相反于上述第一导电类型的第二导电类型;第三阱区,上述第三阱区具有上述第二导电类型,其中上述第二阱区和上述第三阱区被间隙彼此隔开;深阱区,位于上述第一阱区、上述第二阱区和上述第三阱区下方,上述深阱区具有上述第二导电类型,其中部分位于上述间隙的正下方的上述深阱区具有第一杂质浓度,以及其中位于上述第一阱区和上述第二阱区的正下方的上述深阱区具有第二杂质浓度,且其中上述第一杂质浓度小于上述第二杂质浓度;绝缘区,位于一部分上述第一阱区中,从上述第一阱区的顶面延伸至上述第一阱区中;栅极介电质,从上述第一阱区的上方延伸至上述第二阱区的上方,其中一部分上述栅极介电质位于上述绝缘区的上方;栅极,位于上述栅极介电质上。
本发明提供另一种半导体结构,包括:基板;第一低压p型阱区,位于上述基板上;第一低压n型阱区,位于上述基板上,且横向相邻于上述第一低压p型阱区;第二低压n型阱区,位于上述基板上,且包围上述第一低压n型阱区和上述第一低压p型阱区,其中上述第二低压n型阱区与上述第一低压n型阱区和上述第一低压p型阱区隔开;第一n型深阱区,位于至少一部分的上述第一低压n型阱区和上述第一低压p型阱区下方;第二n型深阱区,位于上述第二低压n型阱区下方,且上述第二n型深阱区与上述第一n型深阱区横向隔开;绝缘区,位于上述第一低压p型阱区中,上述绝缘区具有顶面,其大体上与上述第一低压p型阱区的顶面等高;栅极介电质,从上述绝缘区的上方延伸至上述第一低压n型阱区的上方;栅极,位于上述栅极介电质上;源极区,位于上述第一低压n型阱区中,且相邻于上述绝缘区;漏极区,位于上述第一n型深阱区中,且相邻于上述栅极介电质。
本发明还提供一种半导体结构的形成方法,包括:提供基板;在上述基板上形成第一阱区,上述第一阱区具有第一导电类型;在上述基板上形成第二阱区,且横向相邻于上述第一阱区,上述第二阱区具有相反于上述第一导电类型的第二导电类型;在该基板上形成第三阱区,上述第三阱区具有上述第二导电类型,其中上述第二阱区和上述第三阱区彼此隔开;在至少一部分的上述第一阱区和上述第二阱区下方形成第一深阱区,上述第一深阱区具有上述第二导电类型;在上述第三阱区下方形成第二深阱区,上述第二深阱区具有上述第二导电类型,其中上述第二深阱区包围至少一部分的上述第三阱区的侧壁和底部,且其中上述第一深阱区和上述第二深阱区被间隙隔开;在一部分上述第一阱区中形成一绝缘区,且上述绝缘区从上述第一阱区的顶面延伸至上述第一阱区中;形成栅极介电质,上述栅极介电质从上述第一阱区的上方延伸至上述第二阱区的上方,其中一部分上述栅极介电质位于上述绝缘区的上方;在上述栅极介电质上形成栅极。
如上所述的半导体结构的形成方法,其中该第二阱区和该第三阱区同时形成,且其中该第一深阱区和该第二深阱区同时形成。
如上所述的半导体结构的形成方法,其中该第一阱区与第一低压金属氧化物半导体元件的第一低压阱区同时形成,且该第二阱区和第三阱区与第二低压金属氧化物半导体元件的第二低压阱区同时形成。
如上所述的半导体结构的形成方法,还包括在形成该第一深阱区和该第二深阱区步骤之后,该第一深阱区和该第二深阱区中的杂质扩散进入该间隙中,且其中从该第一深阱区和该第二深阱区扩散的原子浓度具有第一杂质浓度,其值低于该第一深阱区和该第二深阱区中的第二杂质浓度。
如上所述的半导体结构的形成方法,其中该第一杂质浓度小于该第二杂质浓度超过一个数量级。
本发明的优点包括提高击穿电压。
附图说明
图1为公知的高压p型金属氧化物半导体元件。
图2至图8为本发明实施例的高压p型金属氧化物半导体元件的制造工艺剖面图。
图9至图10为本发明其它实施例的高压p型金属氧化物半导体元件。
图11为对称结构的高压p型金属氧化物半导体元件。
图12为高压n型金属氧化物半导体元件。
其中,附图标记说明如下:
2~横向扩散p型MOS元件; 4~低压p型阱区;
6~漏极区; 7~低压n型阱区;
8~源极区; 10~栅极氧化层;
12~栅极; 14~浅沟槽隔离区;
30~基板; 32、34~n型深阱区;
36、38、40~n型阱区; 41、42、54、63~光致抗蚀剂;
44、46、48~p型阱区; 50~绝缘区;
52~掩模层; 58、60~P+区;
64、66、68~N+区; 70~栅极介电质;
72~栅极; 74~栅极间隙壁;
76~高压p型金属氧化物半导体元件; 78~基板区域;
S~宽度; 80、82、90、92~低压p型阱区;
84、94、96~低压n型阱区。
具体实施方式
以下利用图2至图8,以更详细地说明本发明优选实施例。接着讨论本发明不同的优选实施例。在本发明各实施例中,相同的符号表示相同或类似的元件。
请参考图2,提供一基板30,其优选包括例如硅(silicon)的半导体材料。在其它实施例中,基板30可为例如锗化硅(SiGe)等常用的半导体材料。优选以p型杂质轻掺杂(lightly doped)基板30,然而基板30也可掺杂n型杂质。
利用光刻工艺形成且图案化光致抗蚀剂31。然后形成n型深阱(deepn-well,DNW)区32和34。n型深阱(deep n-well,DNW)区32和34优选为植入n型杂质形成。举例来说,可植入磷(phosphorous)及/或砷(arsenic)。优选地,n型深阱(deep n-well,DNW)区32和34的n型杂质浓度高于基板30的p型杂质浓度至少一个数量级。n型深阱(deep n-well,DNW)区32和34通过介于上述两者之间的间隙彼此隔开。上述间隙的宽度S影响后续形成的高压金属氧化物半导体(high-voltage metal-oxide-semiconductor,HVMOS)元件的击穿电压,并将于后段详细描述。然后,移除光致抗蚀剂31。
图3系显示光致抗蚀剂41和n型阱区36、38和40的形成方式。在本发明优选实施例中,n型阱区36、38和40为植入n型杂质形成。举例来说,可植入磷(phosphorous)及/或砷(arsenic)。优选地,n型阱区36、38和40的n型杂质浓度高于n型深阱(deep n-well,DNW)区32和34的n型杂质浓度至少一个数量级。在本发明优选实施例中,n型阱区36、38和40为低压n型阱(low-voltage n-well,LVNW)区,其与例如为核心p型金属氧化物半导体(corep-type MOS,PMOS)或p型金属氧化物半导体存储器元件(memory PMOSdevice)的低压元件(图未显示)的n型阱区同时形成。另外,n型阱区36、38和40和相应的形成低压电路的低压n型阱(low-voltage n-well,LVNW)区具有相同的深度和浓度。为了简化起见,说明书中的n型阱区36、38和40也可视为低压n型阱区36、38和40。然而,n型阱区36、38和40可与低压阱区分开形成。在其它实施例中,n型阱区36、38和40可为高压阱区,其杂质浓度优选低于低压n型阱(low-voltage n-well,LVNW)区。注意的是,从剖面图来看,虽然低压n型阱区38和40似乎为两个分离的区域,上述n型阱区38和40为包围低压n型阱(low-voltage n-well,LVNW)区36的连续隔绝环状物的一部分。形成低压n型阱区36、38和40之后,移除光致抗蚀剂41。
请参考图4,形成光致抗蚀剂42,且形成p型阱区44、46和48。p型阱区44、46和48优选为植入p型杂质形成。举例来说,可植入硼(boron)及/或铟(indium)。优选地,p型阱区44、46和48的p型杂质浓度高于n型深阱(deep n-well,DNW)区32和34的n型杂质浓度至少一个数量级。在本发明优选实施例中,p型阱区44、46和48为低压p型阱(low-voltage p-well,LVPW)区,其与例如为核心n型金属氧化物半导体(core n-type MOS,NMOS)及/或n型金属氧化物半导体存储器元件(memory NMOS device)的低压元件(图未显示)的p型阱区同时形成。另外,p型阱区44、46和48和相应的形成低压电路的低压p型阱(low-voltage p-well,LVPW)区具有相同的深度和浓度。为了简化起见,说明书中的p型阱区44、46和48也可视为低压p型阱区44、46和48。然而,p型阱区44、46和48可与低压阱区分开形成。在其它实施例中,p型阱区44、46和48可为高压阱区,其杂质浓度优选高于低压p型阱(low-voltage p-well,LVPW)区。注意的是,从剖面图来看,虽然低压p型阱区46和48似乎为两个分离的区域,上述低压p型阱区46和48为低压p型阱(low-voltage p-well,LVPW)连续隔绝环状物的一部分。在其它实施例中,不形成低压p型阱区48,而形成条状的低压p型阱区46。形成低压p型阱区44、46和48之后,移除光致抗蚀剂42。本领域技术人员可知形成低压n型阱区36、38和40,以及低压p型阱区44、46和48,仅为设计选择的考量。
图5A和图5B显示绝缘区50的形成方式。如图5A所示,在优选实施例中,以形成沟槽,再填入例如二氧化硅(SiO2)或高密度等离子体氧化物(HDPoxide)的介电材料于上述沟槽中,且进行化学机械研磨以移除过量介电材料的方式,使介电材料的表面等高于基板30的表面,以形成绝缘区50。最后形成的浅沟槽隔离(shallow trench isolation,STI)区为绝缘区50。如图5B所示,在其它实施例中,在前述形成的结构上方,形成优选为氮化硅(SiN)的掩模层52。然后图案化掩模层52以形成开口。接着进行氧化步骤,以在开口中形成绝缘区(也可称为场氧化物)50。典型地,对于0.25μm或更小尺寸的制造工艺,绝缘区50优选为浅沟槽隔离(STI)区。对于较大尺寸的制造工艺,绝缘区50优选为场氧化物。
请参考图6,涂布且图案化光致抗蚀剂54,并形成开口56。进行p型杂质植入步骤以在LVPW区48中形成P+区58,且在LVNW区36中形成P+区60。P+区58和60优选包括硼及/或其它p型杂质,且以约大于1020ions/cm3的杂质浓度重掺杂(heavily doped)形成。P+区58和60可分别作为漏极接触区(drain contact region)和源极区(source region)。杂质植入后,移除光致抗蚀剂54。
请参考图7,涂布且图案化光致抗蚀剂62,且进行n型杂质植入步骤以形成N+区64、66和68。植入的杂质可包括磷(phosphorous)及/或砷(arsenic)。优选以约大于1020ions/cm3的杂质浓度重掺杂n型杂质。N+区66和68分别作为低压n型阱区38和40的拾取区(pick-up region)。杂质植入后,移除光致抗蚀剂62。
在另一实施例中,N+区64、66和68可在形成P+区58和60之前形成,或在栅极介电质、栅极和栅极间隙壁形成之后形成。本领域技术人员可了解各个制造工艺步骤。
图8显示栅极介电质70、栅极72和栅极间隙壁74的形成。本领域技术人员可知栅极介电质70优选包括氧化硅,然而也可使用例如氮化硅,碳化硅,氮氧化硅或其组合等其它介电材料。栅极72优选包括掺杂多晶硅。在另一实施例中,栅极72可使用金属、金属氮化物、金属硅化物或其它导电材料。可优选全面性沉积介电层和移除不需要的部分以形成栅极间隙壁74。栅极介电质70、栅极72和栅极间隙壁74的详细制造工艺为公知,因此在此不做重复叙述。栅极72的边缘位于绝缘区50的上方。因此形成高压p型金属氧化物半导体(HVPMOS)元件76。
接着,对高压p型金属氧化物半导体(HVPMOS)元件76进行退火制造工艺,以使DNW区32和34中的杂质向介于DNW区32和34之间的基板区域78扩散。结果,在之后形成的结构中,DNW区32和34可以没有清楚的边界。然而,区域78具有比DNW区32和34低的p型杂质浓度(第一杂质浓度)。上述第一p型杂质浓度有少于二分之一的DNW区32和34中第二p型杂质浓度的趋势。第二p型杂质浓度很可能大于第一p型杂质浓度一个数量级(十倍)或超过一个数量级。在本发明的实施例中,当上述第一杂质浓度为1015ions/cm3时,第二杂质浓度则为1016ions/cm3。
本发明实施例的一项优点为DNW区32和34彼此隔开。另外,LVPW区44与LVNW区38隔开。结果,基板区域78具有较低的p型和n型杂质浓度。因此,可以分散高度集中的电场,因而可以增加HVPMOS元件76的击穿电压(breakdown voltage)。可以了解的是,HVPMOS元件76的击穿电压(breakdown voltage)与基板区域78的宽度S相关。宽度S增加时,HVPMOS元件76的击穿电压(breakdown voltage)会随之增加。利用本发明实施例所形成的HVPMOS样品元件,其击穿电压介于22.5V至30V之间。
图9和图10显示本发明的其它实施例。在图9中,在LVPW区44与DNW区34之间形成LVPW区46,且LVPW区46与DNW区34之间具有额外的间隙。在图10中,LVPW区46并不存在。
前述实施例具有非对称结构(asymmetric structure),其中位于阱区中的源极区和漏极区具有不同的导电类型。图11显示实施例的具有对称结构(symmetric structure)的HVPMOS,其中HVPMOS元件包括两个LVPW区80、82和介于两者之间的LVNW区84。类似于图8所示的实施例,DNW区32和34彼此隔开以增加HVPMOS元件的击穿电压。
虽然上述优选实施例显示HVPMOS元件的形成,但是本领域技术人员可了解形成高压n型金属氧化物半导体(HVNMOS)元件各别的形成步骤,且其具有与n型阱区36、38和40、p型阱区44、46和48、以及源/漏极区58和60等相反的导电类型(请参考图8)。图12显示本发明的另一实施例的高压n型金属氧化物半导体(HVNMOS)元件,其包括LVPW区90和92、LVNW区94和96。可以了解高压MOS元件具有各种不同的布局。然而,仍可应用本发明实施例的形成概念。类似地,可利用反转图11中掺杂区的导电类型以形成具有对称结构的HVNMOS元件。
虽然本发明已以优选实施例公开如上,然其并非用以限制本发明,本领域技术人员在不脱离本发明的精神和范围内,当可做些许变更与修饰,因此本发明的保护范围当视所附的权利要求书所界定的范围为准。
Claims (17)
1.一种半导体结构,包括:
基板;
第一阱区,位于该基板上,该第一阱区具有第一导电类型;
第二阱区,位于该基板上,且横向相邻于该第一阱区,该第二阱区具有相反于该第一导电类型的第二导电类型;
第三阱区,该第三阱区具有该第二导电类型,其中该第二阱区和该第三阱区彼此隔开;
第一深阱区,位于至少一部分的该第一阱区和该第二阱区下方,该第一深阱区具有该第二导电类型;
第二深阱区,位于该第三阱区下方,该第二深阱区具有该第二导电类型,其中该第二深阱区包围至少一部分的该第三阱区的侧壁和底部,且其中该第一深阱区和该第二深阱区被间隙隔开;
绝缘区,位于一部分该第一阱区中,从该第一阱区的顶面延伸至该第一阱区中;
栅极介电质,从该第一阱区的上方延伸至该第二阱区的上方,其中一部分该栅极介电质位于该绝缘区的上方;以及
栅极,位于该栅极介电质上。
2.如权利要求1所述的半导体结构,其中该第一导电类型为p型,且该第二导电类型为n型。
3.如权利要求1所述的半导体结构,其中该第一导电类型为n型,且该第二导电类型为p型。
4.如权利要求1所述的半导体结构,其中位于该间隙中的第二导电类型杂质的第一杂质浓度低于位于该第一深阱区和该第二深阱区中的第二导电类型杂质的第二杂质浓度。
5.如权利要求4所述的半导体结构,其中该第一杂质浓度小于该第二杂质浓度超过一个数量级。
6.如权利要求1所述的半导体结构,其中该第一阱区、该第二阱区和该第三阱区之中每一个都为连续阱区,其具有均匀的杂质浓度。
7.如权利要求1所述的半导体结构,还包括第四阱区,位于该第一阱区和该第三阱区之间,该第四阱区具有该第一导电类型,其中该第四阱区与该第一阱区和该第三阱区隔开。
8.如权利要求7所述的半导体结构,其中该第四阱区与该第二深阱区相邻。
9.如权利要求7所述的半导体结构,其中该第四阱区与该第二深阱区隔开。
10.如权利要求1所述的半导体结构,其中该第一阱区和该第二阱区为高压阱区。
11.如权利要求1所述的半导体结构,还包括第四阱区,位于该第二阱区相对于该第一阱区的相反侧,该第四阱区具有该第一导电类型,其中该第四阱区相邻于该第二阱区,且该栅极介电质延伸至该第四阱区上方。
12.如权利要求1所述的半导体结构,还包括:
第一源/漏极区,位于该第一阱区中,且相邻于该绝缘区;以及
第二源/漏极区,位于该第二阱区中,且相邻于该栅极介电质。
13.一种半导体结构的形成方法,包括下列步骤:
提供基板;
在该基板上形成第一阱区,该第一阱区具有第一导电类型;
在该基板上形成第二阱区,且横向相邻于该第一阱区,该第二阱区具有相反于该第一导电类型的第二导电类型;
在该基板上形成第三阱区,该第三阱区具有该第二导电类型,其中该第二阱区和该第三阱区彼此隔开;
在至少一部分的该第一阱区和该第二阱区下方形成第一深阱区,该第一深阱区具有该第二导电类型;
在该第三阱区下方形成第二深阱区,该第二深阱区具有该第二导电类型,其中该第二深阱区包围至少一部分的该第三阱区的侧壁和底部,且其中该第一深阱区和该第二深阱区被间隙隔开;
在一部分该第一阱区中形成绝缘区,且该绝缘区从该第一阱区的顶面延伸至该第一阱区中;
形成栅极介电质,该栅极介电质从该第一阱区的上方延伸至该第二阱区的上方,其中一部分该栅极介电质位于该绝缘区的上方;以及
在该栅极介电质上形成栅极。
14.如权利要求13所述的半导体结构的形成方法,其中该第二阱区和该第三阱区同时形成,且其中该第一深阱区和该第二深阱区同时形成。
15.如权利要求13所述的半导体结构的形成方法,其中该第一阱区与第一低压金属氧化物半导体元件的第一低压阱区同时形成,且该第二阱区和第三阱区与第二低压金属氧化物半导体元件的第二低压阱区同时形成。
16.如权利要求13所述的半导体结构的形成方法,还包括在形成该第一深阱区和该第二深阱区步骤之后,该第一深阱区和该第二深阱区中的杂质扩散进入该间隙中,且其中从该第一深阱区和该第二深阱区扩散的原子浓度具有第一杂质浓度,其值低于该第一深阱区和该第二深阱区中的第二杂质浓度。
17.如权利要求16所述的半导体结构的形成方法,其中该第一杂质浓度小于该第二杂质浓度超过一个数量级。
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US7968936B2 (en) * | 2007-12-31 | 2011-06-28 | Texas Instruments Incorporated | Quasi-vertical gated NPN-PNP ESD protection device |
US7863645B2 (en) * | 2008-02-13 | 2011-01-04 | ACCO Semiconductor Inc. | High breakdown voltage double-gate semiconductor device |
TWI364800B (en) | 2008-06-30 | 2012-05-21 | Vanguard Int Semiconduct Corp | Semiconductor device and method for fabricating the same, bipolar-cmos (complementary metal-oxide-semiconductor transistor)-dmos (double diffused metal-oxide-semiconductor transistor) and method for fabricating the same |
CN101635260B (zh) * | 2008-07-24 | 2012-04-04 | 世界先进积体电路股份有限公司 | 半导体装置、晶体管及其制造方法 |
US20110081760A1 (en) * | 2009-10-01 | 2011-04-07 | Bo-Jui Huang | Method of manufacturing lateral diffusion metal oxide semiconductor device |
US8704312B2 (en) * | 2010-01-05 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage devices and methods of forming the high voltage devices |
TWI405250B (zh) * | 2010-04-13 | 2013-08-11 | Richtek Technology Corp | 半導體元件雜質濃度分布控制方法與相關半導體元件 |
CN102222609B (zh) * | 2010-04-16 | 2013-07-31 | 立锜科技股份有限公司 | 半导体元件杂质浓度分布控制方法与相关半导体元件 |
US8525258B2 (en) * | 2010-06-17 | 2013-09-03 | Richtek Technology Corporation, R.O.C. | Method for controlling impurity density distribution in semiconductor device and semiconductor device made thereby |
US9209098B2 (en) | 2011-05-19 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | HVMOS reliability evaluation using bulk resistances as indices |
CN103456784B (zh) * | 2012-05-30 | 2017-02-15 | 上海华虹宏力半导体制造有限公司 | 高压p型ldmos器件及制造方法 |
US8896061B2 (en) * | 2012-09-14 | 2014-11-25 | Macronix International Co., Ltd. | Field device and method of operating high voltage semiconductor device applied with the same |
US9583564B2 (en) * | 2013-03-15 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structure |
US9006825B1 (en) * | 2013-09-27 | 2015-04-14 | Mediatek Inc. | MOS device with isolated drain and method for fabricating the same |
TWI804940B (zh) | 2020-08-14 | 2023-06-11 | 力旺電子股份有限公司 | 電荷泵電路 |
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