CN100563029C - 半导体结构 - Google Patents
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Abstract
本发明提供一种半导体结构,包括:衬底;第一阱区,位于上述衬底上,具有第一导电类型;第二阱区,位于上述衬底上,具有与上述第一导电类型相反的第二导电类型;缓冲区,介于上述第一阱区与上述第二阱区之间,且邻接于上述第一阱区和上述第二阱区;隔离区,位于一部分上述第一阱区中,从上述第一阱区的顶面延伸至上述第一阱区中;栅极介电质,从上述第一阱区的上方延伸至上述第二阱区的上方,其中一部分上述栅极介电质位于上述隔离区的上方;栅极,位于上述栅极介电质上。本发明用内部净杂质浓度低的缓冲区来隔开n型阱区和p型阱区,由此改善了HVMOS元件的性能;并降低衬底电流从而增加了HVMOS元件的寿命。
Description
技术领域
本发明涉及一种半导体元件,特别涉及一种金属氧化物半导体(metal-oxide-semiconductor,MOS)元件,又特别涉及一种高压MOS元件的结构及其制造方法。
背景技术
高压金属氧化物半导体(high-voltage metal-oxide-semiconductor,HVMOS)元件广泛地应用于例如中央处理器电源供应器(CPU powersupply)、电源管理系统(power management)、交流/直流转换器(AC/DCconverter)等许多电子元件中。HVMOS元件典型地包括漏极区和包围漏极区的横向扩散漏极区。横向扩散漏极区典型为阱区,其具有较漏极区低的掺杂浓度,因此具有高击穿电场。
图1显示公知的高压n型金属氧化物半导体(HVNMOS)元件2,其包括栅极氧化层10、位于栅极氧化层10上的栅极12、位于n型阱(n-well)区4中的漏极区6以及位于p型阱(p-well)区7中的源极区8。浅沟槽隔离(shallow trench isolation,STI)区14将漏极区6与栅极12隔开,所以可外加高的漏极对栅极电压(drain-to-gate voltage)。
可知高电场典型地产生于界面区域(interface region)。对于HVNMOS元件2来说,当在漏极6与源极8之间施加电压时,在接近PN结(p-n junction)16处会产生高电场,这会变成HVNMOS元件2的弱点。高电场的产生会导致HVNMOS元件2的击穿电压下降。当元件尺寸变小时,电场会变得更高,上述问题会进一步恶化。
因此有需要一种新的方法,其可降低PN结的电场,以改善HVMOS元件的击穿电压。
发明内容
为达成发明的上述目的,本发明提供一种半导体结构,包括:衬底;第一阱区,位于上述衬底上,具有第一导电类型;第二阱区,位于上述衬底上,具有与上述第一导电类型相反的第二导电类型;缓冲区,介于上述第一阱区与上述第二阱区之间,且邻接于上述第一阱区和上述第二阱区;隔离区,位于一部分上述第一阱区中,从上述第一阱区的顶面延伸至上述第一阱区中;栅极介电质,从上述第一阱区的上方延伸至上述第二阱区的上方,其中一部分上述栅极介电质位于上述隔离区的上方;栅极,位于上述栅极介电质上。
上述半导体结构中,该缓冲区可为该第一阱区和该第二阱区形成的重叠区。
上述半导体结构中,该缓冲区可为介于该第一阱区与该第二阱区之间的间隔区。
上述半导体结构还可包括:第三阱区,位于该衬底的上方,该第三阱区具有第一导电类型,且位于该第二阱区中与该第一阱区相对的另一侧,其中该栅极介电质延伸至该第三阱区的上方。
上述半导体结构还可包括:第二缓冲区,介于该第二阱区与该第三阱区之间。
上述半导体结构中,该第一缓冲区和该第二缓冲区其中之一可为重叠区,而另一缓冲区为介于相邻阱区之间的间隔区。
上述半导体结构中,该缓冲区的宽度可介于至3μm之间。
上述半导体结构中,该宽度还可介于0.3μm至0.5μm之间。
上述半导体结构中,该第一导电类型可选自包含n型及p型的族群。
上述半导体结构还可包括:漏极区,位于该第一阱区中,且邻接该绝缘区;以及源极区,位于该第二阱区中,且邻近该栅极的边缘,其中该漏极区和该源极区具有该第一导电类型。
为达成发明的另一目的,本发明提供一种半导体结构,包括:衬底;第一阱区,位于上述衬底上,具有第一导电类型;第二阱区,位于上述衬底上,具有与上述第一导电类型相反的第二导电类型,其中上述第一阱区和上述第二阱区具有重叠区;绝缘区,从上述第一阱区的顶面延伸至上述第一阱区中;栅极介电质,从上述第一阱区的上方延伸至上述第二阱区的上方,其中上述栅极介电质的边缘位于上述绝缘区的正上方;栅极,位于上述栅极介电质上。
上述半导体结构中,该宽度还可介于0.3μm至0.5μm之间。
为达成发明的又一目的,本发明提供一种半导体结构,包括:衬底;第一阱区,位于上述衬底上,具有第一导电类型的第一杂质;第二阱区,位于上述衬底上,具有第二导电类型的第二杂质,上述第二导电类型与上述第一导电类型相反,其中上述第一阱区与上述第二阱区之间具有间隔区;绝缘区,位于一部分上述第一阱区中,从上述第一阱区的顶面延伸至上述第一阱区中;栅极介电质,从上述第一阱区的上方延伸至上述第二阱区的上方,其中上述栅极介电质的边缘位于上述绝缘区的正上方;栅极,位于上述栅极介电质上。上述半导体结构中,该间隔区的宽度可介于至3μm之间。
上述半导体结构中,该宽度还可介于0.3μm至0.5μm之间。
为达成发明的又一目的,本发明提供一种半导体结构的形成方法,包括:提供衬底;在上述衬底上形成第一阱区,上述第一阱区具有第一导电类型;在上述衬底上形成第二阱区,上述第二阱区具有与上述第一导电类型相反的第二导电类型,其中形成缓冲区,上述缓冲区邻接上述第一阱区和上述第二阱区;在一部分上述第一阱区中形成隔离区,且上述隔离区从上述第一阱区的顶面延伸至上述第一阱区中;形成栅极介电质,上述栅极介电质从上述第阱区的上方延伸至上述第二阱区的上方,其中一部分上述栅极介电质位于上述隔离区的上方;在上述栅极介电质上形成栅极。
为达成发明的又一目的,本发明提供一种半导体结构的形成方法,包括:提供衬底;在上述衬底上形成第一阱区,上述第一阱区具有第一导电类型;在上述衬底上形成第二阱区,上述第二阱区具有与上述第一导电类型相反的第二导电类型,其中上述第一阱区与上述第二阱区之间具有重叠区;在一部分上述第一阱区中形成隔离区,且上述隔离区从上述第一阱区的顶面延伸至上述第一阱区中;形成栅极介电质,上述栅极介电质从上述第一阱区的上方延伸至上述第二阱区的上方,其中一部分上述栅极介电质位于上述隔离区的上方;在上述栅极介电质上形成栅极。
介于p型阱区和n型阱区之间的缓冲区提升p型阱区和n型阱区界面区域的击穿电场。因此分别提升高压元件的击穿电压。
本发明用内部净杂质浓度(net impurity concentration)低的缓冲区来隔开n型阱区和p型阱区,由此改善了HVMOS元件的性能;并降低衬底电流从而增加了HVMOS元件的寿命。
附图说明
图1为公知的HVNMOS元件。
图2至图7为本发明第一实施例的工艺剖面图,其中利用重叠n型阱和p型阱形成缓冲区。
图8至图9为本发明第二实施例的工艺剖面图,其中利用隔开n型阱和p型阱形成缓冲区。
图10为对称结构的实施例。
图11为公知高压MOS元件和本发明一实施例的衬底电流的比较图。
其中,附图标记说明如下:
2~公知HVNMOS元件;4~n型阱区;6~漏极区;7~p型阱区;8~源极区;10~栅极氧化层;12~栅极;14~浅沟槽隔离区;16~PN结;20~衬底;22、26、48、54~光致抗蚀剂;23~N+埋层;24、70、72~n型阱区;25~外延层;28、30、74~p型阱区;32、76、78~缓冲区;44~绝缘区;52~P+区;56、58~N+区;60~栅极介电质;62~栅极;64~栅极间隙壁;66~HVNMOS元件;80、82~曲线;92、94~低压p型阱区;C、W~宽度。
具体实施方式
以下利用图2至图7,更详细地说明本发明优选实施例。接着讨论本发明不同的优选实施例。在本发明各实施例中,相同的符号表示相同的元件。
请参考图2,提供衬底20,衬底20优选包括例如硅、锗化硅(SiGe)或例如III-V族元素的半导体材料。衬底20可为块状材料或具有绝缘层上硅(silicon-on-insulator,SOI)的结构。优选以p型杂质对衬底20进行轻掺杂(lightly doped),然而也可用n型杂质来掺杂衬底20。
图2也显示n型阱区24的形成。首先涂布且图案化光致抗蚀剂22。在优选实施例中,n型阱区24是通过注入n型杂质形成的。举例来说,可注入磷(phosphorous)和/或鉮(arsenic)。n型阱区24优选为高压n型阱区,其具有较低的杂质浓度。在另一实施例中,n型阱区24为低压n型阱(low-voltagen-well,LVNW)区,其与低压PMOS元件(图中未示)的n型阱区同时形成。在一实施例中,n型阱区24的杂质浓度介于1014离子/cm3至1017离子/cm3之间。形成n型阱区24之后,除去光致抗蚀剂22。
请参考图3A,涂布光致抗蚀剂26,且注入例如硼(boron)和/或铟(indium)的p型杂质以形成p型阱区28和30。p型阱区28和30为高压p型阱区,其具有较低的杂质浓度。在另一实施例中,p型阱区28和30为低压p型阱(low-voltage p-well,LVPW)区,其与低压NMOS元件(图中未示)的p型阱区同时形成。在一实施例中,p型阱区28和30的杂质浓度介于1014离子/cm3至1017离子/cm3之间。形成p型阱区28和30之后,除去光致抗蚀剂26。
上述讨论中,p型阱区28和30和n型阱区24是利用离子注入衬底20形成的。在另一实施例中,以外延成长来形成阱区。如图3B所示,在一实施例中,在衬底20的顶部区域中形成N+埋层(N+buried layer,NBL)23。N+埋层23优选为在衬底20的顶面中注入杂质或原位掺杂(in-situ doping)杂质形成来。举例来说,可注入或原位掺杂磷和/或鉮,其杂质浓度介于1016离子/cm3至1018离子/cm3之间。
在N+埋层23上外延成长外延层25。外延层25优选包括例如硅半导体等材料,且更优选包括与衬底20相同的材料,且优选以p型或n型其中之一的杂质进行掺杂。假设掺杂p型杂质,则其杂质浓度与p型阱区28和30的预期杂质浓度相同。然后,形成且图案化光致抗蚀剂层(图中未示),暴露出区域24。接着进行n型杂质注入步骤。注入的n型杂质中和外延层25中的p型杂质,且将区域24反转为n型阱区24。而未掺杂的外延层区域形成p型阱区28和30。在另一实施例中,可在成长外延层25时掺杂n型杂质,且注入p型杂质。
图4显示绝缘区(insulating region)44的形成。在优选实施例中,是以形成浅沟槽、在沟槽中填入例如高密度等离子体氧化物(HDP oxide)的介电材料、且进行化学机械研磨以除去过量介电材料的方式来形成绝缘区44。最后形成的浅沟槽隔离(shallow trench isolation,STI)区为绝缘区44。在其他实施例中,在前述形成的结构上方形成例如氮化硅的掩模层。然后图案化掩模层以形成开口。接着进行氧化步骤,以在开口中形成绝缘区(也可称为场氧化物)44。
请参考图5,涂布且图案化光致抗蚀剂48。进行p型杂质注入步骤以形成P+区52。P+区52优选包括硼和/或其他p型杂质,且以约大于1020离子/cm3的杂质浓度进行重掺杂(heavily doped)来形成。P+区52可做为p型阱区28的拾取区(pick-up region)。杂质注入后,除去光致抗蚀剂48。
请参考图6,涂布且图案化光致抗蚀剂54,且进行n型杂质注入步骤以形成N+区56和58。注入的杂质可包括磷和/或鉮。优选以约大于1020离子/cm3的杂质浓度将n型杂质重掺杂,从而形成N+区56和58。N+区56和58分别做为漏极接触区(drain contact region)和源极区(source region)。然后,除去光致抗蚀剂54。
在另一实施例中,N+区56和58可在形成P+区52之前形成,或在栅极介电质、栅极和栅极间隙壁形成之后形成。本领域技术人员可了解各工艺步骤。
图7显示栅极介电质60、栅极62和栅极间隙壁64的形成。本领域技术人员可知栅极介电质60优选包括氧化硅,然而也可使用例如氮化硅,碳化硅,氮氧化硅或其组合等其他介电材料。栅极62优选包括掺杂多晶硅。在另一实施例中,栅极62可使用金属、金属氮化物、金属硅化物或其他导电材料。可全面性沉积介电层并除去不需要的部分以形成栅极间隙壁64。栅极介电质60、栅极62和栅极间隙壁64的详细工艺是公知的,因此在此不做重复叙述。栅极62的边缘位于n型阱区24中绝缘区44的正上方。因此形成高压n型金属氧化物半导体元件66。
图8至图9显示本发明的第二实施例。除了缓冲区32为介于p型阱区28与n型阱区24之间的间隔区之外,此实施例类似于如图7所示的实施例。在一实施例中,形成如图2所示的结构。接着,如图8所示,形成用来形成p型阱区28和30的光致抗蚀剂26。因此p型阱区28和n型阱区24被隔开以形成缓冲区32。可了解n型阱区24和p型阱区28中的杂质很可能会扩散进入缓冲区32中。然而,扩散的杂质浓度会分别低于n型阱区24和p型阱区28的杂质浓度。在一实施例中,n型和p型杂质扩散进入缓冲区32且在缓冲区32中形成PN结。n型和p型杂质浓度的比例很可能分别小于n型阱区24和p型阱区28杂质的五分之一,甚至小于0.1。通过使得缓冲区32具有适当的宽度W,上述比例甚至可小于0.01。类似于第一实施例,缓冲区32的宽度W优选介于至3μm之间,更优选介于0.3μm至0.5μm之间。
前述实施例具有非对称结构(asymmetric structure),其中位于阱区中的源极区和漏极区具有不同的导电类型。图10显示一实施例的具有对称结构(symmetric structure)的HVNMOS,其中HVNMOS元件包括两个n型阱区70、72和介于两者之间的p型阱区74。类似于图7显示的实施例,形成缓冲区76和78,其中每一个缓冲区76和78可为相邻的p型阱区和n型阱区的重叠区或间隔区。在另一实施例中,p型阱区74仅重叠于(或隔开)n型阱区70和72其中之一,因此当p型阱区74与其他相邻的n型阱区形成公知界面时,仅会形成缓冲区76和78其中之一。
虽然上述优选实施例显示HVNMOS元件的形成,本领域技术人员可了解形成高压p型金属氧化物半导体(HVPMOS)元件的各形成步骤,其具有与n型阱区24、p型阱区26和30、N+区56和58等相反的导电类型(请参考图7和图9)。可了解高压MOS元件具有各种不同的布局。然而,仍可应用本发明实施例的形成概念。类似地,可通过将图10中掺杂区的导电类型反转,来形成具有对称结构的HVPMOS元件。
除了形成HVMOS元件之外,形成缓冲区以影响电场分布的概念,可用以形成例如二极管(diode)的其他元件。借助介于p型区和n型区之间的PN结形成缓冲区,可以提升击穿电压。
本发明实施例的一项优点为利用缓冲区32来隔开n型阱区24和p型阱区28。在缓冲区32内部的净杂质浓度低。如图7所示的实施例中,缓冲区32中的p型杂质与n型杂质互相中和,因此降低净杂质浓度。如图9所示的一实施例中,缓冲区32并非由形成阱区时的掺杂形成,因此净杂质浓度低。所以,在界面形成的缓冲区32的净杂质浓度较低,且因此改善HVMOS元件的性能。实验结果显示,本发明实施例的击穿电压提升超过具有类似结构的公知HVMOS元件(除了没有形成缓冲区之外)3V至5V的击穿电压。另外,如图11所示,本发明实施例的衬底电流(Isub)明显低于公知的HVMOS元件。曲线80显示本发明实施例的衬底电流(Isub),其最大值约为2×10-6(即2E-6)A/μm。曲线82显示公知HVMOS元件的衬底电流(Isub),其最大值约为6.5×10-6(6.5E-6)A/μm。本领域技术人员可知,HVMOS元件的寿命与衬底电流强烈相关。若衬底电流降低,则HVMOS元件的寿命就会增加。
虽然本发明已通过优选实施例公开如上,然而其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,应可做一定的改动与修改,因此本发明的保护范围应以所附权利要求范围为准。
Claims (11)
1.一种半导体结构,包括:
衬底;
第一阱区,位于该衬底上,该第一阱区具有第一导电类型;
第二阱区,位于该衬底上,该第二阱区具有与该第一导电类型相反的第二导电类型;
第三阱区,位于该衬底的上方,该第三阱区具有第一导电类型,且位于该第二阱区中与该第一阱区相对的另一侧;
第一缓冲区,介于该第一阱区与该第二阱区之间,且邻接于该第一阱区和该第二阱区;
第二缓冲区,介于该第二阱区与该第三阱区之间,其中该第一缓冲区和该第二缓冲区其中之一为重叠区,而另一缓冲区为介于相邻阱区之间的间隔区;
绝缘区,位于一部分该第一阱区中,从该第一阱区的顶面延伸至该第一阱区中;
栅极介电质,从该第一阱区的上方延伸至该第二阱区的上方,其中一部分该栅极介电质位于该绝缘区的上方,其中该栅极介电质延伸至该第三阱区的上方;以及
栅极,位于该栅极介电质上。
3.如权利要求2所述的半导体结构,其中该宽度介于0.3μm至0.5μm。
4.如权利要求1所述的半导体结构,其中该第一导电类型选自包含n型及p型的族群。
5.如权利要求1所述的半导体结构,还包括:
漏极区,位于该第一阱区中,且邻接该绝缘区;以及
源极区,位于该第二阱区中,且邻近该栅极的边缘,其中该漏极区和该源极区具有该第一导电类型。
6.一种半导体结构,包括:
衬底;
第一阱区,位于该衬底上,该第一阱区具有第一导电类型的第一杂质;
第二阱区,位于该衬底上,该第二阱区具有与该第一导电类型相反的第二导电类型的第二杂质,其中该第一阱区和该第二阱区具有重叠区,其中位于该重叠区的该第一杂质和该第二杂质互相中和,以使该重叠区内部的净杂质浓度分别低于该第一阱区和该第二阱区的杂质浓度;
绝缘区,从该第一阱区的顶面延伸至该第一阱区中;
栅极介电质,从该第一阱区的上方延伸至该第二阱区的上方,其中该栅极介电质的边缘位于该绝缘区的正上方;以及
栅极,位于该栅极介电质上。
8.如权利要求7所述的半导体结构,其中该宽度介于0.3μm至0.5μm。
9.一种半导体结构,包括:
衬底;
第一阱区,位于该衬底上,该第一阱区具有第一导电类型的第一杂质;
第二阱区,位于该衬底上,该第二阱区具有第二导电类型的第二杂质,该第二导电类型与该第一导电类型相反,其中该第一阱区与该第二阱区之间具有间隔区;
绝缘区,位于一部分该第一阱区中,从该第一阱区的顶面延伸至该第一阱区中;
栅极介电质,从该第一阱区的上方延伸至该第二阱区的上方,其中该栅极介电质的边缘位于该绝缘区的正上方;以及
栅极,位于该栅极介电质上。
10.如权利要求9所述的半导体结构,其中该间隔区的宽度介于至3μm。
11.如权利要求10所述的半导体结构,其中该宽度介于0.3μm至0.5μm。
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US7816744B2 (en) * | 2008-07-09 | 2010-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate electrodes of HVMOS devices having non-uniform doping concentrations |
CN101635260B (zh) * | 2008-07-24 | 2012-04-04 | 世界先进积体电路股份有限公司 | 半导体装置、晶体管及其制造方法 |
US8921938B1 (en) | 2009-03-11 | 2014-12-30 | Marvell International Ltd. | Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wells |
US8575702B2 (en) * | 2009-11-27 | 2013-11-05 | Magnachip Semiconductor, Ltd. | Semiconductor device and method for fabricating semiconductor device |
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US9105721B2 (en) * | 2010-07-09 | 2015-08-11 | Magnachip Semiconductor, Ltd. | Semiconductor device and manufacturing method thereof |
CN102097485B (zh) * | 2011-01-27 | 2015-12-16 | 上海华虹宏力半导体制造有限公司 | Edmos晶体管及其制作方法 |
CN104835842A (zh) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | Ldmos器件 |
US9831340B2 (en) * | 2016-02-05 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and associated fabricating method |
CN109728069B (zh) * | 2017-10-27 | 2022-03-01 | 立锜科技股份有限公司 | 高压金属氧化物半导体元件及其制造方法 |
CN112563316A (zh) * | 2019-09-25 | 2021-03-26 | 瑞昱半导体股份有限公司 | 高压半导体装置以及其制作方法 |
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US6265752B1 (en) * | 1999-05-25 | 2001-07-24 | Taiwan Semiconductor Manufacturing, Co., Inc. | Method of forming a HVNMOS with an N+ buried layer combined with N well and a structure of the same |
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