CN101211789A - 制造dmos器件的方法 - Google Patents

制造dmos器件的方法 Download PDF

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CN101211789A
CN101211789A CNA2007103021349A CN200710302134A CN101211789A CN 101211789 A CN101211789 A CN 101211789A CN A2007103021349 A CNA2007103021349 A CN A2007103021349A CN 200710302134 A CN200710302134 A CN 200710302134A CN 101211789 A CN101211789 A CN 101211789A
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尹喆镇
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DB HiTek Co Ltd
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    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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Abstract

提供了一种制造半导体器件的方法，具体是制造DMOS器件的方法。所述半导体器件可以为漏极扩展的金属－氧化物－半导体(DMOS)器件。所述方法包括：在具有有源区的半导体衬底上形成栅极绝缘膜；在栅极绝缘膜上形成栅极；通过使用栅极作为掩模注入低浓度杂质离子在半导体衬底上形成低浓度源极区和低浓度漏极区；在栅极的侧面上形成隔离物；在半导体衬底上形成覆盖栅极和低浓度漏极区的一部分的硅化物区域阻挡(SAB)图案；和通过使用SAB图案作为掩模注入高浓度杂质离子在半导体衬底上形成高浓度源极区和高浓度漏极区。

Description

制造DMOS器件的方法
技术领域
本发明涉及制造漏极扩展的金属-氧化物-半导体(DMOS)器件的方法。
背景技术
由于扩展的漏极区，DMOS器件可通过扩展DMOS器件的沟道长度而使击穿电压提高。DMOS器件常常用于电源装置中。DMOS器件可包含半导体衬底、N阱或P阱、低浓度源极/漏极区、高浓度源极/漏极区、栅极、牺牲氧化物膜、隔离物、层间介电层和接触孔。在DMOS器件的制造中，光刻胶图案用于形成与栅极对准的高浓度源极/漏极。此外，实施工艺以形成与栅极对准的硅化物区域阻挡(SAB)(silicide areablock)氧化物膜图案。覆盖处理也要求精细的光工艺，并需要实施至少两次图案形成过程。
发明内容
根据本发明的实施方案提供制造半导体器件比如DMOS器件的方法。
在一个实施方案中，一种半导体器件包括衬底，在该衬底上形成阱结构、源极区、漏极区、栅极绝缘层、和栅极。所述方法包括提供衬底和利用硅化物区域阻挡(SAB)图案作为掩模在衬底的源极区和漏极区上实施离子注入工艺。
根据该实施方案的制造DMOS器件的方法包括：在具有有源区的半导体衬底上形成栅极绝缘膜；在栅极绝缘膜上形成栅极；通过使用栅极作为掩模注入低浓度杂质离子在半导体衬底上形成低浓度源极区和低浓度漏极区；在栅极的侧面上形成隔离物；在半导体衬底上形成硅化物区域阻挡(SAB)图案，覆盖栅极和低浓度漏极区的一部分；和通过使用SAB图案作为掩模注入高浓度杂质离子在半导体衬底上形成高浓度源极区和高浓度漏极区。
以下将参考附图讨论根据本发明的一种或多种实施方案的详细说明。根据详细说明、附图和所附的权利要求，其他特征对本领域技术人员而言显而易见。
附图说明
图1～7是显示根据本发明的一个实施方案制造DMOS器件的方法。
具体实施方式
以下，将参考附图详细说明根据本发明的实施方案。只要可能，相同的结构或元件由相同的附图标记表示。
此外，当层(膜)、区域、图案或结构描述为形成在另一层(膜)、区域、图案或结构上(on)、之上(above)、上方(over)、下(below)、之下(under)或下方(beneath)时，应理解所述层(膜)、区域、图案、或结构是与另一层(膜)、区域、图案或结构直接接触，或与另一层、区域、图案或结构间接接触，在其间形成有另外的层(膜)、区域、图案或结构。
图1-7说明对应于制造DMOS器件的方法的截面图。DMOS器件可包括漏极扩展的P-MOS器件以及漏极扩展的N-MOS器件。
参考图1，提供半导体衬底10，在该半导体衬底10上形成有器件隔离区(未显示)和有源区(未显示)。通过在半导体衬底10中注入杂质离子在半导体衬底10上形成阱结构11，例如P-阱或N-阱。在一个实施方案中，半导体衬底10可以为注入P型或N型杂质离子的硅衬底。此外，在具有有源区的半导体衬底10上顺序沉积栅极绝缘膜20和栅极导电层30。
参考图2，在栅极导电层30上形成光刻胶膜(未显示)。可以曝光和显影光刻胶膜以形成光刻胶图案(未显示)。可以通过使用光刻胶图案作为蚀刻掩模来蚀刻栅极导电层30，从而形成栅极31。此外，氧化栅极31的表面以形成牺牲氧化物膜32。
参考图3，使用栅极31作为掩模在阱结构11中注入低浓度杂质离子，从而形成低浓度漏极区12和低浓度源极区14。在一个实施方案中，低浓度漏极区12可以形成为具有比低浓度源极区14的长度更长的长度。
参考图4，在所得结构上沉积隔离物绝缘层(未显示)之后，可以实施回蚀刻工艺以在栅极31的侧面上形成隔离物40。在一个实施方案中，隔离物绝缘层可包含例如由氮化物材料制成的氮化物膜。
参考图5，可以在所得结构上形成硅化物区域阻挡(SAB)氧化物膜(未显示)。此外，可以在SAB氧化物膜上涂敷光刻胶膜(未显示)。可以曝光和显影光刻胶膜以形成覆盖靠近低浓度漏极区12的栅极31的上表面的一部分和低浓度漏极区12的一部分的光刻胶图案(未显示)。此外，可以使用光刻胶图案(未显示)作为蚀刻掩模来实施蚀刻工艺以形成SAB氧化物膜图案P。SAB氧化物膜图案P覆盖靠近低浓度漏极区12的栅极31的上表面的一部分和低浓度漏极区12的一部分。在一个实施方案中，如果SAB氧化物膜图案P的长度太小，则由于低浓度漏极区12的小的长度，DMOS器件的击穿电压可能不增加。另一方面，如果SAB氧化物膜图案P太长，击穿电压可能增加，然而，半导体器件的集成性能可能变差。因此，应该适当控制SAB氧化物膜图案P的长度。
参考图6，使用SAB氧化物膜图案P作为掩模注入高浓度杂质离子以在阱结构11中形成高浓度源极区15和高浓度漏极区13。
参考图7，在形成高浓度源极区15和漏极区13之后，可以在具有SAB氧化物膜图案P的所得结构上实施硅化物工艺(silicide process)，以在高浓度源极区15上、在栅极31上表面的一部分上、和在高浓度漏极区13上形成硅化物层21。此外，可以在所得结构上沉积层间介电层(未显示)。此外，可以在层间介电层上形成接触孔(未显示)，并可以实施通常的后续工艺，从而制造DMOS器件。
如上所述，在根据本发明的一个实施方案中，可以在单个光工艺中形成高浓度源极/漏极区上的掩模图案和硅化物区域阻挡(SAB)氧化物膜图案，使得可降低制造DMOS器件的时间和成本。
在该说明书中对“一个实施方案”、“实施方案”、“实例实施方案”等的任何引用，表示与所述实施方案相关的具体的特征包含于与本发明一致的至少一个实施方案中。在说明书不同地方出现的这些术语不必都涉及相同的实施方案。另外，与任何实施方案相关地记载具体特征时，认为在本领域技术人员的范围内能够实现与其他的实施方案相关的这些特征。
尽管已经参考许多说明性的实施方案描述了根据本发明的实施方案，应理解本领域技术人员可以知道很多其它的改变和/或实施方案，这将落入所附权利要求的精神和范围内。此外，在所附权利要求的范围内，本发明主题的组合排列的构件和/或布置可能有不同的变化和改变。除构件和/或结构的变化和改变之外，对本领域技术人员而言，可替代的用途会显而易见。

Claims (13)

1.一种制造半导体器件的方法，包括：
在具有有源区的半导体衬底上形成栅极绝缘膜；
在所述栅极绝缘膜上形成栅极；
通过使用所述栅极作为掩模注入低浓度杂质离子，在所述半导体衬底上形成低浓度源极区和低浓度漏极区；
在所述栅极的侧面上形成隔离物；
在所述半导体衬底上形成覆盖所述栅极和所述低浓度漏极区的一部分的硅化物区域阻挡(SAB)图案；和
通过使用所述SAB图案作为掩模注入高浓度杂质离子，在所述半导体衬底上形成高浓度源极区和高浓度漏极区。
2.权利要求1的方法，其中所述隔离物包括氮化物膜。
3.权利要求1的方法，其中所述SAB图案覆盖靠近所述低浓度漏极区的所述栅极的上表面的一部分。
4.权利要求1的方法，其中所述SAB图案覆盖所述低浓度漏极区的一部分。
5.权利要求1的方法，其中所述SAB图案覆盖靠近所述低浓度漏极区的所述栅极的上表面的一部分和所述低浓度漏极区的一部分。
6.权利要求1的方法，还包括：
在形成所述高浓度源极区和所述高浓度漏极区之后，在所得结构上进行硅化物工艺以在所述高浓度源极区上、在所述栅极的上表面的一部分上和在所述高浓度漏极区上形成硅化物层。
7.一种制造具有衬底的半导体器件的方法，在所述衬底上形成有阱结构、源极区、漏极区、栅极绝缘层和栅极，所述方法包括提供所述衬底，和利用硅化物区域阻挡(SAB)图案作为掩模在所述衬底的所述源极区和所述漏极区上实施离子注入工艺。
8.权利要求7的方法，其中实施所述离子注入工艺包括利用所述SAB图案作为掩模形成高浓度源极区和高浓度漏极区。
9.权利要求8的方法，其中形成所述高浓度源极区和高浓度漏极区包括利用覆盖低浓度漏极区和低浓度源极区的一部分的所述SAB图案作为掩模来注入高浓度杂质离子。
10.权利要求7的方法，其中所述SAB图案覆盖靠近所述漏极区的所述栅极的上表面的一部分和所述低浓度漏极区的一部分。
11.权利要求7的方法，还包括利用所述SAB图案作为掩模，在所述源极区上、在所述栅极的上表面的一部分上和在所述漏极区上形成硅化物层。
12.权利要求7的方法，其中所述半导体器件包括具有漏极扩展N-型MOS结构的DMOS器件。
13.权利要求7的方法，其中所述半导体器件包括具有漏极扩展P-型MOS结构的DMOS器件。
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