CN101170072A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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Abstract
本发明公开一种半导体器件,其特征在于包括以下部件的结构:半导体芯片,其上形成有电极片;凸点,其形成于所述各个电极片上并具有凸出部分;绝缘层,其形成于所述半导体芯片上;以及导电图案,其与所述凸点连接,其中,所述凸出部分的末端插入所述导电图案中,并且所述插入的末端被平坦化。
Description
技术领域
本发明涉及利用凸点的芯片尺寸封装所适用的半导体器件以及用于制造半导体器件的方法。
背景技术
已经提出了各种半导体芯片的封装结构。例如,伴随着封装件的小型化,已经提出了一种称为芯片尺寸封装件的结构,其中在半导体芯片的器件制造面的钝化层(保护层)上形成再配线(用于封装目的的配线)。
关于芯片尺寸封装件,已经提出例如一种用于通过以下方式形成封装件(半导体器件)的方法,即:借助于接合引线在半导体芯片的电极片上形成凸点,并且形成与凸点连接的再配线图案(例如参见专利文献1:JP-A-9-64049)。
然而,在结合JP-A-9-64049所描述的方法中,当通过接合形成与凸点连接的再配线时,会出现需要调整(调平)凸点高度的问题。
例如,利用例如接合机形成借助于接合引线形成的凸点。通过将接合引线从凸点连续地连接到电极片并且切割所接合的接合引线来形成凸点。
因此,利用接合引线形成的凸点距离形成凸点的平面(即电极片)的高度发生变化。这种变化造成在形成与凸点连接的再配线图案过程中的困难。为此,需要通过向凸点施加预定重量来修平凸点的步骤。
通常以晶片级进行这种凸点的修平(平坦化)(在通过切割将芯片分离成小块之前)。然而,在近来成为主流的直径为300mm的晶圆的情况下,当修平在晶圆面内形成的多个凸点时,会出现修平之后获得的高度变化增大的问题。
例如,当凸点的高度变化增大时,凸点及与其连接的再配线图案之间的连接状态出现变化,这转而又出现半导体器件(封装件)的可靠性降低的问题。
此外,在结合JP-A-9-64049所描述的方法中,形成绝缘层以便覆盖凸点。因此,需要研磨绝缘层以便使凸点露出的步骤。为了在研磨步骤之后形成再配线图案,当采用非电解电镀技术时,需要粗化绝缘层的表面的处理(所谓的去污处理)。因此,形成电镀层的处理变得复杂。这转而增加了制造半导体器件(封装件)的成本。
通过溅射或CVD形成导电层也是可行的。然而,该方法需要昂贵的具有真空处理容器的膜生长装置,这也会增加制造成本。因而该方法是不现实的。
发明内容
因此,本发明所要迎接的集中挑战是提供一种新颖、实用的解决上述问题的半导体器件以及提供一种用于制造半导体器件的方法。
本发明所要迎接的具体挑战是提供一种可以以低成本制造的高度可靠的半导体器件以及用于制造半导体器件的方法。
从本发明的第一观点来看,通过一种用于制造半导体器件的方法可以解决上述问题,该方法包括:第一步骤,其在电极片上形成具有凸出部分的凸点,所述电极片形成在基板的与半导体芯片对应的区域中;第二步骤,其在所述基板上形成绝缘层和导电层;第三步骤,其挤压所述导电层,从而压制所述导电层上露出的所述凸出部分的末端;第四步骤,其通过电解电镀形成与所述凸点连接的导电图案,在电解电镀过程中,把所述导电层当作供电层(feeding layer);以及第五步骤,其将所述基板分离成单独的小块。
从本发明的第二观点来看,通过一种半导体器件可以解决上述问题,该半导体器件包括:半导体芯片,其上形成有电极片;凸点,其形成于所述各个电极片上并具有凸出部分;绝缘层,其形成于所述半导体芯片上;以及导电图案,其与所述凸点连接,其中,所述凸出部分的末端插入所述导电图案中,并且所述插入的末端被平坦化。
本发明能够提供一种可以以低成本制造的高度可靠的半导体器件以及用于制造半导体器件的方法。
附图说明
图1是示出第一实施例的半导体器件的视图;
图2是图1的局部放大图;
图3A是示出用于制造第一实施例的半导体器件的方法的视图(部分1);
图3B是示出用于制造第一实施例的半导体器件的方法的视图(部分2);
图3C是示出用于制造第一实施例的半导体器件的方法的视图(部分3);
图3D是示出用于制造第一实施例的半导体器件的方法的视图(部分4);
图3E是示出用于制造第一实施例的半导体器件的方法的视图(部分5);
图3F是示出用于制造第一实施例的半导体器件的方法的视图(部分6);
图3G是示出用于制造第一实施例的半导体器件的方法的视图(部分7);
图3H是示出用于制造第一实施例的半导体器件的方法的视图(部分8);
图3I是示出用于制造第一实施例的半导体器件的方法的视图(部分9);
图3J是示出用于制造第一实施例的半导体器件的方法的视图(部分10);
图3K是示出用于制造第一实施例的半导体器件的方法的视图(部分11);
图3L是示出用于制造第一实施例的半导体器件的方法的视图(部分12);
图3M是示出用于制造第一实施例的半导体器件的方法的视图(部分13);
图4A是示出用于制造第一实施例的半导体器件的方法的视图(部分14);
图4B是示出用于制造第一实施例的半导体器件的方法的视图(部分15);
图4C是示出用于制造第一实施例的半导体器件的方法的视图(部分16);
图4D是示出用于制造第一实施例的半导体器件的方法的视图(部分17);
图4E是示出用于制造第一实施例的半导体器件的方法的视图(部分18);
图5是示出用于制造第一实施例的半导体器件的方法的修改例的视图(部分1);以及
图6是示出用于制造第一实施例的半导体器件的方法的修改例的视图(部分2)。
具体实施方式
用于制造本发明的半导体器件的方法包括:第一步骤,其在基板的与半导体芯片对应的区域中形成的电极片上形成具有凸出部分的凸点;第二步骤,其在所述基板上形成绝缘层和导电层;第三步骤,其挤压所述导电层,从而压制所述导电层上露出的所述凸出部分的末端;第四步骤,其通过电解电镀形成与所述凸点连接的导电图案,在电解电镀过程中,把所述导电层当作供电层;以及第五步骤,其将所述基板分离成单独的小块。
在制造半导体器件的方法中,挤压导电层,并压制导电层上露出的凸点的末端。因此,凸出部分的末端被压制在导电层上,并且凸点和导电层之间的接触面积增大,从而保证了凸点和导电层之间的连接可靠性。
根据该方法,凸出部分的末端被压制在导电层上,因此凸点和导电层之间的电连接可靠性不容易受到凸点(凸出部)的高度变化的影响。因此,可以利用凸点通过简单方法形成具有优良的连接可靠性的再配线图案,该凸点利用例如接合(接合引线)形成并涉及较大的高度变化。此外,在上述方法中,省去了使凸点的凸出部分从绝缘层露出的研磨步骤。
该方法的特征还在于,在第四步骤中,通过把导电层当作供电层,通过电解电镀在该导电层上形成导电图案变得容易。例如,在电解电镀方法中,需要用于将电力供给到待电镀表面的供电层(种晶层)。然而,迄今为止,已经采用例如非电解电镀法或溅射法作为形成这种供电层的方法。
然而,非电解电镀需要用于粗化绝缘层的表面的处理(所谓的去污处理),这使得形成电镀层的处理复杂化。此外,溅射法需要昂贵的具有真空处理容器的膜生长装置,这会增加制造成本。
同时,本发明的制造方法的特征在于,省去了在真空容器中进行的去污处理或溅射处理,从而能够通过简单方法容易地形成种晶层。因此,根据该方法,简化了制造半导体器件的方法,并最终降低了制造成本。
例如,在通过上述制造方法制造的半导体器件中,凸出部分的末端插入导电图案中,所插入的末端被压制,从而变得平坦。因而凸点和导电图案之间的连接可靠性变得优良。
接下来,在下面参照附图说明半导体器件的示例结构和用于制造半导体器件的示例方法。
第一实施例
图1是示意性示出本发明第一实施例的半导体器件的横截面视图。参照图1,本实施例的半导体器件100通常具有这样的结构,即:在形成电极片103的半导体芯片101的保护层(钝化层)102上形成有绝缘层105和导电图案106。在这种情况下,存在这样的情况,即:导电图案106称为所谓的再配线并用于封装半导体芯片101。绝缘层105由例如环氧基树脂形成。导电图案106通过堆叠由铜形成的第一导电图案107和第二导电图案108而形成。
在绝缘层105上形成的导电图案106与由例如金形成的凸点104的凸出部分(将在后面说明)连接。具体来说,导电图案106借助于凸点104与半导体芯片101的器件连接。凸点104利用例如引线接合器由接合引线形成。
在导电图案106上形成有焊料凸点110。在凸点110的周围形成有阻焊层(绝缘层)109,以便覆盖绝缘层105和导电图案106的一部分。
图2是以放大方式示出半导体器件100的部分A(凸点104的邻近区域)的示意性横截面视图。与前述区域相同的区域给予相同的附图标记。参照图2,凸点104与电极片103连接(接合),并且凸点104由基本上为圆形的凸点主体104A和从凸点主体104A凸出的凸出部分104B形成。
例如,凸点104利用引线接合器由金制接合引线形成。引线接合器连续进行接合引线与电极片103的接合以及所接合的接合引线的切割,从而形成与电极片103连接的凸点主体104A和从各个凸点主体104A凸出的凸出部分104B。
在本实施例的半导体器件100中,凸出部分104B由设置在凸出部分104B的末端的平坦末端部分104D以及位于末端部分104D和凸点主体104A之间的连接部分104C形成。本发明的半导体器件100的特征在于,凸出部分104B插入导电图案106中,并且所插入的末端部分104D压制成平坦形状。
例如,末端部分104D被压制在构成导电图案106并且一个堆叠在另一个顶部上的第一导电图案107和第二导电图案108之间,以便呈现平坦形状。因此,增大了凸点104和导电图案106之间的接触面积,增强了凸点104和导电图案106之间的电连接,并且提高了半导体器件100的可靠性。用于将凸点104与导电层106连接的结构的特征在于,与例如铜焊等现有技术的连接方法相比,可以更容易地形成该结构,并且连接可靠性较高。
第一导电图案107和第二导电图案108均由例如铜形成。然而,第一导电图案107和第二导电图案108也可以由除铜之外的材料形成。第一导电图案107和第二导电图案108也可以由不同的金属材料(合金材料)形成,并且导电图案106也可以实现为由不同材料制成的堆叠结构。
例如,当形成导电图案106时,将薄铜箔附着到绝缘层105上,从而形成与第一导电图案107和第二导电图案108中的第一导电图案107对应的薄导电层。随后,挤压薄铜箔,并压制从铜箔露出的凸出部分104B的末端。因此,形成平坦末端部分104D,并使末端部分104D和铜箔之间的电连接优良。接下来,基本要求是通过电解电镀形成与第二导电图案108对应的导电层,在电解电镀过程中,把铜箔当作供电层。
现在,将参照图3A至3M以及图4A至4D说明用于制造半导体器件的方法。在下列附图中,前述部件给予相同的附图标记,并且有时省略其重复说明。
首先,在图3A所示步骤中,通过公知方法制造基板101A,该基板具有多个制造器件的区域101a(排列成例如网格图案)。区域101a是与半导体芯片101对应的区域。在下述步骤中形成再配线(导电图案)之后,通过对基板101A进行切割,于是将半导体器件(半导体芯片101)分离成小块。
在制造器件的区域101a的器件制造面101b上形成电极片103。通过由例如SiN(Si3N4)形成的保护层(钝化层)102保护器件制造面101b中除电极片103之外的其余区域。
图3B是以放大方式示出图3A所示基板101A的一个区域101a的视图。结合图3B及随后的附图,通过以形成多个区域101a的基板101A的一个区域101a为例,说明制造半导体器件的方法。
在图3C所示步骤中,利用例如引线接合器在各个电极片103上由金制接合引线形成凸点104。图4A以放大方式示出图3C所示部分C(凸点104)的示意图。引线接合器连续进行接合引线与电极片103的连接以及所连接的接合引线的切割,从而形成与各个电极片103连接的凸点主体104A和从凸点主体104A凸出的凸出部分104B。
接下来,在图3D所示步骤中,在基板101A(保护层)102上形成由例如环氧基树脂材料制成的绝缘层105。通过例如层压(附着)或涂布形成绝缘层105。凸点104的凸出部分104B优选形成为在绝缘层105上露出。因此,优选使用例如称为NCF并且基本上不掺杂例如填料等硬度调整材料的软树脂材料作为绝缘层105。使用软树脂材料便于凸出部分104B从绝缘层105露出。
绝缘层105不限于上述材料,而可以利用各种绝缘材料(树脂材料)形成。例如,也可以采用通常使用的增层树脂(包含填料的环氧树脂)或称为ACF的树脂材料作为绝缘层105。
在图3E所示步骤中,将由例如薄铜膜制成的导电层107A附着到绝缘层105上。例如,在将导电层107A堆叠在铜制的支撑层111上的状态下(即在通过支撑层111支撑导电层107A的状态下),将导电层107A附着到绝缘层105上。
图4B给出以放大方式示出图3E所示部分E(凸点104的邻近区域)的示意图。在这一步骤中,通过凸点104将导电层107A推压成朝向支撑层111弯成弓形。
在图3F所示步骤中,去除支撑导电层107A的支撑层111。图4C给出以放大方式示出图3F所示部分F(凸点104的邻近区域)的示意图。
在图3G所示步骤中,挤压并加热一个堆叠在另一个的顶部上的导电层107A和绝缘层105。图4D给出以放大方式示出图3G所示部分G(凸点104的邻近区域)的示意图。在这一步骤中,首先推压导电层107A,从而凸点104的凸出部分104B穿透导电层107A。这样,露出凸出部分104B的末端。此外,通过挤压将露出的凸出部分104B的末端压制成平坦形状。因此,凸出部分104B由在凸出部分104B的末端形成的平坦末端部分104D以及位于末端部分104D和凸点主体104A之间的连接部分104C形成。
在这一步骤中,增大了凸点104和导电层107A之间的接触面积,保证了凸点104和导电层107A之间的电连接可靠性。此外,在这一步骤中,凸出部分104B的末端被压制在导电层107A上,因此凸点104和导电层107A之间的电连接可靠性不容易受到凸点104(凸出部分104B)的高度变化的影响。
因此,可以利用凸点104通过简单方法形成具有优良的连接可靠性的再配线图案,该凸点利用例如接合(接合引线)形成并具有较大的高度变化。在上述方法中,省去了使凸点104的凸出部分104B从绝缘层105露出的研磨步骤。
用于将凸点104与导电层106连接的方法的特征在于,该方法比利用铜焊的现有技术的连接方法更简单,并且该方法具有更高的连接可靠性。此外,导电层106在后述电解电镀步骤中用作供电层(种晶层)。
在这一步骤中,绝缘层105与导电层107A一起被挤压并加热,从而使绝缘层105固化(热固)。因此,绝缘层105和导电层107A之间的附着性变得优良。
在图3H至3J所示步骤中,通过电解电镀形成与凸点104连接的导电图案106,在电解电镀过程中,把导电层107A当作供电层(种晶层)。例如,可以使用减成法和半加成法作为形成导电图案106的方法。在本实施例中,将对减成法进行说明。减成法是用于对通过电镀形成的导电层进行图案蚀刻从而形成导电图案的方法。半加成法是用于通过使用掩模图案的图案电镀(pattern plating)形成导电图案的方法。
在图3H所示步骤中,通过电解电镀在导电层107A上堆叠例如铜制的导电层108A,在电解电镀过程中,把导电层107A当作供电层。图4E是以放大方式示出图3H所示部分H(凸点104的邻近区域)的示意图。
在这一步骤中,用通过电解电镀形成的导电层108A覆盖导电层107A和在导电层107A上露出的平坦末端部分104D。具体来说,将末端部分104D夹在导电层107A和导电层108A之间。
在图3工所示步骤中,在导电层108A上形成具有开口Ra的掩模图案R1。可以借助于通过膜的涂布或附着进行的树脂层的形成以及通过光刻进行的树脂层的图案化来形成掩模图案R1。
在图3J所示步骤中,通过把掩模图案R1当作掩模,对导电层107A和108A进行图案蚀刻,从而形成导电图案106,导电图案106由第一导电层107和第二导电层108堆叠而成,并与凸点104连接。
例如,第一导电图案107形成为2μm到3μm的厚度,而第二导电图案108形成为30μm到40μm的厚度。然而,这些数值仅仅是实例,本发明不限于这些数值。
在形成导电图案106时,把导电层107A当作供电层,从而便于利用电解电镀。
例如,当通过非电解电镀形成供电层(种晶层)时,需要粗化绝缘层的表面的处理(所谓的去污处理),这转而使形成电镀层的过程复杂。此外,当通过溅射法形成供电层时,需要昂贵的具有真空处理容器的膜生长装置,这会增加制造成本。
同时,本实施例的方法的特征在于,省去了在真空容器中进行的去污处理或溅射处理,并且能够通过简单方法容易地形成供电层(即导电层107A)。因此,通过本实施例的方法简化了制造半导体器件的方法,并缩减了制造成本。
接下来,在图3K所示步骤中,根据需要,在粗化导电图案(铜)106的表面之后,在绝缘层105上形成具有开口109A的阻焊层(绝缘层)109。导电图案106的一部分通过开口109A露出。
在图3L所示步骤中,根据需要,将基板101A的背部研磨成预定厚度。
接下来,在图3M所示步骤中,根据需要,在导电图案106的从开口109A露出的一部分上形成焊料凸点110。此外,将基板101A分块,从而将半导体芯片分离成小块。这样,可以制造出前面参照图1和图2所描述的半导体器件100。
在上述制造方法中,通过减成法形成导电图案106。然而,也可以利用半加成法形成导电图案106。在这种情况下,基本要求是:在上述制造方法中进行与图3A至3G所示步骤有关的处理之后,进行与下述步骤有关的处理,以代替与图3H至3J所示步骤有关的处理。例如,如图5所示,在导电层107A上形成具有开口Rb的掩模图案R2。可以借助于通过膜的涂布或附着进行的树脂层的形成以及通过光刻进行的树脂层的图案化来形成掩模图案R2。
接下来,通过电解电镀在导电层107A的从开口Rb露出的一部分上形成第二导电图案,在电解电镀过程中,把导电层107A当作供电层(种晶层)。在图案电镀之后,剥离掩模图案R2。此外,蚀刻掉由于剥离掩模图案R2而露出的多余的供电层107A。因此,可以形成图3J所示的导电图案106。
在该制造方法中,在图3D和3E所示步骤中,在基板101A上形成绝缘层105之后,将导电层107A附着到绝缘层105上。然而,也可以将由绝缘层105和导电层107A预先堆叠成的层附着到基板101A上。
在这种情况下,基本要求是:在上述制造方法中进行与图3A至3C所示步骤有关的处理之后,进行与下述步骤有关的处理,以代替与图3D和3E所示步骤有关的处理。例如,如图6所示,也可以将堆叠在支撑层111上的绝缘层105和导电层107A附着到基板101A上。
随后,进行与图3F所示的前述步骤及随后步骤有关的处理,从而可以制造出半导体器件100。
到此为止,已经结合优选实施例对本发明进行了说明。然而,本发明不限于上述特定实施例,在所附权利要求书所限定的要旨的范围内可以进行各种修改或变化。
本发明能够提供一种可以以低成本制造的高度可靠的半导体器件以及用于制造半导体器件的方法。
Claims (7)
1.一种用于制造半导体器件的方法,包括:
第一步骤,其在电极片上形成具有凸出部分的凸点,所述电极片形成在基板的与半导体芯片对应的区域中;
第二步骤,其在所述基板上形成绝缘层和导电层;
第三步骤,其挤压所述导电层,从而压制所述导电层上露出的所述凸出部分的末端;
第四步骤,其通过电解电镀形成与所述凸点连接的导电图案,在电解电镀过程中,把所述导电层当作供电层;以及
第五步骤,其将所述基板分离成单独的小块。
2.根据权利要求1所述的用于制造半导体器件的方法,其中,
所述第二步骤包括以下步骤:
在所述基板上形成所述绝缘层;
将堆叠在支撑层上的所述导电层附着到所述绝缘层上;以及
去除所述支撑层。
3.根据权利要求1所述的用于制造半导体器件的方法,其中,
所述第二步骤包括以下步骤:
将堆叠在支撑层上的所述绝缘层和所述导电层附着到所述基板上;以及
去除所述支撑层。
4.根据权利要求1所述的用于制造半导体器件的方法,其中,
在所述第三步骤中,所述绝缘层与所述导电层一起被挤压并加热,以使所述绝缘层固化。
5.根据权利要求1所述的用于制造半导体器件的方法,其中,
在所述第一步骤中,由接合引线形成所述凸点。
6.一种半导体器件,包括:
半导体芯片,其上形成有电极片;
凸点,其形成于所述各个电极片上并具有凸出部分;
绝缘层,其形成于所述半导体芯片上;以及
导电图案,其与所述凸点连接,
其中,所述凸出部分的末端插入所述导电图案中,并且
所述插入的末端被平坦化。
7.根据权利要求6所述的半导体器件,其中,
所述末端在第一导电图案和第二导电图案之间被平坦化,所述第一导电图案和所述第二导电图案构成所述导电图案并且一个堆叠在另一个顶部上。
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JP2006289149A JP2008108849A (ja) | 2006-10-24 | 2006-10-24 | 半導体装置および半導体装置の製造方法 |
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CN101170072A true CN101170072A (zh) | 2008-04-30 |
CN101170072B CN101170072B (zh) | 2011-02-16 |
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CN2007101514892A Expired - Fee Related CN101170072B (zh) | 2006-10-24 | 2007-10-24 | 半导体器件及其制造方法 |
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US (1) | US7786580B2 (zh) |
EP (1) | EP1933377B1 (zh) |
JP (1) | JP2008108849A (zh) |
KR (1) | KR20080036925A (zh) |
CN (1) | CN101170072B (zh) |
DE (1) | DE602007014000D1 (zh) |
TW (1) | TW200820358A (zh) |
Cited By (1)
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CN104599987A (zh) * | 2014-12-19 | 2015-05-06 | 南通富士通微电子股份有限公司 | 半导体圆片级封装工艺 |
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JP5048420B2 (ja) | 2007-08-17 | 2012-10-17 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP5064158B2 (ja) * | 2007-09-18 | 2012-10-31 | 新光電気工業株式会社 | 半導体装置とその製造方法 |
JP5603191B2 (ja) * | 2010-09-28 | 2014-10-08 | 株式会社テラプローブ | 半導体装置の製造方法 |
EP3996571A4 (en) | 2019-07-12 | 2023-06-28 | Bard Access Systems, Inc. | Catheter tracking and placement system including light emitting diode array |
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JP3313547B2 (ja) | 1995-08-30 | 2002-08-12 | 沖電気工業株式会社 | チップサイズパッケージの製造方法 |
JP3801300B2 (ja) * | 1997-03-21 | 2006-07-26 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP3252745B2 (ja) * | 1997-03-31 | 2002-02-04 | 関西日本電気株式会社 | 半導体装置およびその製造方法 |
JP3830125B2 (ja) * | 2000-03-14 | 2006-10-04 | 株式会社東芝 | 半導体装置の製造方法及び半導体装置 |
JP2002050716A (ja) * | 2000-08-02 | 2002-02-15 | Dainippon Printing Co Ltd | 半導体装置及びその作製方法 |
KR100378285B1 (en) * | 2001-06-15 | 2003-03-29 | Dongbu Electronics Co Ltd | Semiconductor package and fabricating method thereof |
WO2003067656A1 (fr) * | 2002-02-06 | 2003-08-14 | Ibiden Co., Ltd. | Carte de montage pour puce a semiconducteur, realisation correspondante, et module a semiconducteur |
JP2004047725A (ja) * | 2002-07-11 | 2004-02-12 | Sumitomo Bakelite Co Ltd | 半導体装置及び製造方法 |
JP2004193497A (ja) * | 2002-12-13 | 2004-07-08 | Nec Electronics Corp | チップサイズパッケージおよびその製造方法 |
JP2004247530A (ja) * | 2003-02-14 | 2004-09-02 | Renesas Technology Corp | 半導体装置及びその製造方法 |
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2006
- 2006-10-24 JP JP2006289149A patent/JP2008108849A/ja active Pending
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2007
- 2007-10-11 US US11/870,743 patent/US7786580B2/en not_active Expired - Fee Related
- 2007-10-18 TW TW096138960A patent/TW200820358A/zh unknown
- 2007-10-19 KR KR1020070105325A patent/KR20080036925A/ko not_active Application Discontinuation
- 2007-10-24 EP EP07020813A patent/EP1933377B1/en not_active Expired - Fee Related
- 2007-10-24 DE DE602007014000T patent/DE602007014000D1/de active Active
- 2007-10-24 CN CN2007101514892A patent/CN101170072B/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN104599987A (zh) * | 2014-12-19 | 2015-05-06 | 南通富士通微电子股份有限公司 | 半导体圆片级封装工艺 |
Also Published As
Publication number | Publication date |
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EP1933377A3 (en) | 2009-10-21 |
CN101170072B (zh) | 2011-02-16 |
US7786580B2 (en) | 2010-08-31 |
TW200820358A (en) | 2008-05-01 |
EP1933377A2 (en) | 2008-06-18 |
JP2008108849A (ja) | 2008-05-08 |
DE602007014000D1 (de) | 2011-06-01 |
US20090001569A1 (en) | 2009-01-01 |
EP1933377B1 (en) | 2011-04-20 |
KR20080036925A (ko) | 2008-04-29 |
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