CN101159270B - 对快闪记忆单元元件执行操作的方法 - Google Patents

对快闪记忆单元元件执行操作的方法 Download PDF

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CN101159270B
CN101159270B CN2007100903361A CN200710090336A CN101159270B CN 101159270 B CN101159270 B CN 101159270B CN 2007100903361 A CN2007100903361 A CN 2007100903361A CN 200710090336 A CN200710090336 A CN 200710090336A CN 101159270 B CN101159270 B CN 101159270B
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吕函庭
徐子轩
赖二琨
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Macronix International Co Ltd
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Abstract

本发明提供一种当浮置栅与控制栅之间的栅极耦合比小于0.4时使用的对快闪记忆单元元件执行操作的方法。需要越过控制栅施加电位。自控制栅注入电子至浮置栅或自浮置栅射出电子至控制栅。由提供于元件中的硅通道的性质决定与注入或射出相关联的操作。使用块体连接式FinFET状结构的元件特别适合于此方法。此方法亦特别适合用于NAND阵列中的记忆单元上。

Description

对快闪记忆单元元件执行操作的方法
技术领域
本发明是有关于一种记忆单元操作方法，且特别是有关于一种对快闪记忆单元元件执行操作的方法。
背景技术
快闪记忆体元件中浮置栅技术的使用是熟知的。通常，提供n或p型半导体的硅通道。浮置栅晶体管由氧化物环绕，以使储存于栅极上的电荷能够保留于彼处。借由通道注入步骤产生程序化(program)以及抹除(erase)操作。在操作期间，电子经受福勒-诺德翰姆隧穿(Fowler-Nordheimtunneling，FN tunneling)且自通道转移至浮置栅，反之亦然。
为提供有效通道注入，须减小栅极注入(电子经由FN隧穿在控制栅与浮置栅之间的转移)的可能性。此借由最大化栅极耦合比(gate coupling ratio，GCR)来实现。栅极耦合比经定义为浮置栅电位与控制栅电位之比。等于1的GCR是最佳的，但大于0.6的GCR对于大多数快闪记忆体元件已足够。
此结果对于较大记忆体元件是良好的，但当此等元件缩小尺寸时，高GCR变得难于维持。详言之，对于NAND快闪记忆体，当节点(node)低于45纳米时，预测GCR会小于0.3。底部隧穿氧化物(bottom tunnel oxide)将不会具有足够大的电场，从而不能允许FN隧穿。此外，未来快闪记忆体元件将需要鳍式场效晶体管(FinFET)状结构来改良元件短通道特性。这些结构具有自然大的通道栅至浮置栅耦合电容，以及因此具有自然低的GCR。
此外，传统快闪记忆体元件阵列中存在浮置栅间耦合(inter-floating gatecoupling)的问题。由于阵列中的记忆单元的密度变大，浮置栅间耦合电容与通道与浮置栅的栅极耦合电容相当。此引起记忆单元之间的干扰，此干扰会劣化快闪记忆体元件的功能性。此外，对栅极氧化物的电场应力影响单元的可靠性以及耐久性。
因此，特别在使用FinFET状结构时，需要以此方式操作浮置栅装置以便使有效FN隧穿至浮置栅。亦需要以此方式操作浮置栅装置以便增加可靠性以及耐久性，且当元件缩小尺寸时减小记忆单元间干扰。
发明内容
当浮置栅与控制栅之间的栅极耦合比小于0.4时，提供一种快闪记忆单元的记忆元件执行操作的方法。需要越过控制栅施加电位。自控制栅注入电子至浮置栅，或自浮置栅射出电子至控制栅。由提供于元件中的硅通道的性质决定与注入或射出相关联的操作。
对于n通道记忆单元，借由自浮置栅射出电子至控制栅来实现写入(writing)。借由自控制栅注入电子至浮置栅来实现抹除。对于p通道记忆单元，借由自控制栅注入电子至浮置栅来实现写入。借由自浮置栅射出电子至控制栅来实现抹除。
具有块体连接式(bulk-tied)FinFET状结构的元件特别适合于此方法，因为此结构产生自然低的栅极耦合比。此方法亦特别适合用于NAND快闪记忆体阵列中的记忆单元上，因为其允许记忆单元的尺寸缩小(scalability)低至20纳米以下。
附图说明
图1展示在供本发明的一较佳实施例中使用的快闪记忆单元的通道长度方向中的典型剖面示意图。
图2A、2B、3A以及3B展示在根据本发明的一较佳实施例的n通道记忆单元与p通道记忆单元中借由-/+FN隧穿的电子注入以及电子射出。
图4展示在供本发明的一较佳实施例中使用的较佳快闪记忆单元的通道宽度方向中的剖面示意图。
图5至图6展示在供根据本发明的一较佳实施例使用的NAND阵列中的两个快闪记忆单元的通道长度以及宽度方向中的剖面示意图。
图7A至图7C以及图8A至图8C展示对供根据本发明的一较佳实施例使用的n通道以及p通道NAND阵列中的记忆单元的操作。
图9A以及9B展示临限电压(以伏为单位)对时间(以秒为单位、对数刻度)的曲线图。
图10展示用于具有不同大小的技术节点的资料，其指示尺寸缩小低至小于20内米。
10：控制栅                    10′：控制栅
12：多晶硅间顶部隧穿介电质    14：电荷储存浮置栅
16：底部栅极氧化物            18：硅通道
18′：硅通道                  20a：n型掺杂源极
20b：p型掺杂源极              22a：n型掺杂漏极
22b：p型掺杂漏极              24：井
24a：p型井                    24b：n型井
26：接面                      28：高密度等离子体氧化物
A：记忆单元                   B：记忆单元
C：记忆单元                    D：记忆单元
F：记忆单元的宽度              GCR：栅极耦合比
αB：浮置栅与通道之间的耦合比
αBL-BL：同一位线上的记忆单元之间的干扰耦合比
αG：栅极耦合比
αWL-WL：同一字线上的记忆单元之间的干扰耦合比
具体实施方式
图1展示在供本发明的实施例中使用的快闪记忆单元的通道长度方向中的典型剖面示意图。图1的左图展示n通道元件。此结构含有硅通道18，硅通道18具有p型井24a以及n型掺杂源极20a及漏极22a。在较佳实施例中，使用块体连接式FinFET结构。此结构亦含有底部栅极氧化物16、电荷储存浮置栅14、多晶硅间(inter-poly)顶部隧穿介电质12，以及控制栅10。图1的右侧展示p通道元件，除了硅通道18含有n型井24b以及p型掺杂源极20b及漏极22b之外，其与n通道元件相同。
底部栅极氧化物16在程序化以及抹除操作期间受到通常小于约7百万伏/厘米(MV/cm)的相对小的电场应力。此避免任何FN隧穿(其防止在现有习知快闪记忆体元件中发生的大量损坏)，且允许更佳的直流(DC)效能。此外，底部栅极氧化物16以及隧穿氧化物(多晶硅间顶部隧穿介电质12)是分离的。此增强了可靠性以及耐久性。
参看图2A以及2B，说明借由-FN隧穿而来自控制栅10的电子注入。参看图2A，借由施加高临限电压(threshold voltage)(例如，-16伏)至控制栅10而在n通道元件上实现抹除。对于等于0.3的GCR，电荷储存浮置栅14的电位为-4.8伏。底部栅极氧化物16中的电场小于8百万伏/厘米，但顶部氧化物(多晶硅间顶部隧穿介电质12)中的电场大于10百万伏/厘米，且因此自控制栅10至电荷储存浮置栅14发生隧穿。展示p通道元件的图2B是类似的。然而，由于硅通道18的性质，元件执行写入操作而非抹除。小于约0.4的GCR对于n通道元件与p通道元件中的电子注入均为较佳。
参看图3A以及3B，说明借由+FN隧穿的来自电荷储存浮置栅14的电子射出。参看图3A，借由施加低临限电压(例如，+16伏)至控制栅10而在n通道元件上实现写入操作。对于等于0.3的GCR，电荷储存浮置栅14的电位将为+4.8伏。底部栅极氧化物16中的电场小于8百万伏/厘米，但顶部氧化物(多晶硅间顶部隧穿介电质12)中的电场大于10百万伏/厘米，且因此自电荷储存浮置栅14至控制栅10发生隧穿。展示p通道元件的图3B是类似的。然而，由于硅通道18的性质，元件执行抹除操作而非写入操作。小于约0.4的GCR对于n通道元件与p通道元件中的电子射出均为较佳。
图4展示在供本发明的一较佳实施例中使用的快闪记忆单元的通道宽度方向中的剖面示意图。高密度等离子体(high density plasma，HDP)氧化物28环绕硅通道18、底部栅极氧化物16以及电荷储存浮置栅14。此高密度等离子体氧化物28使记忆单元与周围记忆单元隔离。硅通道18为FinFET结构。一种获得小GCR的方法为增加硅通道18与电荷储存浮置栅14之间的区域，借此增加两者之间的耦合电容。典型FinFET结构自然地产生硅通道18与电荷储存浮置栅14之间的较大耦合区域，此使其特别适合供根据本发明的一较佳实施例使用。
图5展示在供根据本发明的一较佳实施例使用的NAND阵列中的两个快闪记忆单元的通道长度方向中的剖面示意图。井24沿阵列中的位线(未展示于图5中)延伸。记忆单元共用接面(junction)26。控制栅10的第一角与控制栅10′的对应角之间的距离是2F，其中F是记忆单元的宽度，亦被称为技术节点(technology node)。
图6展示在供根据本发明的一较佳实施例使用的NAND阵列中的两个快闪记忆单元的通道宽度方向中的剖面示意图。HDP氧化物28使通道鳍(硅通道18与18′)彼此隔离。控制栅10沿阵列中的字线(未展示于图6中)延伸。记忆单元共用此控制栅10。硅通道18的第一边缘与硅通道18′的对应边缘之间的距离是2F，其中F如为图5所定义般。
图7A、7B以及7C展示根据本发明的一较佳实施例的n通道NAND阵列中的操作。在图7A中，借由沿邻接字线施加(例如)15伏且将对应位线接地(grounding)来降低记忆单元A的临限电压。发生+FN隧穿且程序化记忆单元A。相邻记忆单元B、C以及D在可接受的程度上具有程序化扰乱(program disturbance)。在图7B中，所有字线上的临限电压增加至(例如)-18伏。发生-FN隧穿且抹除经程序化记忆单元。在图7C中，借由施加适当的电位至对应字线且施加通过电压(pass voltage)至其他字线，以允许读通过电流(read through current)来读出记忆单元A。
图8A、8B以及8C展示根据本发明的一较佳实施例的p通道NAND阵列中的操作。在图8A中，借由沿邻接字线施加(例如)-18伏且将对应位线接地来增加记忆单元A的临限电压。发生-FN隧穿且程序化记忆单元A。相邻记忆单元B、C以及D在可接受的程度上具有程序化扰乱。在图8B中，所有字线上的临限电压降低至(例如)+15伏。发生+FN隧穿且抹除经程序化记忆单元。在图8C中，借由施加适当的电位至对应字线且施加通过电压至其他字线，以允许读通过电流来读出记忆单元A。
图9A以及9B为临限电压(以伏为单位)对时间(以秒为单位、对数刻度)的曲线图。图9A中的曲线展示与来自浮置栅的+FN隧穿相关联的临限电压下降。GCR固定于0.3处，底部栅极氧化物厚度经设定为7纳米，且隧穿氧化物厚度经设定为10纳米。施加三个不同电位至控制栅。结果证明：使用中等范围电压可获得较大记忆窗口(memory window)。图9B中的曲线展示与来自控制栅的-FN隧穿相关联的临限电压增加。模拟设定与图9A中相同的GCR、底部栅极氧化物厚度以及隧穿氧化物厚度参数，且越过控制栅施加相同电位。
图10展示耦合比对技术节点大小(以纳米为单位)的表格以及曲线图。以低至约20纳米的递减节点大小进行模拟。αG为GCR。αB为浮置栅与通道之间的耦合比。αWL-WL为同一字线上的记忆单元之间的干扰耦合比(interference coupling ratio)。αBL-BL为同一位线上的记忆单元之间的干扰耦合比。表格的左侧行中的剩余制程参数定义且标记于图5以及图6中。
来自图10的资料展示利用如以上所述的栅极注入方法的浮置栅元件具有的尺寸缩小低至小于约20纳米的技术节点大小。栅极耦合比可维持于约0.3处。此外，来自邻近记忆单元的干扰耦合比可经限制至0.1以下，以消除记忆单元功能上的大量劣化(deterioration)。
熟习此项技术者应了解：在不脱离以上所述的实施例的广泛发明性概念的情况下，可对其作出改变。因此，当然，本发明并不限于所揭露的特定实施例，而其意欲涵盖在本发明的精神以及范畴内的修改。

Claims (7)

1.一种快闪记忆单元的记忆元件执行操作的方法，其特征在于所述快闪记忆单元具有单一个控制栅与单一个浮置栅，且所述浮置栅与所述控制栅之间的栅极耦合比小于0.4，所述快闪记忆单元的记忆元件执行操作的方法包括：
(a)越过所述控制栅提供电位；以及
(b)自所述控制栅注入电子至所述浮置栅，或自所述浮置栅射出电子至所述控制栅。
2.一种快闪记忆单元的记忆元件执行操作的方法，其特征在于所述快闪记忆单元元件具有块体连接式鳍式场效晶体管状结构的硅通道，具有单一个控制栅与单一个浮置栅，且所述浮置栅与所述控制栅之间的栅极耦合比小于0.4，所述快闪记忆单元的记忆元件执行操作的方法包括以下步骤：
(a)越过所述控制栅提供电位；以及
(b)自所述控制栅注入电子至所述浮置栅，或自所述浮置栅射出电子至所述控制栅。
3.根据权利要求2所述的快闪记忆单元的记忆元件执行操作的方法，其特征在于其中所述硅通道为n通道类型，且步骤(b)更包括：
(i)借由自所述浮置栅射出电子至所述控制栅来程序化记忆单元；以及
(ii)借由自所述控制栅注入电子至所述浮置栅来抹除所述记忆单元。
4.根据权利要求2所述的快闪记忆单元的记忆元件执行操作的方法，其特征在于其中所述硅通道为p通道类型，且步骤(b)更包括：
(i)借由自所述控制栅注入电子至所述浮置栅来程序化记忆单元；以及
(ii)借由自所述浮置栅射出电子至所述控制栅来抹除所述记忆单元。
5.一种对提供于NAND快闪记忆体阵列中的快闪记忆单元的记忆元件执行操作的方法，其特征在于所述快闪记忆单元具有块体连接式鳍式场效晶体管状结构的硅通道，具有单一个控制栅与单一个浮置栅，且所述浮置栅与所述控制栅之间的栅极耦合比小于0.4，所述对提供于NAND快闪记忆体阵列中的快闪记忆单元的记忆元件执行操作的方法包括以下步骤：
(a)越过所述控制栅提供电位；以及
(b)自所述控制栅注入电子至所述浮置栅，或自所述浮置栅射出电子至所述控制栅。
6.根据权利要求5所述的对提供于NAND快闪记忆体阵列中的快闪记忆单元的记忆元件执行操作的方法，其特征在于其中所述硅通道为n通道类型，且步骤(b)更包括：
(i)借由自所述浮置栅射出电子至所述控制栅来程序化记忆单元；以及
(ii)借由自所述控制栅注入电子至所述浮置栅来抹除所述记忆单元。
7.根据权利要求5所述的对提供于NAND快闪记忆体阵列中的快闪记忆单元的记忆元件执行操作的方法，其特征在于其中所述硅通道为p通道类型，且步骤(b)更包括：
(i)借由自所述控制栅注入电子至所述浮置栅来程序化记忆单元；以及
(ii)借由自所述浮置栅射出电子至所述控制栅来抹除所述记忆单元。
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