CN101145384B - 半导体存储器装置及其数据掩蔽方法 - Google Patents

半导体存储器装置及其数据掩蔽方法 Download PDF

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Publication number
CN101145384B
CN101145384B CN2007100969617A CN200710096961A CN101145384B CN 101145384 B CN101145384 B CN 101145384B CN 2007100969617 A CN2007100969617 A CN 2007100969617A CN 200710096961 A CN200710096961 A CN 200710096961A CN 101145384 B CN101145384 B CN 101145384B
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China
Prior art keywords
data
masking information
masking
register
write
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Expired - Fee Related
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CN2007100969617A
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English (en)
Chinese (zh)
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CN101145384A (zh
Inventor
尹相植
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SK Hynix Inc
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Hynix Semiconductor Inc
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Publication of CN101145384A publication Critical patent/CN101145384A/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
CN2007100969617A 2006-09-13 2007-04-19 半导体存储器装置及其数据掩蔽方法 Expired - Fee Related CN101145384B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020060088742 2006-09-13
KR10-2006-0088742 2006-09-13
KR1020060088742A KR100813533B1 (ko) 2006-09-13 2006-09-13 반도체 메모리 장치 및 그 데이터 마스크 방법

Publications (2)

Publication Number Publication Date
CN101145384A CN101145384A (zh) 2008-03-19
CN101145384B true CN101145384B (zh) 2010-05-26

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Family Applications (1)

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CN2007100969617A Expired - Fee Related CN101145384B (zh) 2006-09-13 2007-04-19 半导体存储器装置及其数据掩蔽方法

Country Status (5)

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US (1) US7590009B2 (https=)
JP (1) JP5064939B2 (https=)
KR (1) KR100813533B1 (https=)
CN (1) CN101145384B (https=)
TW (1) TWI336478B (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8006033B2 (en) * 2008-09-09 2011-08-23 Intel Corporation Systems, methods, and apparatuses for in-band data mask bit transmission
KR101090329B1 (ko) * 2010-02-25 2011-12-07 주식회사 하이닉스반도체 메모리장치, 메모리장치의 동작방법 및 제어방법
CN107608716B (zh) * 2011-04-01 2020-12-15 英特尔公司 向量友好指令格式及其执行
CN104011670B (zh) 2011-12-22 2016-12-28 英特尔公司 用于基于向量写掩码的内容而在通用寄存器中存储两个标量常数之一的指令
CN104303141A (zh) * 2011-12-22 2015-01-21 英特尔公司 用于从寄存器提取写掩码的系统、装置和方法
US9135984B2 (en) * 2013-12-18 2015-09-15 Micron Technology, Inc. Apparatuses and methods for writing masked data to a buffer
US10296489B2 (en) 2014-12-27 2019-05-21 Intel Corporation Method and apparatus for performing a vector bit shuffle
US10063474B2 (en) 2015-09-29 2018-08-28 Keysight Technologies Singapore (Holdings) Pte Ltd Parallel match processing of network packets to identify packet data for masking or other actions
KR20170068718A (ko) * 2015-12-09 2017-06-20 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1162819A (zh) * 1995-12-13 1997-10-22 三星电子株式会社 缓冲存储器控制器
CN1345070A (zh) * 2000-09-16 2002-04-17 三星电子株式会社 具有数据掩蔽引脚的半导体存储装置及包括该装置的存储系统
US20050248995A1 (en) * 1997-10-10 2005-11-10 Davis Paul G Memory system and method for two step memory write operations

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0554651A (ja) * 1991-08-29 1993-03-05 Nec Corp 半導体メモリ回路
JPH08249884A (ja) * 1995-03-08 1996-09-27 Sanyo Electric Co Ltd 半導体メモリのライトパービット回路
JP3003613B2 (ja) * 1997-01-31 2000-01-31 日本電気株式会社 半導体記憶装置
DE10128770B4 (de) * 2001-06-13 2014-05-15 Qimonda Ag Verfahren zum Übertragen von Daten in ein Speicherzellenfeld und Schaltungsanordnung
JP2003007060A (ja) * 2001-06-26 2003-01-10 Toshiba Microelectronics Corp 半導体記憶装置及びその制御方法
KR100427037B1 (ko) * 2001-09-24 2004-04-14 주식회사 하이닉스반도체 적응적 출력 드라이버를 갖는 반도체 기억장치
US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
JP4492938B2 (ja) 2004-05-26 2010-06-30 ルネサスエレクトロニクス株式会社 半導体記憶装置及びその動作方法
JP2007242162A (ja) * 2006-03-09 2007-09-20 Toshiba Corp 半導体記憶装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1162819A (zh) * 1995-12-13 1997-10-22 三星电子株式会社 缓冲存储器控制器
US20050248995A1 (en) * 1997-10-10 2005-11-10 Davis Paul G Memory system and method for two step memory write operations
CN1345070A (zh) * 2000-09-16 2002-04-17 三星电子株式会社 具有数据掩蔽引脚的半导体存储装置及包括该装置的存储系统

Also Published As

Publication number Publication date
JP5064939B2 (ja) 2012-10-31
JP2008071477A (ja) 2008-03-27
US7590009B2 (en) 2009-09-15
KR100813533B1 (ko) 2008-03-17
TWI336478B (en) 2011-01-21
CN101145384A (zh) 2008-03-19
US20080062771A1 (en) 2008-03-13
TW200814091A (en) 2008-03-16

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Granted publication date: 20100526

Termination date: 20130419